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Currently, GRA incorrectly assigns GPR for load/store of vector masks as shown below (x11 is assigned to mRegLoad). GRA should be fixed to properly assign appropriate registers for mRegLoad/mRegStore.
On AArch64, GRA for vector opcode (including masks) is disabled by #6802.
Currently, GRA incorrectly assigns GPR for load/store of vector masks as shown below (
x11
is assigned tomRegLoad
). GRA should be fixed to properly assign appropriate registers for mRegLoad/mRegStore.On AArch64, GRA for vector opcode (including masks) is disabled by #6802.
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