- Circuit: 11-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
---|---|---|---|---|---|---|
mul11u_001 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
mul11u_0AG | 0.10 | 0.20 | 98.28 | 1.84 | 28977.591e3 | [Verilog] [C] |
mul11u_0DX | 1.18 | 6.03 | 99.90 | 19.95 | 37290.89e5 | [Verilog] [C] |
- V. Mrazek, S. S. Sarwar, L. Sekanina, Z. Vasicek and K. Roy, "Design of power-efficient approximate multipliers for approximate artificial neural networks," 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2016, pp. 1-7. doi: 10.1145/2966986.2967021