- Circuit: 7-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
---|---|---|---|---|---|---|
mul7u_01L | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
mul7u_03M | 0.03 | 0.092 | 82.61 | 0.98 | 40 | [Verilog] [C] |
mul7u_0DE | 0.051 | 0.19 | 87.35 | 1.44 | 115 | [Verilog] [C] |
mul7u_05K | 0.12 | 0.49 | 92.60 | 2.84 | 613 | [Verilog] [C] |
mul7u_03K | 0.23 | 0.96 | 96.04 | 4.91 | 2248 | [Verilog] [C] |
mul7u_0GG | 0.45 | 1.92 | 97.31 | 8.23 | 8544 | [Verilog] [C] |
mul7u_09J | 0.46 | 1.93 | 97.53 | 10.12 | 8789 | [Verilog] [C] |
mul7u_0B6 | 1.13 | 4.96 | 98.23 | 17.68 | 54027 | [Verilog] [C] |
mul7u_00M | 3.63 | 14.44 | 98.41 | 36.98 | 573266 | [Verilog] [C] |
mul7u_0CA | 5.09 | 19.05 | 98.41 | 46.83 | 11107.118e2 | [Verilog] [C] |
- V. Mrazek, S. S. Sarwar, L. Sekanina, Z. Vasicek and K. Roy, "Design of power-efficient approximate multipliers for approximate artificial neural networks," 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2016, pp. 1-7. doi: 10.1145/2966986.2967021