- Circuit: 8x5-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x5u_4E8 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x5u_0CF | 0.0015 | 0.049 | 3.12 | 0.031 | 0.5 | [Verilog] [C] |
| mul8x5u_00N | 0.0031 | 0.012 | 25.00 | 0.10 | 0.25 | [Verilog] [C] |
| mul8x5u_5R9 | 0.0092 | 0.024 | 50.00 | 0.28 | 1.2 | [Verilog] [C] |
| mul8x5u_44H | 0.027 | 0.073 | 70.31 | 0.79 | 9.2 | [Verilog] [C] |
| mul8x5u_31H | 0.089 | 0.28 | 85.94 | 2.15 | 86 | [Verilog] [C] |
| mul8x5u_5HE | 0.29 | 1.09 | 93.44 | 5.70 | 892 | [Verilog] [C] |
| mul8x5u_2Y9 | 0.94 | 3.77 | 95.37 | 15.13 | 9467 | [Verilog] [C] |
| mul8x5u_0N9 | 3.81 | 15.44 | 96.37 | 38.51 | 154036 | [Verilog] [C] |
| mul8x5u_541 | 24.12 | 96.50 | 96.50 | 100.00 | 70690.462e2 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020