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embmicroembmicro
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6 files changed

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‎flash.cpp

+148
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#include "flash.h"
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void waitBusy() {
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SET(CS_FLASH, LOW);
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SPI.transfer(0x05); //read status register
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while (SPI.transfer(0) & 0x01)
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;
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SET(CS_FLASH, HIGH);
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}
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void SPI_Setup() {
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OUT(SS); // prevent SPI from entering slave mode
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SET(SS, HIGH);
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IN(MISO);
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SPI.begin();
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SPI.setClockDivider(SPI_CLOCK_DIV2);
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SPI.setDataMode(SPI_MODE0);
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SPI.setBitOrder(MSBFIRST);
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}
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void eraseFlash() {
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SPI_Setup();
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SET(CS_FLASH, LOW);
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SPI.transfer(0x06); // Write mode
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SET(CS_FLASH, HIGH);
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SET(CS_FLASH, LOW);
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SPI.transfer(0x01); // Write status reg
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SPI.transfer(0x00); // Disable protection
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SET(CS_FLASH, HIGH);
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SET(CS_FLASH, LOW);
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SPI.transfer(0x06); // Write mode
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SET(CS_FLASH, HIGH);
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SET(CS_FLASH, LOW);
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SPI.transfer(0x60); // Full chip erase
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SET(CS_FLASH, HIGH);
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waitBusy(); // Wait for operation to finish
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SPI.end();
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}
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void writeByteFlash(uint32_t address, uint8_t b) {
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SPI_Setup();
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waitBusy(); // wait for other writes
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SET(CS_FLASH, LOW);
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SPI.transfer(0x06); // Write mode
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SET(CS_FLASH, HIGH);
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SET(CS_FLASH, LOW);
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SPI.transfer(0x02); // Single write
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SPI.transfer(address >> 16);
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SPI.transfer(address >> 8);
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SPI.transfer(address);
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SPI.transfer(b);
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SET(CS_FLASH, HIGH);
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SPI.end();
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}
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void waitHardwareBusy() {
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SET(CS_FLASH, LOW);
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delayMicroseconds(1); // change to 1
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while (digitalRead(MISO) == 0)
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;
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SET(CS_FLASH, HIGH);
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}
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void writeFlash(uint32_t startAddress, uint8_t *data, uint16_t length) {
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if (length < 2) {
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if (length == 1)
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writeByteFlash(startAddress, data[0]);
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return;
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}
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uint16_t pos;
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SPI_Setup();
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waitBusy();
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SET(CS_FLASH, LOW);
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SPI.transfer(0x70); // Hardware EOW detection
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SET(CS_FLASH, HIGH);
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SET(CS_FLASH, LOW);
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SPI.transfer(0x06); // Write Enable
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SET(CS_FLASH, HIGH);
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SET(CS_FLASH, LOW);
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SPI.transfer(0xAD); // Auto-increment write
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SPI.transfer(startAddress >> 16);
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SPI.transfer(startAddress >> 8);
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SPI.transfer(startAddress);
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SPI.transfer(data[0]);
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SPI.transfer(data[1]);
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SET(CS_FLASH, HIGH);
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waitHardwareBusy();
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for (pos = 2; pos <= length - 2; pos += 2) {
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SET(CS_FLASH, LOW);
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SPI.transfer(0xAD); // Auto-increment write
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SPI.transfer(data[pos]);
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SPI.transfer(data[pos + 1]);
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SET(CS_FLASH, HIGH);
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waitHardwareBusy();
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}
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SET(CS_FLASH, LOW);
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SPI.transfer(0x04); // Write Disable
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SET(CS_FLASH, HIGH);
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SET(CS_FLASH, LOW);
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SPI.transfer(0x80); // Disable hardware EOW detection
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SET(CS_FLASH, HIGH);
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if (pos < length)
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writeByteFlash(startAddress + pos, data[pos]);
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}
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void readFlash(volatile uint8_t* buffer, uint32_t address, uint16_t count) {
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SPI_Setup();
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SET(CS_FLASH, LOW);
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SPI.transfer(0x03);
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SPI.transfer(address >> 16);
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SPI.transfer(address >> 8);
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SPI.transfer(address);
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for (uint16_t c = 0; c < count; c++)
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buffer[c] = SPI.transfer(0);
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SET(CS_FLASH, HIGH);
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SPI.end();
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}
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‎flash.h

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/*
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* flash.h
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*
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* Created on: Jan 17, 2014
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* Author: Justin Rajewski
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*/
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#ifndef FLASH_H_
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#define FLASH_H_
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#include "ring_buffer.h"
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#include "hardware.h"
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void SPI_Setup(void);
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/*
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* eraseFlash()
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* This will erase the entire flash
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* memory. This must be called before writing
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* to it to ensure it is in the erased state.
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*/
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void eraseFlash(void);
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/*
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* writeByteFlash(address, byte)
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* This writes one byte to the address
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* specified.
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*/
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void writeByteFlash (uint32_t, uint8_t);
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/*
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* writeFlash(address, data, length)
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* This will write a block of data of size length
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* to the flash starting at the address specified.
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*
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* The starting address MUST be an even number as
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* writes are performed in pairs. If an odd number
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* is given the actual start address will be the
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* address one earlier.
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*/
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void writeFlash(uint32_t, uint8_t*, uint16_t);
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/*
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* readFlash(data, address, length)
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* This reads the flash memory and stores the
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* values into data. Data must be an array
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* of size length or more.
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*/
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void readFlash(volatile uint8_t*, uint32_t, uint16_t);
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#endif /* FLASH_H_ */
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‎fpga.ino

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inline void enableDataBus() {
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FPGA_BUS_DDR = 0xFF;
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}
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void initLoad() {
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SET(INIT, HIGH);
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SET(CCLK, LOW);
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SET(PROGRAM, LOW);
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enableDataBus();
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}
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void startLoad() {
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SET(CCLK, LOW);
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SET(PROGRAM, LOW);
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delay(1);
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SET(PROGRAM, HIGH);
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while (!VALUE(INIT));
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}
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void sendByte(uint8_t b) {
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FPGA_BUS_PORT = b;
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SET(CCLK, HIGH);
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SET(CCLK, LOW);
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}
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void sendExtraClocks() {
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FPGA_BUS_PORT = 0xff;
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for (int i = 0; i < 10; i++) {
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SET(CCLK, HIGH);
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SET(CCLK, LOW);
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}
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}
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void loadFromFlash() {
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uint32_t lastAddr = 0;
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initLoad();
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startLoad();
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readFlash(loadBuffer, 0, 5);
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if (loadBuffer[0] != 0xaa){
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return;
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}
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for (uint8_t k = 0; k < 4; k++) {
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lastAddr |= (uint32_t) loadBuffer[k + 1] << (k * 8);
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}
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uint32_t curAddr = 5;
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while (curAddr + 256 < lastAddr) {
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readFlash(loadBuffer, curAddr, 256);
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enableDataBus();
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for (uint16_t i = 0; i < 256; i++) {
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sendByte(loadBuffer[i]);
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}
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curAddr += 256;
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}
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if (curAddr < lastAddr) {
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uint8_t rem = lastAddr - curAddr;
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readFlash(loadBuffer, curAddr, rem);
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enableDataBus();
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for (uint8_t i = 0; i < rem; i++) {
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sendByte(loadBuffer[i]);
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}
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}
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sendExtraClocks();
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}

‎hardware.h

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#ifndef HARDWARE_H_
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#define HARDWARE_H_
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#include <avr/io.h>
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#include <avr/wdt.h>
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#include <avr/power.h>
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#include <avr/interrupt.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "Arduino.h"
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#include <SPI.h>
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#define FPGA_BUS_PORT PORTB
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#define FPGA_BUS_DDR DDRB
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#define FPGA_BUS_PIN PINB
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#define FPGA_BUS_MASK 0xFF
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#define FPGA_BUS_OFFSET 0
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#define ADC_BUS_PORT PORTB
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#define ADC_BUS_DDR DDRB
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#define ADC_BUS_PIN PINB
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#define ADC_BUS_MASK 0xF0
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#define ADC_BUS_OFFSET 4
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#define CCLK_N 3
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#define CS_FLASH_N 2
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#define INIT_N 30
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#define TX_BUSY_N 30
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#define DONE_N 5
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#define PROGRAM_N 13
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#define CCLK_PORT PORTD
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#define CCLK_DDR DDRD
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#define CCLK_BIT PD0
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#define CCLK_PIN PIND
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#define CS_FLASH_PORT PORTD
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#define CS_FLASH_DDR DDRD
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#define CS_FLASH_BIT PD1
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#define CS_FLASH_PIN PIND
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#define INIT_PORT PORTD
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#define INIT_DDR DDRD
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#define INIT_BIT PD5
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#define INIT_PIN PIND
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#define TX_BUSY_PORT PORTD
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#define TX_BUSY_DDR DDRD
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#define TX_BUSY_BIT PD5
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#define TX_BUSY_PIN PIND
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#define DONE_PORT PORTC
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#define DONE_DDR DDRC
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#define DONE_BIT PC6
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#define DONE_PIN PINC
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#define PROGRAM_PORT PORTC
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#define PROGRAM_DDR DDRC
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#define PROGRAM_BIT PC7
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#define PROGRAM_PIN PINC
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#define MISO_PORT PORTB
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#define MISO_DDR DDRB
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#define MISO_BIT PB3
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#define MISO_PIN PINB
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#define SS_PORT PORTB
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#define SS_DDR DDRB
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#define SS_BIT PB0
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#define SS_PIN PINB
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#define SET(p, v) p ## _PORT = (p ## _PORT & ~(1 << p ## _BIT)) | (v << p ## _BIT)
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#define VALUE(p) (p ## _PIN & (1 << p ## _BIT))
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#define OUT(p) p ## _DDR |= (1 << p ## _BIT)
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#define IN(p) p ## _DDR &= ~(1 << p ## _BIT)
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#define LINESTATE_DTR 1
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#endif /* HARDWARE_H_ */

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