AxSIZE mismatch?

[TheZoq2]

When generating a ram controller with an Axi interface, the awsize and arsize ports are 4 bits wide

    input  wire    [3:0] user_port_axi_0_awsize,

    input  wire    [3:0] user_port_axi_0_arsize,

but according to section A4.1.1, those fields should be 3 bits wide. This also seems to be how they are used in the generated verilog

wire    [2:0] main_aw_payload_size;
assign main_aw_payload_size = user_port_axi_0_awsize;

Is this intentional?

[TheZoq2]

Looking at the ax_description in litex/soc/interconnect/axi/axi_full, it seems like the size depends on whether or not axi3 or axi4 is used

def ax_description(address_width, version="axi4"):
    len_width  = {"axi3":4, "axi4":8}[version]
    size_width = {"axi3":4, "axi4":3}[version]
    lock_width = {"axi3":2, "axi4":1}[version]
    # * present for interconnect with others cores but not used by LiteX.
    return [
        ("addr",   address_width),   # Address Width.
        ("burst",  2),               # Burst type.
        ("len",    len_width),       # Number of data (-1) transfers (up to 16 (AXI3) or 256 (AXI4)).
        ("size",   size_width),      # Number of bytes (-1) of each data transfer (up to 1024-bit).
        ("lock",   lock_width),      # *
        ("prot",   3),               # *
        ("cache",  4),               # *
        ("qos",    4),               # *
        ("region", 4),               # *
    ]

But reading the spec, I can't find where it says that axi3 should have size 4. I also can't find where litedram requests axi3 and/or size 4 🤔