LiteSATA Bench not initializing on Nexys Video

[md-raz]

I am trying to run the LiteSATA bench file provided for the Nexys Video (xc7a200t-sbg484-1). The board is new and does not have anything connected to it, and I am building / loading the bitstream to the FPGA with the following over USB programming interface:

./nexys_video.py --pll-refclk --build --load from the /litex/litesata/bench directory.

Since there is no external clock provided for the transceiver, I am attempting to use the internal 150 MHz PLL reference clock. I have tried this with both Gen 1 and Gen2 SATA. The bitstream is built and loaded successfully using the Vivado toolchain, however once the program starts, only a single LED0 lights up, signifying that the TX, RX, and Ready signals are never initialized. I am unsure as to why SATA does not initialize, is an external 150MHz clock required? Does a hard drive need to be attached to the SATA RX/TX lines for the SATA core to initialize?

I have attached my bench file, along with the terminal output below. Please let me know if there is a solution discernible from these, or if you need more information. Thanks!

nexys_video_bench.txt
terminal_output-Nexys_Video.txt