The 16-bit RISC Machine project focused on designing and implementing a Central Processing Unit (CPU) architecture using SystemVerilog. This included a Finite State Machine (FSM) controller, instruction decoder, Arithmetic Logic Unit (ALU), memory unit, and program counter.
To validate the correctness of each individual component and the CPU as a complete system, my partner and I wrote a set of testbenches using SystemVerilog and executed them in ModelSim. This allowed us to identify failures in specific modules and test the integration of the CPU components.
The code is available uppon request. Please send an email to eomielan@gmail.com or ljiawen49@gmail.com.
