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if (ifmap[6] == 1) begin
p = p + ({{24{1'b1}}, (ifmap[7]?((~((~(ifmap-1)) << 1))+1):(ifmap<<1))})<<i;
end else begin
p = p + ({24'b0, (ifmap[7]?((~((~(ifmap-1)) << 1))+1):(ifmap<<1))})<<i;
end
$display("\\011 = >2/");
end
where ifmap is a input, but [ericsonj ](https://github.com/ericsonj)/ [verilog-format](https://github.com/ericsonj/verilog-format) will see it as if and map, which is not correct!
the out come is like:
if (if map[6] == 1) begin
p = p + ({{24{1'b1}}, (ifmap[7]?((~((~(ifmap-1)) << 1))+1):(ifmap<<1))})<<i;
end else begin
p = p + ({24'b0, (ifmap[7]?((~((~(ifmap-1)) << 1))+1):(ifmap<<1))})<<i;
end
$display("\\011 = >2/");
end
the correct version need to be like if (ifmap[6] == 1) begin
The text was updated successfully, but these errors were encountered:
for example i have a code:
where
ifmap
is ainput
, but[ericsonj ](https://github.com/ericsonj)/ [verilog-format](https://github.com/ericsonj/verilog-format)
will see it asif
andmap
, which is not correct!the out come is like:
the correct version need to be like
if (ifmap[6] == 1) begin
The text was updated successfully, but these errors were encountered: