ci(pre-commit): Apply automatic fixes

Author: pre-commit-ci-lite[bot]

cores/esp32/HardwareSerial.cpp

@@ -623,7 +623,7 @@ bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
     log_e("No Clock Source change was done. This function must be called before beginning UART%d.", _uart_nr);
     return false;
   }
-  return uartSetClockSource(_uart_nr, (uart_sclk_t) clkSrc);
+  return uartSetClockSource(_uart_nr, (uart_sclk_t)clkSrc);
 }
 // minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.
 // LP UART has FIFO of 16 bytes

cores/esp32/HardwareSerial.h

@@ -96,26 +96,26 @@ typedef enum {
   UART_PARITY_ERROR
 } hardwareSerial_error_t;
 
-  typedef enum {
-    UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT,
+typedef enum {
+  UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT,
 #if SOC_UART_SUPPORT_APB_CLK
-    UART_CLK_SRC_APB = UART_SCLK_APB,
+  UART_CLK_SRC_APB = UART_SCLK_APB,
 #endif
 #if SOC_UART_SUPPORT_PLL_F40M_CLK
-    UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M,
+  UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M,
 #elif SOC_UART_SUPPORT_PLL_F80M_CLK
-    UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M,
+  UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M,
 #elif CONFIG_IDF_TARGET_ESP32H2
-    UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M,
+  UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M,
 #endif
 #if SOC_UART_SUPPORT_XTAL_CLK
-    UART_CLK_SRC_XTAL = UART_SCLK_XTAL,
+  UART_CLK_SRC_XTAL = UART_SCLK_XTAL,
 #endif
 #if SOC_UART_SUPPORT_RTC_CLK
-    UART_CLK_SRC_RTC = UART_SCLK_RTC,
+  UART_CLK_SRC_RTC = UART_SCLK_RTC,
 #endif
 #if SOC_UART_SUPPORT_REF_TICK
-    UART_CLK_SRC_REF_TICK = UART_SCLK_REF_TICK,
+  UART_CLK_SRC_REF_TICK = UART_SCLK_REF_TICK,
 #endif
 } SerialClkSrc;
 
@@ -380,6 +380,7 @@ class HardwareSerial : public Stream {
   bool setClockSource(SerialClkSrc clkSrc);
   size_t setRxBufferSize(size_t new_size);
   size_t setTxBufferSize(size_t new_size);
+
 protected:
   uint8_t _uart_nr;
   uart_t *_uart;

cores/esp32/esp32-hal-uart.c

@@ -665,23 +665,23 @@ uart_t *uartBegin(
   rxfifo_full_thrhd = uart_config.rx_flow_ctrl_thresh;  // makes sure that it will be set correctly in the struct
   uart_config.baud_rate = baudrate;
 #if SOC_UART_LP_NUM >= 1
-  if (uart_nr >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
+  if (uart_nr >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
     if (uart->_uart_clock_source > 0) {
-      uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
+      uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart_nr, uart->_uart_clock_source);
     } else {
       uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT;  // use default LP clock
       log_v("Setting UART%d to Default LP clock source", uart_nr);
     }
   } else
-#endif // SOC_UART_LP_NUM >= 1
+#endif  // SOC_UART_LP_NUM >= 1
   {
     if (uart->_uart_clock_source >= 0) {
-      uart_config.source_clk = (soc_module_clk_t) uart->_uart_clock_source;  // use user defined HP UART clock
+      uart_config.source_clk = (soc_module_clk_t)uart->_uart_clock_source;  // use user defined HP UART clock
       log_v("Setting UART%d to user defined HP clock source (%d) ", uart_nr, uart->_uart_clock_source);
-    } else {    
-    // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
-    // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
+    } else {
+      // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
+      // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
 #if SOC_UART_SUPPORT_XTAL_CLK
       uart_config.source_clk = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
       log_v("Setting UART%d to use XTAL clock", uart_nr);
@@ -697,7 +697,7 @@ uart_t *uartBegin(
       // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
       uart_config.source_clk = UART_SCLK_DEFAULT;  // baudrate may change with the APB Frequency!
       log_v("Setting UART%d to use DEFAULT clock", uart_nr);
-#endif // SOC_UART_SUPPORT_XTAL_CLK
+#endif  // SOC_UART_SUPPORT_XTAL_CLK
     }
   }
 
@@ -997,23 +997,23 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
   soc_module_clk_t newClkSrc = UART_SCLK_DEFAULT;
   int8_t previousClkSrc = uart->_uart_clock_source;
 #if SOC_UART_LP_NUM >= 1
-  if (uart->num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
+  if (uart->num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
     if (uart->_uart_clock_source > 0) {
-      newClkSrc = (soc_periph_lp_uart_clk_src_t) uart->_uart_clock_source;  // use user defined LP UART clock
+      newClkSrc = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source;  // use user defined LP UART clock
       log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc);
     } else {
       newClkSrc = LP_UART_SCLK_DEFAULT;  // use default LP clock
       log_v("Setting UART%d to Default LP clock source", uart->num);
     }
-  } else 
-#endif // SOC_UART_LP_NUM >= 1
+  } else
+#endif  // SOC_UART_LP_NUM >= 1
   {
     if (uart->_uart_clock_source >= 0) {
-      newClkSrc = (soc_module_clk_t) uart->_uart_clock_source;  // use user defined HP UART clock
+      newClkSrc = (soc_module_clk_t)uart->_uart_clock_source;  // use user defined HP UART clock
       log_v("Setting UART%d to use HP clock source (%d) ", uart->num, newClkSrc);
-    } else {    
-    // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
-    // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
+    } else {
+      // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
+      // therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
 #if SOC_UART_SUPPORT_XTAL_CLK
       newClkSrc = UART_SCLK_XTAL;  // valid for C2, S3, C3, C6, H2 and P4
       log_v("Setting UART%d to use XTAL clock", uart->num);
@@ -1029,7 +1029,7 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
       // Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
       // using newClkSrc = UART_SCLK_DEFAULT as defined in the variable declaration
       log_v("Setting UART%d to use DEFAULT clock", uart->num);
-#endif // SOC_UART_SUPPORT_XTAL_CLK
+#endif  // SOC_UART_SUPPORT_XTAL_CLK
     }
   }
   UART_MUTEX_LOCK();
@@ -1133,7 +1133,7 @@ bool uartSetMode(uart_t *uart, uart_mode_t mode) {
   return retCode;
 }
 
-// this function will set the uart clock source 
+// this function will set the uart clock source
 // it must be called before uartBegin(), otherwise it won't change any thing.
 bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc) {
   if (uartNum >= SOC_UART_NUM) {
@@ -1144,15 +1144,10 @@ bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc) {
 #if SOC_UART_LP_NUM >= 1
   if (uart->num >= SOC_UART_HP_NUM) {
     switch (clkSrc) {
-      case UART_SCLK_XTAL:
-        uart->_uart_clock_source = LP_UART_SCLK_XTAL_D2;
-        break;
-      case UART_SCLK_RTC:
-        uart->_uart_clock_source = LP_UART_SCLK_LP_FAST;
-        break;
+      case UART_SCLK_XTAL:    uart->_uart_clock_source = LP_UART_SCLK_XTAL_D2; break;
+      case UART_SCLK_RTC:     uart->_uart_clock_source = LP_UART_SCLK_LP_FAST; break;
       case UART_SCLK_DEFAULT:
-      default:
-        uart->_uart_clock_source = LP_UART_SCLK_DEFAULT;
+      default:                uart->_uart_clock_source = LP_UART_SCLK_DEFAULT;
     }
   } else
 #endif