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shanggl
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Merge branch '4.3.1-bsp-fix-i2c' into 4.3-bsp-rebase
2 parents 08d7e05 + 61341f1 commit 928087d

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Diff for: ‎lib/main/AT32F43x/cmsis/cm4/at32f435_437.h

+33-33
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,17 @@
11
/**
22
**************************************************************************
33
* @file at32f435_437.h
4-
* @version v2.0.5
5-
* @date 2022-02-11
4+
* @version v2.1.0
5+
* @date 2022-08-16
66
* @brief at32f435_437 header file
77
**************************************************************************
88
* Copyright notice & Disclaimer
99
*
10-
* The software Board Support Package (BSP) that is made available to
11-
* download from Artery official website is the copyrighted work of Artery.
12-
* Artery authorizes customers to use, copy, and distribute the BSP
13-
* software and its related documentation for the purpose of design and
14-
* development in conjunction with Artery microcontrollers. Use of the
10+
* The software Board Support Package (BSP) that is made available to
11+
* download from Artery official website is the copyrighted work of Artery.
12+
* Artery authorizes customers to use, copy, and distribute the BSP
13+
* software and its related documentation for the purpose of design and
14+
* development in conjunction with Artery microcontrollers. Use of the
1515
* software is governed by this copyright notice and the following disclaimer.
1616
*
1717
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -43,7 +43,7 @@ extern "C" {
4343
/** @addtogroup AT32F435_437
4444
* @{
4545
*/
46-
46+
4747
/** @addtogroup Library_configuration_section
4848
* @{
4949
*/
@@ -84,8 +84,8 @@ extern "C" {
8484
#ifndef USE_STDPERIPH_DRIVER
8585
/**
8686
* @brief comment the line below if you will not use the peripherals drivers.
87-
* in this case, these drivers will not be included and the application code will
88-
* be based on direct access to peripherals registers
87+
* in this case, these drivers will not be included and the application code will
88+
* be based on direct access to peripherals registers
8989
*/
9090
#ifdef _RTE_
9191
#include "RTE_Components.h"
@@ -99,8 +99,8 @@ extern "C" {
9999
* @brief at32f435_437 standard peripheral library version number
100100
*/
101101
#define __AT32F435_437_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
102-
#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
103-
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x05) /*!< [15:8] minor version */
102+
#define __AT32F435_437_LIBRARY_VERSION_MIDDLE (0x01) /*!< [23:16] middle version */
103+
#define __AT32F435_437_LIBRARY_VERSION_MINOR (0x00) /*!< [15:8] minor version */
104104
#define __AT32F435_437_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
105105
#define __AT32F435_437_LIBRARY_VERSION ((__AT32F435_437_LIBRARY_VERSION_MAJOR << 24) | \
106106
(__AT32F435_437_LIBRARY_VERSION_MIDDLE << 16) | \
@@ -232,13 +232,13 @@ typedef enum IRQn
232232
TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
233233
TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
234234
TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
235-
DMA2_Channel1_IRQn = 108, /*!< dma1 channel 1 global interrupt */
236-
DMA2_Channel2_IRQn = 109, /*!< dma1 channel 2 global interrupt */
237-
DMA2_Channel3_IRQn = 110, /*!< dma1 channel 3 global interrupt */
238-
DMA2_Channel4_IRQn = 111, /*!< dma1 channel 4 global interrupt */
239-
DMA2_Channel5_IRQn = 112, /*!< dma1 channel 5 global interrupt */
240-
DMA2_Channel6_IRQn = 113, /*!< dma1 channel 6 global interrupt */
241-
DMA2_Channel7_IRQn = 114, /*!< dma1 channel 7 global interrupt */
235+
DMA2_Channel1_IRQn = 108, /*!< dma2 channel 1 global interrupt */
236+
DMA2_Channel2_IRQn = 109, /*!< dma2 channel 2 global interrupt */
237+
DMA2_Channel3_IRQn = 110, /*!< dma2 channel 3 global interrupt */
238+
DMA2_Channel4_IRQn = 111, /*!< dma2 channel 4 global interrupt */
239+
DMA2_Channel5_IRQn = 112, /*!< dma2 channel 5 global interrupt */
240+
DMA2_Channel6_IRQn = 113, /*!< dma2 channel 6 global interrupt */
241+
DMA2_Channel7_IRQn = 114, /*!< dma2 channel 7 global interrupt */
242242
#endif
243243

244244
#if defined (AT32F437xx)
@@ -313,13 +313,13 @@ typedef enum IRQn
313313
TMR20_OVF_IRQn = 105, /*!< tmr20 overflow interrupt */
314314
TMR20_TRG_HALL_IRQn = 106, /*!< tmr20 trigger and hall interrupt */
315315
TMR20_CH_IRQn = 107, /*!< tmr20 channel interrupt */
316-
DMA2_Channel1_IRQn = 108, /*!< dma1 channel 1 global interrupt */
317-
DMA2_Channel2_IRQn = 109, /*!< dma1 channel 2 global interrupt */
318-
DMA2_Channel3_IRQn = 110, /*!< dma1 channel 3 global interrupt */
319-
DMA2_Channel4_IRQn = 111, /*!< dma1 channel 4 global interrupt */
320-
DMA2_Channel5_IRQn = 112, /*!< dma1 channel 5 global interrupt */
321-
DMA2_Channel6_IRQn = 113, /*!< dma1 channel 6 global interrupt */
322-
DMA2_Channel7_IRQn = 114, /*!< dma1 channel 7 global interrupt */
316+
DMA2_Channel1_IRQn = 108, /*!< dma2 channel 1 global interrupt */
317+
DMA2_Channel2_IRQn = 109, /*!< dma2 channel 2 global interrupt */
318+
DMA2_Channel3_IRQn = 110, /*!< dma2 channel 3 global interrupt */
319+
DMA2_Channel4_IRQn = 111, /*!< dma2 channel 4 global interrupt */
320+
DMA2_Channel5_IRQn = 112, /*!< dma2 channel 5 global interrupt */
321+
DMA2_Channel6_IRQn = 113, /*!< dma2 channel 6 global interrupt */
322+
DMA2_Channel7_IRQn = 114, /*!< dma2 channel 7 global interrupt */
323323
#endif
324324

325325
} IRQn_Type;
@@ -334,7 +334,7 @@ typedef enum IRQn
334334

335335
/** @addtogroup Exported_types
336336
* @{
337-
*/
337+
*/
338338

339339
typedef int32_t INT32;
340340
typedef int16_t INT16;
@@ -376,7 +376,7 @@ typedef __I uint16_t vuc16; /*!< read only */
376376
typedef __I uint8_t vuc8; /*!< read only */
377377

378378
typedef enum {RESET = 0, SET = !RESET} flag_status;
379-
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
379+
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
380380
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
381381

382382
/**
@@ -480,7 +480,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
480480
#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
481481
#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
482482
#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
483-
/* ahb bus base address */
483+
/* ahb bus base address */
484484
#define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
485485
#define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
486486
#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
@@ -557,7 +557,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
557557
#define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
558558
#define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
559559
#define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
560-
560+
561561
#define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
562562
#define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
563563
#define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
@@ -640,7 +640,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
640640
#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
641641
#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
642642
#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
643-
/* ahb bus base address */
643+
/* ahb bus base address */
644644
#define OTGFS2_BASE (AHBPERIPH1_BASE + 0x20000)
645645
#define SDIO1_BASE (AHBPERIPH1_BASE + 0xC400)
646646
#define EMAC_BASE (AHBPERIPH1_BASE + 0x8000)
@@ -718,7 +718,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
718718
#define EDMA_STREAM6_2D_BASE (EDMA_2D_BASE + 0x002C)
719719
#define EDMA_STREAM7_2D_BASE (EDMA_2D_BASE + 0x0034)
720720
#define EDMA_STREAM8_2D_BASE (EDMA_2D_BASE + 0x003C)
721-
721+
722722
#define EDMA_LL_BASE (EDMA_BASE + 0x00D0)
723723
#define EDMA_STREAM1_LL_BASE (EDMA_LL_BASE + 0x0004)
724724
#define EDMA_STREAM2_LL_BASE (EDMA_LL_BASE + 0x0008)
@@ -760,7 +760,7 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
760760
/**
761761
* @}
762762
*/
763-
763+
764764
/**
765765
* @}
766766
*/

Diff for: ‎lib/main/AT32F43x/cmsis/cm4/core_support/arm_helium_utils.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
180180
while (blkCnt > 0U)
181181
{
182182
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
183-
vstrwq(pDataDestR, vecIn);
183+
vstrwq(pDataDestR, vecIn);
184184
pDataDestR += 4;
185185
pDataC = pDataC + srcCols * 4;
186186
/*

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