A RISC-V based uC written in verilog and a hardware design that can be used with it.
For most of the projects documentation have a look at the github wiki.
This project was written/created with the following utilities:
- Yosys (For synthesis)
- nextpnr (For routing and placing)
- prjtrellis (Bitstream documentation for the LATTICE LFE5U-12F)
- icarus verilog (Used for simulation)
- gtkwave (For opening the produced waveforms of the simulation as a vcd file)
- freecad (Used for 3d modeling)
- src -> Holds all the verilog src files that are synthesizeable.
- tests -> Consists of all verilog testbenches (for each model one with the naming convention
test_<name>.v). - designs -> Contains all of the 3d models of the project.