ARCv3: MMUv4 enable hacks #2: pgd and pte are 64-bits

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

Author: vineetgarc

arch/arc/include/asm/asm-macro-32-bit.h

@@ -6,7 +6,7 @@
 .endm
 .endr
 
-.irp    aa,,.as
+.irp    aa,,.as,.aw
 .macro LDR\aa d, s, off=0
 	ld\aa  \d, [\s, \off]
 .endm

arch/arc/include/asm/asm-macro-64-bit.h

@@ -6,7 +6,7 @@
 .endm
 .endr
 
-.irp    aa,,.as
+.irp    aa,,.as,.aw
 .macro LDR\aa d, s, off=0
 	ldl\aa \d, [\s, \off]
 .endm

arch/arc/mm/tlbex.S

@@ -169,7 +169,7 @@ ex_saved_reg1:
 #endif
 
 	lsr     r0, r2, PGDIR_SHIFT     ; Bits for indexing into PGD
-	ld.as   r3, [r1, r0]            ; PGD entry corresp to faulting addr
+	LDR.as  r3, r1, r0              ; PGD entry corresp to faulting addr
 	tst	r3, r3
 	bz	do_slow_path_pf         ; if no Page Table, do page fault
 
@@ -205,7 +205,7 @@ ex_saved_reg1:
 	; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
 	; (3) z = (pgtbl + y * 4)
 
-#ifdef CONFIG_ARC_HAS_PAE40
+#if defined(CONFIG_ARC_HAS_PAE40) || defined(CONFIG_ISA_ARCV3)
 #define PTE_SIZE_LOG	3	/* 8 == 2 ^ 3 */
 #else
 #define PTE_SIZE_LOG	2	/* 4 == 2 ^ 2 */
@@ -214,7 +214,7 @@ ex_saved_reg1:
 	; multiply in step (3) above avoided by shifting lesser in step (1)
 	lsr     r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
 	and     r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
-	ld.aw   r0, [r1, r0]            ; r0: PTE (lower word only for PAE40)
+	LDR.aw  r0, r1, r0              ; r0: PTE (lower word only for PAE40)
 					; r1: PTE ptr
 
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