You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
This causes VCS compilation to fail because the module instantiation is missing these 0-width ports, but they are included in the test harness DUT instantiation:
0-width wires in the top-level I/O are correctly removed in the verilator cpp test harness, but are included in the verilog test harness used by VCS:
This causes VCS compilation to fail because the module instantiation is missing these 0-width ports, but they are included in the test harness DUT instantiation:
Module definition:
The text was updated successfully, but these errors were encountered: