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cmd/asm,cmd/internal/obj/riscv: add atomic memory operation instructions
Use instructions in place of currently used defines. Updates #36765 Change-Id: I00bb59e77b1aace549d7857cc9721ba2cb4ac6ca Reviewed-on: https://go-review.googlesource.com/c/go/+/220541 Reviewed-by: Cherry Zhang <cherryyz@google.com>
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4 files changed

+57
-22
lines changed

4 files changed

+57
-22
lines changed

‎src/cmd/asm/internal/arch/riscv64.go

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,10 @@ import (
1818
// handling.
1919
func IsRISCV64AMO(op obj.As) bool {
2020
switch op {
21-
case riscv.ASCW, riscv.ASCD:
21+
case riscv.ASCW, riscv.ASCD, riscv.AAMOSWAPW, riscv.AAMOSWAPD, riscv.AAMOADDW, riscv.AAMOADDD,
22+
riscv.AAMOANDW, riscv.AAMOANDD, riscv.AAMOORW, riscv.AAMOORD, riscv.AAMOXORW, riscv.AAMOXORD,
23+
riscv.AAMOMINW, riscv.AAMOMIND, riscv.AAMOMINUW, riscv.AAMOMINUD,
24+
riscv.AAMOMAXW, riscv.AAMOMAXD, riscv.AAMOMAXUW, riscv.AAMOMAXUD:
2225
return true
2326
}
2427
return false

‎src/cmd/asm/internal/asm/testdata/riscvenc.s

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -163,6 +163,26 @@ start:
163163
SCW X5, (X6), X7 // af23531c
164164
SCD X5, (X6), X7 // af33531c
165165

166+
// 8.3: Atomic Memory Operations
167+
AMOSWAPW X5, (X6), X7 // af23530c
168+
AMOSWAPD X5, (X6), X7 // af33530c
169+
AMOADDW X5, (X6), X7 // af235304
170+
AMOADDD X5, (X6), X7 // af335304
171+
AMOANDW X5, (X6), X7 // af235364
172+
AMOANDD X5, (X6), X7 // af335364
173+
AMOORW X5, (X6), X7 // af235344
174+
AMOORD X5, (X6), X7 // af335344
175+
AMOXORW X5, (X6), X7 // af235324
176+
AMOXORD X5, (X6), X7 // af335324
177+
AMOMAXW X5, (X6), X7 // af2353a4
178+
AMOMAXD X5, (X6), X7 // af3353a4
179+
AMOMAXUW X5, (X6), X7 // af2353e4
180+
AMOMAXUD X5, (X6), X7 // af3353e4
181+
AMOMINW X5, (X6), X7 // af235384
182+
AMOMIND X5, (X6), X7 // af335384
183+
AMOMINUW X5, (X6), X7 // af2353c4
184+
AMOMINUD X5, (X6), X7 // af3353c4
185+
166186
// 10.1: Base Counters and Timers
167187
RDCYCLE X5 // f32200c0
168188
RDTIME X5 // f32210c0
@@ -282,7 +302,7 @@ start:
282302
// These jumps can get printed as jumps to 2 because they go to the
283303
// second instruction in the function (the first instruction is an
284304
// invisible stack pointer adjustment).
285-
JMP start // JMP 2 // 6ff09fcb
305+
JMP start // JMP 2 // 6ff01fc7
286306
JMP (X5) // 67800200
287307
JMP 4(X5) // 67804200
288308

‎src/cmd/internal/obj/riscv/obj.go

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1591,6 +1591,26 @@ var encodings = [ALAST & obj.AMask]encoding{
15911591
ASCW & obj.AMask: rIIIEncoding,
15921592
ASCD & obj.AMask: rIIIEncoding,
15931593

1594+
// 8.3: Atomic Memory Operations
1595+
AAMOSWAPW & obj.AMask: rIIIEncoding,
1596+
AAMOSWAPD & obj.AMask: rIIIEncoding,
1597+
AAMOADDW & obj.AMask: rIIIEncoding,
1598+
AAMOADDD & obj.AMask: rIIIEncoding,
1599+
AAMOANDW & obj.AMask: rIIIEncoding,
1600+
AAMOANDD & obj.AMask: rIIIEncoding,
1601+
AAMOORW & obj.AMask: rIIIEncoding,
1602+
AAMOORD & obj.AMask: rIIIEncoding,
1603+
AAMOXORW & obj.AMask: rIIIEncoding,
1604+
AAMOXORD & obj.AMask: rIIIEncoding,
1605+
AAMOMAXW & obj.AMask: rIIIEncoding,
1606+
AAMOMAXD & obj.AMask: rIIIEncoding,
1607+
AAMOMAXUW & obj.AMask: rIIIEncoding,
1608+
AAMOMAXUD & obj.AMask: rIIIEncoding,
1609+
AAMOMINW & obj.AMask: rIIIEncoding,
1610+
AAMOMIND & obj.AMask: rIIIEncoding,
1611+
AAMOMINUW & obj.AMask: rIIIEncoding,
1612+
AAMOMINUD & obj.AMask: rIIIEncoding,
1613+
15941614
// 10.1: Base Counters and Timers
15951615
ARDCYCLE & obj.AMask: iIEncoding,
15961616
ARDTIME & obj.AMask: iIEncoding,
@@ -1776,7 +1796,8 @@ func instructionsForProg(p *obj.Prog) []*instruction {
17761796
ins.funct7 = 2
17771797
ins.rs1, ins.rs2 = uint32(p.From.Reg), REG_ZERO
17781798

1779-
case ASCW, ASCD:
1799+
case ASCW, ASCD, AAMOSWAPW, AAMOSWAPD, AAMOADDW, AAMOADDD, AAMOANDW, AAMOANDD, AAMOORW, AAMOORD,
1800+
AAMOXORW, AAMOXORD, AAMOMINW, AAMOMIND, AAMOMINUW, AAMOMINUD, AAMOMAXW, AAMOMAXD, AAMOMAXUW, AAMOMAXUD:
17801801
// Set aq to use acquire access ordering, which matches Go's memory requirements.
17811802
ins.funct7 = 2
17821803
ins.rd, ins.rs1, ins.rs2 = uint32(p.RegTo2), uint32(p.To.Reg), uint32(p.From.Reg)

‎src/runtime/internal/atomic/atomic_riscv64.s

Lines changed: 10 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -30,15 +30,6 @@
3030

3131
#include "textflag.h"
3232

33-
#define AMOWSC(op,rd,rs1,rs2) WORD $0x0600202f+rd<<7+rs1<<15+rs2<<20+op<<27
34-
#define AMODSC(op,rd,rs1,rs2) WORD $0x0600302f+rd<<7+rs1<<15+rs2<<20+op<<27
35-
#define ADD_ 0
36-
#define SWAP_ 1
37-
#define LR_ 2
38-
#define SC_ 3
39-
#define OR_ 8
40-
#define AND_ 12
41-
4233
// Atomically:
4334
// if(*val == *old){
4435
// *val = new;
@@ -108,7 +99,7 @@ TEXT ·Load64(SB),NOSPLIT|NOFRAME,$0-16
10899
TEXT ·Store(SB), NOSPLIT, $0-12
109100
MOV ptr+0(FP), A0
110101
MOVW val+8(FP), A1
111-
AMOWSC(SWAP_,0,10,11)
102+
AMOSWAPW A1, (A0), ZERO
112103
RET
113104

114105
// func Store8(ptr *uint8, val uint8)
@@ -124,7 +115,7 @@ TEXT ·Store8(SB), NOSPLIT, $0-9
124115
TEXT ·Store64(SB), NOSPLIT, $0-16
125116
MOV ptr+0(FP), A0
126117
MOV val+8(FP), A1
127-
AMODSC(SWAP_,0,10,11)
118+
AMOSWAPD A1, (A0), ZERO
128119
RET
129120

130121
TEXT ·Casp1(SB), NOSPLIT, $0-25
@@ -151,7 +142,7 @@ TEXT ·Loadint64(SB),NOSPLIT,$0-16
151142
TEXT ·Xaddint64(SB),NOSPLIT,$0-24
152143
MOV ptr+0(FP), A0
153144
MOV delta+8(FP), A1
154-
WORD $0x04b5352f // amoadd.d.aq a0,a1,(a0)
145+
AMOADDD A1, (A0), A0
155146
ADD A0, A1, A0
156147
MOVW A0, ret+16(FP)
157148
RET
@@ -174,15 +165,15 @@ TEXT ·StoreRel(SB), NOSPLIT, $0-12
174165
TEXT ·Xchg(SB), NOSPLIT, $0-20
175166
MOV ptr+0(FP), A0
176167
MOVW new+8(FP), A1
177-
AMOWSC(SWAP_,11,10,11)
168+
AMOSWAPW A1, (A0), A1
178169
MOVW A1, ret+16(FP)
179170
RET
180171

181172
// func Xchg64(ptr *uint64, new uint64) uint64
182173
TEXT ·Xchg64(SB), NOSPLIT, $0-24
183174
MOV ptr+0(FP), A0
184175
MOV new+8(FP), A1
185-
AMODSC(SWAP_,11,10,11)
176+
AMOSWAPD A1, (A0), A1
186177
MOV A1, ret+16(FP)
187178
RET
188179

@@ -194,7 +185,7 @@ TEXT ·Xchg64(SB), NOSPLIT, $0-24
194185
TEXT ·Xadd(SB), NOSPLIT, $0-20
195186
MOV ptr+0(FP), A0
196187
MOVW delta+8(FP), A1
197-
AMOWSC(ADD_,12,10,11)
188+
AMOADDW A1, (A0), A2
198189
ADD A2,A1,A0
199190
MOVW A0, ret+16(FP)
200191
RET
@@ -203,8 +194,8 @@ TEXT ·Xadd(SB), NOSPLIT, $0-20
203194
TEXT ·Xadd64(SB), NOSPLIT, $0-24
204195
MOV ptr+0(FP), A0
205196
MOV delta+8(FP), A1
206-
AMODSC(ADD_,12,10,11)
207-
ADD A2,A1,A0
197+
AMOADDD A1, (A0), A2
198+
ADD A2, A1, A0
208199
MOV A0, ret+16(FP)
209200
RET
210201

@@ -226,7 +217,7 @@ TEXT ·And8(SB), NOSPLIT, $0-9
226217
XOR $255, A1
227218
SLL A2, A1
228219
XOR $-1, A1
229-
AMOWSC(AND_,0,10,11)
220+
AMOANDW A1, (A0), ZERO
230221
RET
231222

232223
// func Or8(ptr *uint8, val uint8)
@@ -237,5 +228,5 @@ TEXT ·Or8(SB), NOSPLIT, $0-9
237228
AND $-4, A0
238229
SLL $3, A2
239230
SLL A2, A1
240-
AMOWSC(OR_,0,10,11)
231+
AMOORW A1, (A0), ZERO
241232
RET

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