cmd/internal/obj/riscv: support zawrs assembly (#47)

Author: newborn22

src/cmd/asm/internal/asm/testdata/riscv64.s

@@ -244,6 +244,10 @@ start:
 	AMOMINUW	X5, (X6), X7			// af2353c6
 	AMOMINUD	X5, (X6), X7			// af3353c6
 
+	// 15: Wait-on-Reservation-Set Instructions (Zawrs)
+	WRSNTO                              // 7300d000
+    WRSSTO                              // 7300d001
+
 	// 20.5: Single-Precision Load and Store Instructions
 	FLW	(X5), F0				// 07a00200
 	FLW	4(X5), F0				// 07a04200

src/cmd/internal/obj/riscv/anames.go

@@ -456,6 +456,10 @@ const (
 	AAMOMINW
 	AAMOMINUW
 
+	// 15: Wait-on-Reservation-Set Instructions (Zawrs)
+	AWRSNTO
+	AWRSSTO
+
 	// 20.5: Single-Precision Load and Store Instructions
 	AFLW
 	AFSW

src/cmd/internal/obj/riscv/cpu.go

@@ -2032,6 +2032,10 @@ var instructions = [ALAST & obj.AMask]instructionData{
 	AFLD & obj.AMask: {enc: iFEncoding},
 	AFSD & obj.AMask: {enc: sFEncoding},
 
+	// 15: Wait-on-Reservation-Set Instructions (Zawrs)
+	AWRSNTO & obj.AMask: {enc: iIIEncoding},
+	AWRSSTO & obj.AMask: {enc: iIIEncoding},
+
 	// 21.4: Double-Precision Floating-Point Computational Instructions
 	AFADDD & obj.AMask:   {enc: rFFFEncoding},
 	AFSUBD & obj.AMask:   {enc: rFFFEncoding},
@@ -3610,6 +3614,14 @@ func instructionsForProg(p *obj.Prog) []*instruction {
 		ins.funct7 = 3
 		ins.rd, ins.rs1, ins.rs2 = uint32(p.RegTo2), uint32(p.To.Reg), uint32(p.From.Reg)
 
+	case AWRSNTO, AWRSSTO:
+		ins.rd, ins.rs1 = REG_ZERO, REG_ZERO
+		if ins.as == AWRSNTO {
+			ins.imm = 0x0d
+		} else {
+			ins.imm = 0x1d
+		}
+
 	case AECALL, AEBREAK:
 		insEnc := encode(p.As)
 		if p.To.Type == obj.TYPE_NONE {