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phy.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2018-2019 Realtek Corporation
*/
#include <linux/bcd.h>
#include "main.h"
#include "reg.h"
#include "fw.h"
#include "phy.h"
#include "debug.h"
#include "regd.h"
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0)
#include "sar.h"
#endif
struct phy_cfg_pair {
u32 addr;
u32 data;
};
union phy_table_tile {
struct rtw_phy_cond cond;
struct phy_cfg_pair cfg;
};
static const u32 db_invert_table[12][8] = {
{10, 13, 16, 20,
25, 32, 40, 50},
{64, 80, 101, 128,
160, 201, 256, 318},
{401, 505, 635, 800,
1007, 1268, 1596, 2010},
{316, 398, 501, 631,
794, 1000, 1259, 1585},
{1995, 2512, 3162, 3981,
5012, 6310, 7943, 10000},
{12589, 15849, 19953, 25119,
31623, 39811, 50119, 63098},
{79433, 100000, 125893, 158489,
199526, 251189, 316228, 398107},
{501187, 630957, 794328, 1000000,
1258925, 1584893, 1995262, 2511886},
{3162278, 3981072, 5011872, 6309573,
7943282, 1000000, 12589254, 15848932},
{19952623, 25118864, 31622777, 39810717,
50118723, 63095734, 79432823, 100000000},
{125892541, 158489319, 199526232, 251188643,
316227766, 398107171, 501187234, 630957345},
{794328235, 1000000000, 1258925412, 1584893192,
1995262315, 2511886432U, 3162277660U, 3981071706U}
};
u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M };
u8 rtw_ofdm_rates[] = {
DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
DESC_RATE48M, DESC_RATE54M
};
u8 rtw_ht_1s_rates[] = {
DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
DESC_RATEMCS6, DESC_RATEMCS7
};
u8 rtw_ht_2s_rates[] = {
DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10,
DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13,
DESC_RATEMCS14, DESC_RATEMCS15
};
u8 rtw_vht_1s_rates[] = {
DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9
};
u8 rtw_vht_2s_rates[] = {
DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9
};
u8 *rtw_rate_section[RTW_RATE_SECTION_MAX] = {
rtw_cck_rates, rtw_ofdm_rates,
rtw_ht_1s_rates, rtw_ht_2s_rates,
rtw_vht_1s_rates, rtw_vht_2s_rates
};
EXPORT_SYMBOL(rtw_rate_section);
u8 rtw_rate_size[RTW_RATE_SECTION_MAX] = {
ARRAY_SIZE(rtw_cck_rates),
ARRAY_SIZE(rtw_ofdm_rates),
ARRAY_SIZE(rtw_ht_1s_rates),
ARRAY_SIZE(rtw_ht_2s_rates),
ARRAY_SIZE(rtw_vht_1s_rates),
ARRAY_SIZE(rtw_vht_2s_rates)
};
EXPORT_SYMBOL(rtw_rate_size);
static const u8 rtw_cck_size = ARRAY_SIZE(rtw_cck_rates);
static const u8 rtw_ofdm_size = ARRAY_SIZE(rtw_ofdm_rates);
static const u8 rtw_ht_1s_size = ARRAY_SIZE(rtw_ht_1s_rates);
static const u8 rtw_ht_2s_size = ARRAY_SIZE(rtw_ht_2s_rates);
static const u8 rtw_vht_1s_size = ARRAY_SIZE(rtw_vht_1s_rates);
static const u8 rtw_vht_2s_size = ARRAY_SIZE(rtw_vht_2s_rates);
enum rtw_phy_band_type {
PHY_BAND_2G = 0,
PHY_BAND_5G = 1,
};
static void rtw_phy_cck_pd_init(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 i, j;
for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) {
for (j = 0; j < RTW_RF_PATH_MAX; j++)
dm_info->cck_pd_lv[i][j] = CCK_PD_LV0;
}
dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
}
void rtw_phy_set_edcca_th(struct rtw_dev *rtwdev, u8 l2h, u8 h2l)
{
struct rtw_hw_reg_offset *edcca_th = rtwdev->chip->edcca_th;
rtw_write32_mask(rtwdev,
edcca_th[EDCCA_TH_L2H_IDX].hw_reg.addr,
edcca_th[EDCCA_TH_L2H_IDX].hw_reg.mask,
l2h + edcca_th[EDCCA_TH_L2H_IDX].offset);
rtw_write32_mask(rtwdev,
edcca_th[EDCCA_TH_H2L_IDX].hw_reg.addr,
edcca_th[EDCCA_TH_H2L_IDX].hw_reg.mask,
h2l + edcca_th[EDCCA_TH_H2L_IDX].offset);
}
EXPORT_SYMBOL(rtw_phy_set_edcca_th);
void rtw_phy_adaptivity_set_mode(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
/* turn off in debugfs for debug usage */
if (!rtw_edcca_enabled) {
dm_info->edcca_mode = RTW_EDCCA_NORMAL;
rtw_dbg(rtwdev, RTW_DBG_PHY, "EDCCA disabled, cannot be set\n");
return;
}
switch (rtwdev->regd.dfs_region) {
case NL80211_DFS_ETSI:
dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY;
dm_info->l2h_th_ini = chip->l2h_th_ini_ad;
break;
case NL80211_DFS_JP:
dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY;
dm_info->l2h_th_ini = chip->l2h_th_ini_cs;
break;
default:
dm_info->edcca_mode = RTW_EDCCA_NORMAL;
break;
}
}
static void rtw_phy_adaptivity_init(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
rtw_phy_adaptivity_set_mode(rtwdev);
if (chip->ops->adaptivity_init)
chip->ops->adaptivity_init(rtwdev);
}
static void rtw_phy_adaptivity(struct rtw_dev *rtwdev)
{
if (rtwdev->chip->ops->adaptivity)
rtwdev->chip->ops->adaptivity(rtwdev);
}
static void rtw_phy_cfo_init(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
if (chip->ops->cfo_init)
chip->ops->cfo_init(rtwdev);
}
static void rtw_phy_tx_path_div_init(struct rtw_dev *rtwdev)
{
struct rtw_path_div *path_div = &rtwdev->dm_path_div;
path_div->current_tx_path = rtwdev->chip->default_1ss_tx_path;
path_div->path_a_cnt = 0;
path_div->path_a_sum = 0;
path_div->path_b_cnt = 0;
path_div->path_b_sum = 0;
}
void rtw_phy_init(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 addr, mask;
dm_info->fa_history[3] = 0;
dm_info->fa_history[2] = 0;
dm_info->fa_history[1] = 0;
dm_info->fa_history[0] = 0;
dm_info->igi_bitmap = 0;
dm_info->igi_history[3] = 0;
dm_info->igi_history[2] = 0;
dm_info->igi_history[1] = 0;
addr = chip->dig[0].addr;
mask = chip->dig[0].mask;
dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
rtw_phy_cck_pd_init(rtwdev);
dm_info->iqk.done = false;
rtw_phy_adaptivity_init(rtwdev);
rtw_phy_cfo_init(rtwdev);
rtw_phy_tx_path_div_init(rtwdev);
}
EXPORT_SYMBOL(rtw_phy_init);
void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi)
{
struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_hal *hal = &rtwdev->hal;
u32 addr, mask;
u8 path;
if (chip->dig_cck) {
const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0];
rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1);
}
for (path = 0; path < hal->rf_path_num; path++) {
addr = chip->dig[path].addr;
mask = chip->dig[path].mask;
rtw_write32_mask(rtwdev, addr, mask, igi);
}
}
static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
chip->ops->false_alarm_statistics(rtwdev);
}
#define RA_FLOOR_TABLE_SIZE 7
#define RA_FLOOR_UP_GAP 3
static u8 rtw_phy_get_rssi_level(u8 old_level, u8 rssi)
{
u8 table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
u8 new_level = 0;
int i;
for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++)
if (i >= old_level)
table[i] += RA_FLOOR_UP_GAP;
for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
if (rssi < table[i]) {
new_level = i;
break;
}
}
return new_level;
}
struct rtw_phy_stat_iter_data {
struct rtw_dev *rtwdev;
u8 min_rssi;
};
static void rtw_phy_stat_rssi_iter(void *data, struct ieee80211_sta *sta)
{
struct rtw_phy_stat_iter_data *iter_data = data;
struct rtw_dev *rtwdev = iter_data->rtwdev;
struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
u8 rssi;
rssi = ewma_rssi_read(&si->avg_rssi);
si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi);
rtw_fw_send_rssi_info(rtwdev, si);
iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi);
}
static void rtw_phy_stat_rssi(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
struct rtw_phy_stat_iter_data data = {};
data.rtwdev = rtwdev;
data.min_rssi = U8_MAX;
rtw_iterate_stas_atomic(rtwdev, rtw_phy_stat_rssi_iter, &data);
dm_info->pre_min_rssi = dm_info->min_rssi;
dm_info->min_rssi = data.min_rssi;
}
static void rtw_phy_stat_rate_cnt(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
dm_info->last_pkt_count = dm_info->cur_pkt_count;
memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count));
}
static void rtw_phy_statistics(struct rtw_dev *rtwdev)
{
rtw_phy_stat_rssi(rtwdev);
rtw_phy_stat_false_alarm(rtwdev);
rtw_phy_stat_rate_cnt(rtwdev);
}
#define DIG_PERF_FA_TH_LOW 250
#define DIG_PERF_FA_TH_HIGH 500
#define DIG_PERF_FA_TH_EXTRA_HIGH 750
#define DIG_PERF_MAX 0x5a
#define DIG_PERF_MID 0x40
#define DIG_CVRG_FA_TH_LOW 2000
#define DIG_CVRG_FA_TH_HIGH 4000
#define DIG_CVRG_FA_TH_EXTRA_HIGH 5000
#define DIG_CVRG_MAX 0x2a
#define DIG_CVRG_MID 0x26
#define DIG_CVRG_MIN 0x1c
#define DIG_RSSI_GAIN_OFFSET 15
static bool
rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info)
{
u16 fa_lo = DIG_PERF_FA_TH_LOW;
u16 fa_hi = DIG_PERF_FA_TH_HIGH;
u16 *fa_history;
u8 *igi_history;
u8 damping_rssi;
u8 min_rssi;
u8 diff;
u8 igi_bitmap;
bool damping = false;
min_rssi = dm_info->min_rssi;
if (dm_info->damping) {
damping_rssi = dm_info->damping_rssi;
diff = min_rssi > damping_rssi ? min_rssi - damping_rssi :
damping_rssi - min_rssi;
if (diff > 3 || dm_info->damping_cnt++ > 20) {
dm_info->damping = false;
return false;
}
return true;
}
igi_history = dm_info->igi_history;
fa_history = dm_info->fa_history;
igi_bitmap = dm_info->igi_bitmap & 0xf;
switch (igi_bitmap) {
case 5:
/* down -> up -> down -> up */
if (igi_history[0] > igi_history[1] &&
igi_history[2] > igi_history[3] &&
igi_history[0] - igi_history[1] >= 2 &&
igi_history[2] - igi_history[3] >= 2 &&
fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
fa_history[2] > fa_hi && fa_history[3] < fa_lo)
damping = true;
break;
case 9:
/* up -> down -> down -> up */
if (igi_history[0] > igi_history[1] &&
igi_history[3] > igi_history[2] &&
igi_history[0] - igi_history[1] >= 4 &&
igi_history[3] - igi_history[2] >= 2 &&
fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
fa_history[2] < fa_lo && fa_history[3] > fa_hi)
damping = true;
break;
default:
return false;
}
if (damping) {
dm_info->damping = true;
dm_info->damping_cnt = 0;
dm_info->damping_rssi = min_rssi;
}
return damping;
}
static void rtw_phy_dig_get_boundary(struct rtw_dev *rtwdev,
struct rtw_dm_info *dm_info,
u8 *upper, u8 *lower, bool linked)
{
u8 dig_max, dig_min, dig_mid;
u8 min_rssi;
if (linked) {
dig_max = DIG_PERF_MAX;
dig_mid = DIG_PERF_MID;
dig_min = rtwdev->chip->dig_min;
min_rssi = max_t(u8, dm_info->min_rssi, dig_min);
} else {
dig_max = DIG_CVRG_MAX;
dig_mid = DIG_CVRG_MID;
dig_min = DIG_CVRG_MIN;
min_rssi = dig_min;
}
/* DIG MAX should be bounded by minimum RSSI with offset +15 */
dig_max = min_t(u8, dig_max, min_rssi + DIG_RSSI_GAIN_OFFSET);
*lower = clamp_t(u8, min_rssi, dig_min, dig_mid);
*upper = clamp_t(u8, *lower + DIG_RSSI_GAIN_OFFSET, dig_min, dig_max);
}
static void rtw_phy_dig_get_threshold(struct rtw_dm_info *dm_info,
u16 *fa_th, u8 *step, bool linked)
{
u8 min_rssi, pre_min_rssi;
min_rssi = dm_info->min_rssi;
pre_min_rssi = dm_info->pre_min_rssi;
step[0] = 4;
step[1] = 3;
step[2] = 2;
if (linked) {
fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH;
fa_th[1] = DIG_PERF_FA_TH_HIGH;
fa_th[2] = DIG_PERF_FA_TH_LOW;
if (pre_min_rssi > min_rssi) {
step[0] = 6;
step[1] = 4;
step[2] = 2;
}
} else {
fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH;
fa_th[1] = DIG_CVRG_FA_TH_HIGH;
fa_th[2] = DIG_CVRG_FA_TH_LOW;
}
}
static void rtw_phy_dig_recorder(struct rtw_dm_info *dm_info, u8 igi, u16 fa)
{
u8 *igi_history;
u16 *fa_history;
u8 igi_bitmap;
bool up;
igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe;
igi_history = dm_info->igi_history;
fa_history = dm_info->fa_history;
up = igi > igi_history[0];
igi_bitmap |= up;
igi_history[3] = igi_history[2];
igi_history[2] = igi_history[1];
igi_history[1] = igi_history[0];
igi_history[0] = igi;
fa_history[3] = fa_history[2];
fa_history[2] = fa_history[1];
fa_history[1] = fa_history[0];
fa_history[0] = fa;
dm_info->igi_bitmap = igi_bitmap;
}
static void rtw_phy_dig(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 upper_bound, lower_bound;
u8 pre_igi, cur_igi;
u16 fa_th[3], fa_cnt;
u8 level;
u8 step[3];
bool linked;
if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags))
return;
if (rtw_phy_dig_check_damping(dm_info))
return;
linked = !!rtwdev->sta_cnt;
fa_cnt = dm_info->total_fa_cnt;
pre_igi = dm_info->igi_history[0];
rtw_phy_dig_get_threshold(dm_info, fa_th, step, linked);
/* test the false alarm count from the highest threshold level first,
* and increase it by corresponding step size
*
* note that the step size is offset by -2, compensate it afterall
*/
cur_igi = pre_igi;
for (level = 0; level < 3; level++) {
if (fa_cnt > fa_th[level]) {
cur_igi += step[level];
break;
}
}
cur_igi -= 2;
/* calculate the upper/lower bound by the minimum rssi we have among
* the peers connected with us, meanwhile make sure the igi value does
* not beyond the hardware limitation
*/
rtw_phy_dig_get_boundary(rtwdev, dm_info, &upper_bound, &lower_bound,
linked);
cur_igi = clamp_t(u8, cur_igi, lower_bound, upper_bound);
/* record current igi value and false alarm statistics for further
* damping checks, and record the trend of igi values
*/
rtw_phy_dig_recorder(dm_info, cur_igi, fa_cnt);
if (cur_igi != pre_igi)
rtw_phy_dig_write(rtwdev, cur_igi);
}
static void rtw_phy_ra_info_update_iter(void *data, struct ieee80211_sta *sta)
{
struct rtw_dev *rtwdev = data;
struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
rtw_update_sta_info(rtwdev, si, false);
}
static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev)
{
if (rtwdev->watch_dog_cnt & 0x3)
return;
rtw_iterate_stas_atomic(rtwdev, rtw_phy_ra_info_update_iter, rtwdev);
}
static u32 rtw_phy_get_rrsr_mask(struct rtw_dev *rtwdev, u8 rate_idx)
{
u8 rate_order;
rate_order = rate_idx;
if (rate_idx >= DESC_RATEVHT4SS_MCS0)
rate_order -= DESC_RATEVHT4SS_MCS0;
else if (rate_idx >= DESC_RATEVHT3SS_MCS0)
rate_order -= DESC_RATEVHT3SS_MCS0;
else if (rate_idx >= DESC_RATEVHT2SS_MCS0)
rate_order -= DESC_RATEVHT2SS_MCS0;
else if (rate_idx >= DESC_RATEVHT1SS_MCS0)
rate_order -= DESC_RATEVHT1SS_MCS0;
else if (rate_idx >= DESC_RATEMCS24)
rate_order -= DESC_RATEMCS24;
else if (rate_idx >= DESC_RATEMCS16)
rate_order -= DESC_RATEMCS16;
else if (rate_idx >= DESC_RATEMCS8)
rate_order -= DESC_RATEMCS8;
else if (rate_idx >= DESC_RATEMCS0)
rate_order -= DESC_RATEMCS0;
else if (rate_idx >= DESC_RATE6M)
rate_order -= DESC_RATE6M;
else
rate_order -= DESC_RATE1M;
if (rate_idx >= DESC_RATEMCS0 || rate_order == 0)
rate_order++;
return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0);
}
static void rtw_phy_rrsr_mask_min_iter(void *data, struct ieee80211_sta *sta)
{
struct rtw_dev *rtwdev = (struct rtw_dev *)data;
struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 mask = 0;
mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate);
if (mask < dm_info->rrsr_mask_min)
dm_info->rrsr_mask_min = mask;
}
static void rtw_phy_rrsr_update(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
dm_info->rrsr_mask_min = RRSR_RATE_ORDER_MAX;
rtw_iterate_stas_atomic(rtwdev, rtw_phy_rrsr_mask_min_iter, rtwdev);
rtw_write32(rtwdev, REG_RRSR, dm_info->rrsr_val_init & dm_info->rrsr_mask_min);
}
static void rtw_phy_dpk_track(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
if (chip->ops->dpk_track)
chip->ops->dpk_track(rtwdev);
}
struct rtw_rx_addr_match_data {
struct rtw_dev *rtwdev;
struct ieee80211_hdr *hdr;
struct rtw_rx_pkt_stat *pkt_stat;
u8 *bssid;
};
static void rtw_phy_parsing_cfo_iter(void *data, u8 *mac,
struct ieee80211_vif *vif)
{
struct rtw_rx_addr_match_data *iter_data = data;
struct rtw_dev *rtwdev = iter_data->rtwdev;
struct rtw_rx_pkt_stat *pkt_stat = iter_data->pkt_stat;
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
struct rtw_cfo_track *cfo = &dm_info->cfo_track;
u8 *bssid = iter_data->bssid;
u8 i;
if (!ether_addr_equal(vif->bss_conf.bssid, bssid))
return;
for (i = 0; i < rtwdev->hal.rf_path_num; i++) {
cfo->cfo_tail[i] += pkt_stat->cfo_tail[i];
cfo->cfo_cnt[i]++;
}
cfo->packet_count++;
}
void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev,
struct rtw_rx_pkt_stat *pkt_stat)
{
struct ieee80211_hdr *hdr = pkt_stat->hdr;
struct rtw_rx_addr_match_data data = {};
if (pkt_stat->crc_err || pkt_stat->icv_err || !pkt_stat->phy_status ||
ieee80211_is_ctl(hdr->frame_control))
return;
data.rtwdev = rtwdev;
data.hdr = hdr;
data.pkt_stat = pkt_stat;
data.bssid = get_hdr_bssid(hdr);
rtw_iterate_vifs_atomic(rtwdev, rtw_phy_parsing_cfo_iter, &data);
}
EXPORT_SYMBOL(rtw_phy_parsing_cfo);
static void rtw_phy_cfo_track(struct rtw_dev *rtwdev)
{
struct rtw_chip_info *chip = rtwdev->chip;
if (chip->ops->cfo_track)
chip->ops->cfo_track(rtwdev);
}
#define CCK_PD_FA_LV1_MIN 1000
#define CCK_PD_FA_LV0_MAX 500
static u8 rtw_phy_cck_pd_lv_unlink(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 cck_fa_avg = dm_info->cck_fa_avg;
if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
return CCK_PD_LV1;
if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
return CCK_PD_LV0;
return CCK_PD_LV_MAX;
}
#define CCK_PD_IGI_LV4_VAL 0x38
#define CCK_PD_IGI_LV3_VAL 0x2a
#define CCK_PD_IGI_LV2_VAL 0x24
#define CCK_PD_RSSI_LV4_VAL 32
#define CCK_PD_RSSI_LV3_VAL 32
#define CCK_PD_RSSI_LV2_VAL 24
static u8 rtw_phy_cck_pd_lv_link(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 igi = dm_info->igi_history[0];
u8 rssi = dm_info->min_rssi;
u32 cck_fa_avg = dm_info->cck_fa_avg;
if (igi > CCK_PD_IGI_LV4_VAL && rssi > CCK_PD_RSSI_LV4_VAL)
return CCK_PD_LV4;
if (igi > CCK_PD_IGI_LV3_VAL && rssi > CCK_PD_RSSI_LV3_VAL)
return CCK_PD_LV3;
if (igi > CCK_PD_IGI_LV2_VAL || rssi > CCK_PD_RSSI_LV2_VAL)
return CCK_PD_LV2;
if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
return CCK_PD_LV1;
if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
return CCK_PD_LV0;
return CCK_PD_LV_MAX;
}
static u8 rtw_phy_cck_pd_lv(struct rtw_dev *rtwdev)
{
if (!rtw_is_assoc(rtwdev))
return rtw_phy_cck_pd_lv_unlink(rtwdev);
else
return rtw_phy_cck_pd_lv_link(rtwdev);
}
static void rtw_phy_cck_pd(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
struct rtw_chip_info *chip = rtwdev->chip;
u32 cck_fa = dm_info->cck_fa_cnt;
u8 level;
if (rtwdev->hal.current_band_type != RTW_BAND_2G)
return;
if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET)
dm_info->cck_fa_avg = cck_fa;
else
dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2;
rtw_dbg(rtwdev, RTW_DBG_PHY, "IGI=0x%x, rssi_min=%d, cck_fa=%d\n",
dm_info->igi_history[0], dm_info->min_rssi,
dm_info->fa_history[0]);
rtw_dbg(rtwdev, RTW_DBG_PHY, "cck_fa_avg=%d, cck_pd_default=%d\n",
dm_info->cck_fa_avg, dm_info->cck_pd_default);
level = rtw_phy_cck_pd_lv(rtwdev);
if (level >= CCK_PD_LV_MAX)
return;
if (chip->ops->cck_pd_set)
chip->ops->cck_pd_set(rtwdev, level);
}
static void rtw_phy_pwr_track(struct rtw_dev *rtwdev)
{
rtwdev->chip->ops->pwr_track(rtwdev);
}
static void rtw_phy_ra_track(struct rtw_dev *rtwdev)
{
rtw_fw_update_wl_phy_info(rtwdev);
rtw_phy_ra_info_update(rtwdev);
rtw_phy_rrsr_update(rtwdev);
}
void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev)
{
/* for further calculation */
rtw_phy_statistics(rtwdev);
rtw_phy_dig(rtwdev);
rtw_phy_cck_pd(rtwdev);
rtw_phy_ra_track(rtwdev);
rtw_phy_tx_path_diversity(rtwdev);
rtw_phy_cfo_track(rtwdev);
rtw_phy_dpk_track(rtwdev);
rtw_phy_pwr_track(rtwdev);
if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_ADAPTIVITY))
rtw_fw_adaptivity(rtwdev);
else
rtw_phy_adaptivity(rtwdev);
}
#define FRAC_BITS 3
static u8 rtw_phy_power_2_db(s8 power)
{
if (power <= -100 || power >= 20)
return 0;
else if (power >= 0)
return 100;
else
return 100 + power;
}
static u64 rtw_phy_db_2_linear(u8 power_db)
{
u8 i, j;
u64 linear;
if (power_db > 96)
power_db = 96;
else if (power_db < 1)
return 1;
/* 1dB ~ 96dB */
i = (power_db - 1) >> 3;
j = (power_db - 1) - (i << 3);
linear = db_invert_table[i][j];
linear = i > 2 ? linear << FRAC_BITS : linear;
return linear;
}
static u8 rtw_phy_linear_2_db(u64 linear)
{
u8 i;
u8 j;
u32 dB;
if (linear >= db_invert_table[11][7])
return 96; /* maximum 96 dB */
for (i = 0; i < 12; i++) {
if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][7])
break;
else if (i > 2 && linear <= db_invert_table[i][7])
break;
}
for (j = 0; j < 8; j++) {
if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j])
break;
else if (i > 2 && linear <= db_invert_table[i][j])
break;
}
if (j == 0 && i == 0)
goto end;
if (j == 0) {
if (i != 3) {
if (db_invert_table[i][0] - linear >
linear - db_invert_table[i - 1][7]) {
i = i - 1;
j = 7;
}
} else {
if (db_invert_table[3][0] - linear >
linear - db_invert_table[2][7]) {
i = 2;
j = 7;
}
}
} else {
if (db_invert_table[i][j] - linear >
linear - db_invert_table[i][j - 1]) {
j = j - 1;
}
}
end:
dB = (i << 3) + j + 1;
return dB;
}
u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num)
{
s8 power;
u8 power_db;
u64 linear;
u64 sum = 0;
u8 path;
for (path = 0; path < path_num; path++) {
power = rf_power[path];
power_db = rtw_phy_power_2_db(power);
linear = rtw_phy_db_2_linear(power_db);
sum += linear;
}
sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
switch (path_num) {
case 2:
sum >>= 1;
break;
case 3:
sum = ((sum) + ((sum) << 1) + ((sum) << 3)) >> 5;
break;
case 4:
sum >>= 2;
break;
default:
break;
}
return rtw_phy_linear_2_db(sum);
}
EXPORT_SYMBOL(rtw_phy_rf_power_2_rssi);
u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
u32 addr, u32 mask)
{
struct rtw_hal *hal = &rtwdev->hal;
struct rtw_chip_info *chip = rtwdev->chip;
const u32 *base_addr = chip->rf_base_addr;
u32 val, direct_addr;
if (rf_path >= hal->rf_phy_num) {
rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
return INV_RF_DATA;
}
addr &= 0xff;
direct_addr = base_addr[rf_path] + (addr << 2);
mask &= RFREG_MASK;
val = rtw_read32_mask(rtwdev, direct_addr, mask);
return val;
}
EXPORT_SYMBOL(rtw_phy_read_rf);
u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
u32 addr, u32 mask)
{
struct rtw_hal *hal = &rtwdev->hal;
struct rtw_chip_info *chip = rtwdev->chip;
const struct rtw_rf_sipi_addr *rf_sipi_addr;
const struct rtw_rf_sipi_addr *rf_sipi_addr_a;
u32 val32;
u32 en_pi;
u32 r_addr;
u32 shift;
if (rf_path >= hal->rf_phy_num) {
rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
return INV_RF_DATA;
}
if (!chip->rf_sipi_read_addr) {
rtw_err(rtwdev, "rf_sipi_read_addr isn't defined\n");
return INV_RF_DATA;
}
rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path];
rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A];
addr &= 0xff;
val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2);
val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23);
rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32);
/* toggle read edge of path A */
val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2);
rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK);
rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK);
udelay(120);
en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8));
r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read;
val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK);
shift = __ffs(mask);
return (val32 & mask) >> shift;
}
EXPORT_SYMBOL(rtw_phy_read_rf_sipi);
bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
u32 addr, u32 mask, u32 data)
{
struct rtw_hal *hal = &rtwdev->hal;
struct rtw_chip_info *chip = rtwdev->chip;
u32 *sipi_addr = chip->rf_sipi_addr;
u32 data_and_addr;
u32 old_data = 0;
u32 shift;
if (rf_path >= hal->rf_phy_num) {
rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
return false;
}
addr &= 0xff;
mask &= RFREG_MASK;
if (mask != RFREG_MASK) {
old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK);
if (old_data == INV_RF_DATA) {
rtw_err(rtwdev, "Write fail, rf is disabled\n");
return false;
}
shift = __ffs(mask);
data = ((old_data) & (~mask)) | (data << shift);