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Ben Skeggsairlied
Ben Skeggs
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airlied
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drm/nouveau/gv100-: switch to volta semaphore methods
HOPPER_CHANNEL_GPFIFO_A removes the SEMAPHORE[A-D] methods that are currently used by nouveau to implement fences on GF100 and newer. Switch to the newer SEM methods available from VOLTA_CHANNEL_GPFIFO, which are also available on the Hopper/Blackwell host classes. Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Timur Tabi <ttabi@nvidia.com> Tested-by: Timur Tabi <ttabi@nvidia.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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6 files changed

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‎drivers/gpu/drm/nouveau/Kbuild‎

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Original file line numberDiff line numberDiff line change
@@ -69,5 +69,6 @@ nouveau-y += nv17_fence.o
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nouveau-y += nv50_fence.o
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nouveau-y += nv84_fence.o
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nouveau-y += nvc0_fence.o
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nouveau-y += gv100_fence.o
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obj-$(CONFIG_DRM_NOUVEAU) += nouveau.o

‎drivers/gpu/drm/nouveau/gv100_fence.c‎

Lines changed: 93 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,93 @@
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/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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#include "nouveau_fence.h"
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9+
#include "nv50_display.h"
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11+
#include <nvif/push906f.h>
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#include <nvhw/class/clc36f.h>
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static int
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gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
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{
18+
struct nvif_push *push = &chan->chan.push;
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int ret;
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ret = PUSH_WAIT(push, 8);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
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SEM_ADDR_HI, upper_32_bits(virtual),
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SEM_PAYLOAD_LO, sequence);
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PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
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NVDEF(NVC36F, SEM_EXECUTE, OPERATION, RELEASE) |
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NVDEF(NVC36F, SEM_EXECUTE, RELEASE_WFI, EN) |
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NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |
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NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS));
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PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0);
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PUSH_KICK(push);
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return 0;
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}
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static int
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gv100_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
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{
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struct nvif_push *push = &chan->chan.push;
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int ret;
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ret = PUSH_WAIT(push, 6);
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if (ret)
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return ret;
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PUSH_MTHD(push, NVC36F, SEM_ADDR_LO, lower_32_bits(virtual),
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SEM_ADDR_HI, upper_32_bits(virtual),
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SEM_PAYLOAD_LO, sequence);
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PUSH_MTHD(push, NVC36F, SEM_EXECUTE,
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NVDEF(NVC36F, SEM_EXECUTE, OPERATION, ACQ_CIRC_GEQ) |
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NVDEF(NVC36F, SEM_EXECUTE, ACQUIRE_SWITCH_TSG, EN) |
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NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT));
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PUSH_KICK(push);
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return 0;
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}
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static int
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gv100_fence_context_new(struct nouveau_channel *chan)
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{
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struct nv84_fence_chan *fctx;
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int ret;
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ret = nv84_fence_context_new(chan);
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if (ret)
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return ret;
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fctx = chan->fence;
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fctx->base.emit32 = gv100_fence_emit32;
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fctx->base.sync32 = gv100_fence_sync32;
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return 0;
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}
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int
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gv100_fence_create(struct nouveau_drm *drm)
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{
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struct nv84_fence_priv *priv;
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int ret;
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ret = nv84_fence_create(drm);
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if (ret)
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return ret;
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priv = drm->fence;
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priv->base.context_new = gv100_fence_context_new;
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return 0;
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}

‎drivers/gpu/drm/nouveau/include/nvhw/class/clc36f.h‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
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/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _clc36f_h_
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#define _clc36f_h_
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#define NVC36F_NON_STALL_INTERRUPT (0x00000020)
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#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0
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#define NVC36F_SEM_ADDR_LO (0x0000005c)
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#define NVC36F_SEM_ADDR_LO_OFFSET 31:2
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#define NVC36F_SEM_ADDR_HI (0x00000060)
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#define NVC36F_SEM_ADDR_HI_OFFSET 7:0
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#define NVC36F_SEM_PAYLOAD_LO (0x00000064)
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#define NVC36F_SEM_PAYLOAD_LO_PAYLOAD 31:0
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#define NVC36F_SEM_PAYLOAD_HI (0x00000068)
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#define NVC36F_SEM_PAYLOAD_HI_PAYLOAD 31:0
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#define NVC36F_SEM_EXECUTE (0x0000006c)
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#define NVC36F_SEM_EXECUTE_OPERATION 2:0
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#define NVC36F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
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#define NVC36F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
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#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002
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#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003
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#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004
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#define NVC36F_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005
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#define NVC36F_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006
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#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12
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#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000
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#define NVC36F_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001
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#define NVC36F_SEM_EXECUTE_RELEASE_WFI 20:20
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#define NVC36F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
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#define NVC36F_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001
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#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
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#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
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#define NVC36F_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001
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#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25
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#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000
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#define NVC36F_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001
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#define NVC36F_SEM_EXECUTE_REDUCTION 30:27
40+
#define NVC36F_SEM_EXECUTE_REDUCTION_IMIN 0x00000000
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#define NVC36F_SEM_EXECUTE_REDUCTION_IMAX 0x00000001
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#define NVC36F_SEM_EXECUTE_REDUCTION_IXOR 0x00000002
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#define NVC36F_SEM_EXECUTE_REDUCTION_IAND 0x00000003
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#define NVC36F_SEM_EXECUTE_REDUCTION_IOR 0x00000004
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#define NVC36F_SEM_EXECUTE_REDUCTION_IADD 0x00000005
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#define NVC36F_SEM_EXECUTE_REDUCTION_INC 0x00000006
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#define NVC36F_SEM_EXECUTE_REDUCTION_DEC 0x00000007
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#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT 31:31
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#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000
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#define NVC36F_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001
51+
52+
#endif

‎drivers/gpu/drm/nouveau/include/nvif/push906f.h‎

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Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#ifndef PUSH906F_SUBC
88
// Host methods
99
#define PUSH906F_SUBC_NV906F 0
10+
#define PUSH906F_SUBC_NVC36F 0
1011

1112
// Twod
1213
#define PUSH906F_SUBC_NV902D 3

‎drivers/gpu/drm/nouveau/nouveau_drm.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -503,11 +503,13 @@ nouveau_accel_init(struct nouveau_drm *drm)
503503
case KEPLER_CHANNEL_GPFIFO_B:
504504
case MAXWELL_CHANNEL_GPFIFO_A:
505505
case PASCAL_CHANNEL_GPFIFO_A:
506+
ret = nvc0_fence_create(drm);
507+
break;
506508
case VOLTA_CHANNEL_GPFIFO_A:
507509
case TURING_CHANNEL_GPFIFO_A:
508510
case AMPERE_CHANNEL_GPFIFO_A:
509511
case AMPERE_CHANNEL_GPFIFO_B:
510-
ret = nvc0_fence_create(drm);
512+
ret = gv100_fence_create(drm);
511513
break;
512514
default:
513515
break;

‎drivers/gpu/drm/nouveau/nouveau_fence.h‎

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Original file line numberDiff line numberDiff line change
@@ -83,6 +83,7 @@ void nv17_fence_resume(struct nouveau_drm *drm);
8383
int nv50_fence_create(struct nouveau_drm *);
8484
int nv84_fence_create(struct nouveau_drm *);
8585
int nvc0_fence_create(struct nouveau_drm *);
86+
int gv100_fence_create(struct nouveau_drm *);
8687

8788
struct nv84_fence_chan {
8889
struct nouveau_fence_chan base;

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