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Mason Changgregkh
Mason Chang
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gregkh
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thermal/drivers/mediatek/lvts_thermal: Add lvts commands and their sizes to driver data
commit 6203a5e upstream. Add LVTS commands and their sizes to driver data in preparation for adding different commands. Signed-off-by: Mason Chang <mason-cw.chang@mediatek.com> Link: https://lore.kernel.org/r/20250526102659.30225-3-mason-cw.chang@mediatek.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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‎drivers/thermal/mediatek/lvts_thermal.c‎

Lines changed: 52 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -96,17 +96,6 @@
9696

9797
#define LVTS_MINIMUM_THRESHOLD 20000
9898

99-
static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
100-
/*
101-
* Write device mask: 0xC1030000
102-
*/
103-
static const u32 default_init_cmds[] = {
104-
0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
105-
0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
106-
0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
107-
0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
108-
};
109-
11099
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
111100
static int golden_temp_offset;
112101

@@ -136,7 +125,11 @@ struct lvts_ctrl_data {
136125

137126
struct lvts_data {
138127
const struct lvts_ctrl_data *lvts_ctrl;
128+
const u32 *conn_cmd;
129+
const u32 *init_cmd;
139130
int num_lvts_ctrl;
131+
int num_conn_cmd;
132+
int num_init_cmd;
140133
int temp_factor;
141134
int temp_offset;
142135
int gt_calib_bit_offset;
@@ -996,9 +989,10 @@ static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
996989

997990
static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
998991
{
992+
const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
999993
u32 id;
1000994

1001-
lvts_write_config(lvts_ctrl, default_conn_cmds, ARRAY_SIZE(default_conn_cmds));
995+
lvts_write_config(lvts_ctrl, lvts_data->conn_cmd, lvts_data->num_conn_cmd);
1002996

1003997
/*
1004998
* LVTS_ID : Get ID and status of the thermal controller
@@ -1017,7 +1011,9 @@ static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
10171011

10181012
static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
10191013
{
1020-
lvts_write_config(lvts_ctrl, default_init_cmds, ARRAY_SIZE(default_init_cmds));
1014+
const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
1015+
1016+
lvts_write_config(lvts_ctrl, lvts_data->init_cmd, lvts_data->num_init_cmd);
10211017

10221018
return 0;
10231019
}
@@ -1446,6 +1442,17 @@ static int lvts_resume(struct device *dev)
14461442
return 0;
14471443
}
14481444

1445+
static const u32 default_conn_cmds[] = { 0xC103FFFF, 0xC502FF55 };
1446+
/*
1447+
* Write device mask: 0xC1030000
1448+
*/
1449+
static const u32 default_init_cmds[] = {
1450+
0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
1451+
0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
1452+
0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
1453+
0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
1454+
};
1455+
14491456
/*
14501457
* The MT8186 calibration data is stored as packed 3-byte little-endian
14511458
* values using a weird layout that makes sense only when viewed as a 32-bit
@@ -1740,15 +1747,23 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
17401747

17411748
static const struct lvts_data mt7988_lvts_ap_data = {
17421749
.lvts_ctrl = mt7988_lvts_ap_data_ctrl,
1750+
.conn_cmd = default_conn_cmds,
1751+
.init_cmd = default_init_cmds,
17431752
.num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
1753+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1754+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17441755
.temp_factor = LVTS_COEFF_A_MT7988,
17451756
.temp_offset = LVTS_COEFF_B_MT7988,
17461757
.gt_calib_bit_offset = 24,
17471758
};
17481759

17491760
static const struct lvts_data mt8186_lvts_data = {
17501761
.lvts_ctrl = mt8186_lvts_data_ctrl,
1762+
.conn_cmd = default_conn_cmds,
1763+
.init_cmd = default_init_cmds,
17511764
.num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl),
1765+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1766+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17521767
.temp_factor = LVTS_COEFF_A_MT7988,
17531768
.temp_offset = LVTS_COEFF_B_MT7988,
17541769
.gt_calib_bit_offset = 24,
@@ -1757,7 +1772,11 @@ static const struct lvts_data mt8186_lvts_data = {
17571772

17581773
static const struct lvts_data mt8188_lvts_mcu_data = {
17591774
.lvts_ctrl = mt8188_lvts_mcu_data_ctrl,
1775+
.conn_cmd = default_conn_cmds,
1776+
.init_cmd = default_init_cmds,
17601777
.num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl),
1778+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1779+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17611780
.temp_factor = LVTS_COEFF_A_MT8195,
17621781
.temp_offset = LVTS_COEFF_B_MT8195,
17631782
.gt_calib_bit_offset = 20,
@@ -1766,7 +1785,11 @@ static const struct lvts_data mt8188_lvts_mcu_data = {
17661785

17671786
static const struct lvts_data mt8188_lvts_ap_data = {
17681787
.lvts_ctrl = mt8188_lvts_ap_data_ctrl,
1788+
.conn_cmd = default_conn_cmds,
1789+
.init_cmd = default_init_cmds,
17691790
.num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl),
1791+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1792+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17701793
.temp_factor = LVTS_COEFF_A_MT8195,
17711794
.temp_offset = LVTS_COEFF_B_MT8195,
17721795
.gt_calib_bit_offset = 20,
@@ -1775,7 +1798,11 @@ static const struct lvts_data mt8188_lvts_ap_data = {
17751798

17761799
static const struct lvts_data mt8192_lvts_mcu_data = {
17771800
.lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
1801+
.conn_cmd = default_conn_cmds,
1802+
.init_cmd = default_init_cmds,
17781803
.num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
1804+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1805+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17791806
.temp_factor = LVTS_COEFF_A_MT8195,
17801807
.temp_offset = LVTS_COEFF_B_MT8195,
17811808
.gt_calib_bit_offset = 24,
@@ -1784,7 +1811,11 @@ static const struct lvts_data mt8192_lvts_mcu_data = {
17841811

17851812
static const struct lvts_data mt8192_lvts_ap_data = {
17861813
.lvts_ctrl = mt8192_lvts_ap_data_ctrl,
1814+
.conn_cmd = default_conn_cmds,
1815+
.init_cmd = default_init_cmds,
17871816
.num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
1817+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1818+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17881819
.temp_factor = LVTS_COEFF_A_MT8195,
17891820
.temp_offset = LVTS_COEFF_B_MT8195,
17901821
.gt_calib_bit_offset = 24,
@@ -1793,7 +1824,11 @@ static const struct lvts_data mt8192_lvts_ap_data = {
17931824

17941825
static const struct lvts_data mt8195_lvts_mcu_data = {
17951826
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
1827+
.conn_cmd = default_conn_cmds,
1828+
.init_cmd = default_init_cmds,
17961829
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
1830+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1831+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
17971832
.temp_factor = LVTS_COEFF_A_MT8195,
17981833
.temp_offset = LVTS_COEFF_B_MT8195,
17991834
.gt_calib_bit_offset = 24,
@@ -1802,7 +1837,11 @@ static const struct lvts_data mt8195_lvts_mcu_data = {
18021837

18031838
static const struct lvts_data mt8195_lvts_ap_data = {
18041839
.lvts_ctrl = mt8195_lvts_ap_data_ctrl,
1840+
.conn_cmd = default_conn_cmds,
1841+
.init_cmd = default_init_cmds,
18051842
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
1843+
.num_conn_cmd = ARRAY_SIZE(default_conn_cmds),
1844+
.num_init_cmd = ARRAY_SIZE(default_init_cmds),
18061845
.temp_factor = LVTS_COEFF_A_MT8195,
18071846
.temp_offset = LVTS_COEFF_B_MT8195,
18081847
.gt_calib_bit_offset = 24,

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