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[RISC-V] Data layout mismatch between module #7174

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dkurt opened this issue Nov 22, 2022 · 0 comments · Fixed by #7175
Closed

[RISC-V] Data layout mismatch between module #7174

dkurt opened this issue Nov 22, 2022 · 0 comments · Fixed by #7175

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@dkurt
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dkurt commented Nov 22, 2022

Works fine with LLVM 15.0.2 but fails on LLVM llvm/llvm-project@c67b710

Module: e-m:e-p:64:64-i64:64-i128:128-n64-S128
Engine: e-m:e-p:64:64-i64:64-i128:128-n32:64-S128

Internal Error at /home/dkurt/Halide/src/JITModule.cpp:286 triggered by user code at : Warning: data layout mismatch between module (e-m:e-p:64:64-i64:64-i128:128-n64-S128) and what the execution engine expects (e-m:e-p:64:64-i64:64-i128:128-n32:64-S128)
Reproducer
#include "Halide.h"

using namespace Halide;

static int sz = 64;
static int numPrints = 17;

int main(int argc, char** argv) {
    Func brighter("brighter");
    Var x("x"), y("y");

    Buffer<uint8_t> input(sz, sz);
    for (int j = 0; j < numPrints; j++) {
        for (int i = 0; i < numPrints; i++) {
            input(i, j) = i + j;
            std::cout << (int)input(i, j) << " ";
        }
        std::cout << std::endl;
    }
    std::cout << std::endl;

    brighter(x, y) = input(x, y) * 2;

    brighter.bound(x, 0, sz).bound(y, 0, sz);

    Target target = get_host_target();
    std::cout << target << std::endl;

    brighter.print_loop_nest();

    Buffer<uint8_t> output(sz, sz);
    try {
        brighter.realize(output, target);
    } catch(Halide::InternalError& ex) {
        std::cout << ex.what() << std::endl;
    }

    for (int j = 0; j < numPrints; j++) {
        for (int i = 0; i < numPrints; i++) {
            std::cout << (int)output(i, j) << " ";
        }
        std::cout << std::endl;
    }
    std::cout << std::endl;
}
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