-*- mode:org -*-

Cycle stealing

Fix double cache write on I-cache miss & D-cache miss overlap

misc

Rename doneM

Changes

dma.v

Added port doneM, renamed READ -> WRITE
Cycle stealing: disable BR for just 1 cycle

hazard_unit.v

Added port dma_begin, dma_end

cache.v

Add !bus_granted for readM and writeM