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[AArch64][Win] Emit SEH instructions for the swift async
context-related instructions in the prologue and the epilogue. This fixes an error from checkARM64Instructions() in MCWin64EH.cpp. Cherrypick from commit llvm/llvm-project@0ecd884 Cherrypick PR swiftlang#7533
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2 files changed

+54
-1
lines changed

2 files changed

+54
-1
lines changed

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 30 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1477,10 +1477,20 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
14771477
BuildMI(MBB, MBBI, DL, TII->get(AArch64::LOADgot), AArch64::X16)
14781478
.addExternalSymbol("swift_async_extendedFramePointerFlags",
14791479
AArch64II::MO_GOT);
1480+
if (NeedsWinCFI) {
1481+
BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1482+
.setMIFlags(MachineInstr::FrameSetup);
1483+
HasWinCFI = true;
1484+
}
14801485
BuildMI(MBB, MBBI, DL, TII->get(AArch64::ORRXrs), AArch64::FP)
14811486
.addUse(AArch64::FP)
14821487
.addUse(AArch64::X16)
14831488
.addImm(Subtarget.isTargetILP32() ? 32 : 0);
1489+
if (NeedsWinCFI) {
1490+
BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1491+
.setMIFlags(MachineInstr::FrameSetup);
1492+
HasWinCFI = true;
1493+
}
14841494
break;
14851495
}
14861496
[[fallthrough]];
@@ -1491,6 +1501,11 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
14911501
.addUse(AArch64::FP)
14921502
.addImm(0x1100)
14931503
.setMIFlag(MachineInstr::FrameSetup);
1504+
if (NeedsWinCFI) {
1505+
BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1506+
.setMIFlags(MachineInstr::FrameSetup);
1507+
HasWinCFI = true;
1508+
}
14941509
break;
14951510

14961511
case SwiftAsyncFramePointerMode::Never:
@@ -1621,11 +1636,20 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
16211636
bool HaveInitialContext = Attrs.hasAttrSomewhere(Attribute::SwiftAsync);
16221637
if (HaveInitialContext)
16231638
MBB.addLiveIn(AArch64::X22);
1639+
Register Reg = HaveInitialContext ? AArch64::X22 : AArch64::XZR;
16241640
BuildMI(MBB, MBBI, DL, TII->get(AArch64::StoreSwiftAsyncContext))
1625-
.addUse(HaveInitialContext ? AArch64::X22 : AArch64::XZR)
1641+
.addUse(Reg)
16261642
.addUse(AArch64::SP)
16271643
.addImm(FPOffset - 8)
16281644
.setMIFlags(MachineInstr::FrameSetup);
1645+
if (NeedsWinCFI) {
1646+
// WinCFI and arm64e, where StoreSwiftAsyncContext is expanded
1647+
// to multiple instructions, should be mutually-exclusive.
1648+
assert(Subtarget.getTargetTriple().getArchName() != "arm64e");
1649+
BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1650+
.setMIFlags(MachineInstr::FrameSetup);
1651+
HasWinCFI = true;
1652+
}
16291653
}
16301654

16311655
// Issue sub fp, sp, FPOffset or
@@ -2123,6 +2147,11 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
21232147
.addUse(AArch64::FP)
21242148
.addImm(0x10fe)
21252149
.setMIFlag(MachineInstr::FrameDestroy);
2150+
if (NeedsWinCFI) {
2151+
BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
2152+
.setMIFlags(MachineInstr::FrameDestroy);
2153+
HasWinCFI = true;
2154+
}
21262155
break;
21272156

21282157
case SwiftAsyncFramePointerMode::Never:
Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
; RUN: rm -rf %t && mkdir -p %t
2+
; RUN: llc -mtriple aarch64-unknown-windows-msvc %s -o - | FileCheck %s
3+
; RUN: llc -mtriple aarch64-unknown-windows-msvc -filetype obj %s -o %t/a.o
4+
5+
; Check that the prologue/epilogue instructions for the swift async
6+
; context have an associated SEH instruction and that it doesn't error
7+
; when the output is an object file.
8+
9+
; CHECK: orr x29, x29, #0x1000000000000000
10+
; CHECK-NEXT: .seh_nop
11+
; CHECK: str x22, [sp, #16]
12+
; CHECK-NEXT: .seh_nop
13+
; CHECK: and x29, x29, #0xefffffffffffffff
14+
; CHECK-NEXT: .seh_nop
15+
16+
declare ptr @llvm.swift.async.context.addr()
17+
18+
define internal swifttailcc void @test(ptr nocapture readonly swiftasync %0) {
19+
entryresume.0:
20+
%1 = load ptr, ptr %0, align 8
21+
%2 = tail call ptr @llvm.swift.async.context.addr()
22+
store ptr %1, ptr %2, align 8
23+
ret void
24+
}

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