riscv: Add bitmanip instructions to emitter

[unknownbrackets]

Like vector, this has also been ratified. Fairly simple, adds a few things that would be useful.

-[Unknown]

[hrydgard]

Makes me curious, does RISC-V have some kind of CPUID type instruction that works in user mode, so we can check for the extensions without reading from /proc or something, or not? Always felt it's silly that ARM doesn't have that..

[hrydgard]

Whoops, accidentally squash-merged because github saved tha state, sigh. Oh well.

[unknownbrackets]

Makes me curious, does RISC-V have some kind of CPUID type instruction that works in user mode, so we can check for the extensions without reading from /proc or something, or not? Always felt it's silly that ARM doesn't have that..

So kinda yes, but I'm confused about how you're supposed to do this.

The extensions that are a single letter (this one's B, the last one's V) set a bit in a CSR that can be read by the letter index (A=0.) However, this bit can indicate if the extension is enabled/supported at machine/hypervisor/etc. level only and is more of a privileged thing. We use getauxval(AT_HWCAP) to get the current state for user-mode. I don't know if there's a better way.

Zmmul, Zicsr, half-floats, and some other things have "Z" extensions. These don't get a bit, so I don't really understand how to detect them. It seems like they're only in /proc or /sys or something, and not sure on BSD. Because of this, I'm not sure how to tell if Zicsr is enabled but it's the only way I know of to set frm (float rounding mode) or read vl (otherwise VLEFF_V is kinda useless.) It's probably gonna be enabled everywhere...

One can use getauxval on ARM as well:
https://community.arm.com/arm-community-blogs/b/operating-systems-blog/posts/runtime-detection-of-cpu-features-on-an-armv8-a-cpu
https://www.kernel.org/doc/html/v5.3/arm64/elf_hwcaps.html

This should be the most platform independent way to do it (FreeBSD on ARM64, etc. too.) Though beware:
microsoft/WSL#3682

-[Unknown]