LiteX submodule version points to unreachable URL

[d0ntrash]

The submodule "litex @ fbadfa1" uses an outdated URL in .gitmodules:

[submodule "litex/soc/software/compiler_rt"]
	path = litex/soc/software/compiler_rt
	url = https://git.llvm.org/git/compiler-rt

The URL is not reachable anymore. It seems like llvm moved to https://github.com/llvm/llvm-project.
This leads to an error while installing submodules using the lxbuildenv.py scirpt.

Using the LiteX master branch instead seams to break some more things.

Warning: multiple conflicting drivers for icebreaker.\sys_rst:
    port O[0] of cell sys_rst_SB_LUT4_O (SB_LUT4)
    port Q[0] of cell SB_DFFS_1 (SB_DFFS)
ERROR: Net 'sys_rst' is multiply driven by cell ports SB_DFFS_1.Q and sys_rst_SB_LUT4_O.O
0 warnings, 1 error
Traceback (most recent call last):
  File "/home/___/Projects/Icebreaker/icebreaker-litex-examples/soc/icebreaker.py", line 243, in <module>
    main()
  File "/home/___/Projects/Icebreaker/icebreaker-litex-examples/soc/icebreaker.py", line 234, in main
    builder.build()
  File "/home/___/Projects/Icebreaker/icebreaker-litex-examples/soc/deps/litex/litex/soc/integration/builder.py", line 217, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/home/___/Projects/Icebreaker/icebreaker-litex-examples/soc/deps/litex/litex/soc/integration/soc.py", line 1075, in build
    return self.platform.build(self, *args, **kwargs)
  File "/home/___/Projects/Icebreaker/icebreaker-litex-examples/soc/deps/litex/litex/build/lattice/platform.py", line 41, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/___/Projects/Icebreaker/icebreaker-litex-examples/soc/deps/litex/litex/build/lattice/icestorm.py", line 211, in build
    _run_script(script)
  File "/home/___/Projects/Icebreaker/icebreaker-litex-examples/soc/deps/litex/litex/build/lattice/icestorm.py", line 142, in _run_script
    raise OSError("Error occured during Yosys/Nextpnr's script execution.")
OSError: Error occured during Yosys/Nextpnr's script execution.

Does anyone have an ideas on how to fix this easily?

[ziaddb]

I have been trying to but unable to.

https://github.com/llvm-mirror/compiler-rt

seems to be a location we can try to point it to, but could not find where to change it in the code.

Does anyone have an idea ?

[dylanmc]

Also don't know where to change it, but after an initial (unsuccessful) run of icebreaker.py, changing the compiler_rt section of .git/modules/soc/deps/litex/config to:

[submodule "litex/soc/software/compiler_rt"]
    active = true
    url = https://github.com/litex-hub/pythondata-software-compiler_rt

seems to have enabled icebreaker.py to run and build to completion.

[jaycosper]

I also had to change the VexRiscv-verilog repo link as well:

[submodule "litex/soc/software/compiler_rt"]
active = true
url = https://github.com/litex-hub/pythondata-software-compiler_rt

[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
path = litex/soc/cores/cpu/vexriscv/verilog
url = https://github.com/litex-hub/pythondata-cpu-vexriscv.git

And then do a git submodule update .

For whatever reason, I also failed timing at the default 21MHz. I lowered it to 12MHz (to match the Icebreaker default) and passed. The clock can be changed in the icebreaker.py script or as an argument.

[sedurCode]

https://github.com/litex-hub/pythondata-cpu-vexriscv.git

Did you ever manage to figure out how to clock it higher @jaycosper ?

[jaycosper]

@sedurCode I did not clock it at the full 21MHz, but got to 20MHz. It was barely failing timing, but I did not spend the effort to fully debug.
from icebreaker.py:

• parser.add_argument("--sys-clk-freq", type=float, default=20e6, help="Select system clock frequency")