@@ -9093,6 +9093,13 @@ void ForbiddenRegs::generateReservedGRFForbidden(
90939093 for (unsigned int i = 0 ; i < reservedGRFNum; i++) {
90949094 forbiddenVec[index].set (largestNoneReservedReg - i, true );
90959095 }
9096+
9097+ auto &fg = builder.kernel .fg ;
9098+ if (fg.reserveSR ) {
9099+ forbiddenVec[index].set (
9100+ fg.scratchRegDcl ->getRegVar ()->getPhyReg ()->asGreg ()->getRegNum (),
9101+ true );
9102+ }
90969103}
90979104
90989105// ETO use only last 16 registers
@@ -10965,6 +10972,27 @@ void GlobalRA::createVariablesForHybridRAWithSpill() {
1096510972 0 );
1096610973}
1096710974
10975+ void GlobalRA::initSRAsScratch () const {
10976+ // Verify old scratch dcl assignment before changing it
10977+ vISA_ASSERT (kernel.fg .scratchRegDcl ->getRegVar ()
10978+ ->getPhyReg ()
10979+ ->asGreg ()
10980+ ->getRegNum () == kernel.stackCall .getSpillHeaderGRF (),
10981+ " unexpected assignment" );
10982+ vISA_ASSERT (kernel.stackCall .getSpillHeaderGRF () ==
10983+ kernel.stackCall .getFPSPGRF (),
10984+ " expecting same GRF" );
10985+ // Use last caller save GRF for spill/fill addr computation. Since this
10986+ // address is used as LSC header, we must use 0th sub-reg of reserved
10987+ // GRF.
10988+ kernel.fg .scratchRegDcl ->getRegVar ()->setPhyReg (
10989+ regPool.getGreg (kernel.stackCall .getCallerSaveLastGRF ()), 0 );
10990+
10991+ // Mark SR assignment as reserved so other variables don't try to
10992+ // use it.
10993+ kernel.fg .reserveSR = true ;
10994+ }
10995+
1096810996void GlobalRA::stackCallSaveRestore (bool hasStackCall) {
1096910997 //
1097010998 // If the graph has stack calls, then add the caller-save/callee-save pseudo
@@ -10988,6 +11016,7 @@ void GlobalRA::stackCallSaveRestore(bool hasStackCall) {
1098811016 builder.getBuiltinR0 ()->getRegVar ()->setPhyReg (
1098911017 builder.phyregpool .getGreg (kernel.stackCall .getThreadHeaderGRF ()), 0 );
1099011018 }
11019+
1099111020 }
1099211021}
1099311022
0 commit comments