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igorban-inteligcbot
igorban-intel
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igcbot
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Minor fixes and refactors.
1 parent 5a62655 commit 7bcf614

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12 files changed

+41
-38
lines changed

12 files changed

+41
-38
lines changed

‎IGC/VectorCompiler/CMCL/lib/Support/BuiltinTranslator.cpp‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -240,11 +240,8 @@ Type &getTypeFromBuiltinOperand(CallInst &BiCall, int OpIdx) {
240240
auto *OpInst = BiCall.getArgOperand(OpIdx);
241241
while (auto *Inst = dyn_cast<CastInst>(OpInst))
242242
OpInst = Inst->getOperand(0);
243-
auto *Alloc = dyn_cast<AllocaInst>(OpInst);
244-
assert(Alloc);
245-
auto *RetVTy =
246-
dyn_cast<IGCLLVM::FixedVectorType>(Alloc->getAllocatedType());
247-
assert(RetVTy);
243+
auto *Alloc = cast<AllocaInst>(OpInst);
244+
auto *RetVTy = cast<IGCLLVM::FixedVectorType>(Alloc->getAllocatedType());
248245
IRBuilder<> IRB(Alloc);
249246
RetVTy = IGCLLVM::FixedVectorType::get(IRB.getInt1Ty(),
250247
RetVTy->getNumElements());
@@ -575,7 +572,7 @@ static inline Value &createInvmRsqrtm(const std::vector<Value *> &Operands,
575572
auto *Mask = IRB.CreateExtractValue(CI, 1, Suffix + ".mask");
576573

577574
// Cast from i1-mask to i8 to store result
578-
auto *ResTy = dyn_cast<IGCLLVM::FixedVectorType>(Res->getType());
575+
auto *ResTy = cast<IGCLLVM::FixedVectorType>(Res->getType());
579576
auto *RetI8Ty =
580577
IGCLLVM::FixedVectorType::get(IRB.getInt8Ty(), ResTy->getNumElements());
581578
auto *ExtMask = IRB.CreateZExt(Mask, RetI8Ty);

‎IGC/VectorCompiler/include/GenXUtil.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ template <typename T> inline int log2(T Val) {
5959
if (Val <= 0)
6060
return -1;
6161
unsigned CLZ = llvm::countLeadingZeros<uint32_t>(Val);
62+
IGC_ASSERT_EXIT(CLZ < 32);
6263
return 31 - CLZ;
6364
}
6465

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXBaling.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -780,7 +780,7 @@ void GenXBaling::processStore(StoreInst *Inst) {
780780
<< __FUNCTION__ << " setting operand #" << OperandNum
781781
<< " to bale in instruction " << *Inst << "\n");
782782
setOperandBaled(Inst, OperandNum, &BI);
783-
} else if (isa<CallInst>(V) && cast<CallInst>(V)->isInlineAsm()) {
783+
} else if (V && isa<CallInst>(V) && cast<CallInst>(V)->isInlineAsm()) {
784784
LLVM_DEBUG(llvm::dbgs()
785785
<< __FUNCTION__ << " setting operand #" << OperandNum
786786
<< " to bale in instruction " << *Inst << "\n");
@@ -1778,7 +1778,7 @@ void GenXBaling::processTwoAddrSend(CallInst *CI) {
17781778
if (Liveness)
17791779
Liveness->eraseLiveRange(Wr);
17801780
Wr->eraseFromParent();
1781-
IGC_ASSERT(Rd);
1781+
IGC_ASSERT_EXIT(Rd);
17821782
if (Rd->use_empty()) {
17831783
if (Liveness)
17841784
Liveness->eraseLiveRange(Rd);

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2957,7 +2957,7 @@ Value *GenXKernelBuilder::getPredicateOperand(Instruction *Inst,
29572957
Value *Mask = Inst->getOperand(OperandNum);
29582958
// Check for baled in all/any/notp/rdpredregion.
29592959
while (BI.isOperandBaled(OperandNum)) {
2960-
Instruction *Inst = dyn_cast<Instruction>(Mask);
2960+
Instruction *Inst = cast<Instruction>(Mask);
29612961
if (isNot(Inst)) {
29622962
if (Control != PRED_CTRL_NON) {
29632963
// switch any<->all as well as invert bit

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXDetectPointerArg.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -271,7 +271,7 @@ std::pair<AllocaInst *, GetElementPtrInst *>
271271
GenXDetectPointerArg::findAllocaWithOffset(Value *Ptr) {
272272
// Only support pointer to alloca
273273
if (auto *PTy = dyn_cast<PointerType>(Ptr->getType());
274-
PTy->getAddressSpace() != vc::AddrSpace::Private)
274+
PTy && PTy->getAddressSpace() != vc::AddrSpace::Private)
275275
return {};
276276

277277
AllocaInst *AI = nullptr;

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXLegacyToLscTranslator.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -294,7 +294,7 @@ Value *GenXLegacyToLscTranslator::translateOWordLoadStore(CallInst &CI) const {
294294
IGC_ASSERT_EXIT(Data);
295295
OrigVTy = dyn_cast<IGCLLVM::FixedVectorType>(Data->getType());
296296
}
297-
IGC_ASSERT(OrigVTy);
297+
IGC_ASSERT_EXIT(OrigVTy);
298298

299299
auto SizeBits = OrigVTy->getScalarSizeInBits() * OrigVTy->getNumElements();
300300
auto NumDWords = SizeBits / DWordBits;

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXLegalization.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1216,6 +1216,7 @@ unsigned GenXLegalization::determineWidth(unsigned WholeWidth,
12161216
// * this legalization pass does not have access to FGs
12171217
ExecSizeAllowedBits &= 0x1f;
12181218

1219+
IGC_ASSERT_EXIT(ExecSizeAllowedBits > 0);
12191220
unsigned MainInstMinWidth = 1
12201221
<< llvm::countTrailingZeros(ExecSizeAllowedBits);
12211222
// Determine the vector width that we need to split into.

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXSimdCFConformance.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3044,7 +3044,7 @@ bool GenXSimdCFConformance::getConnectedVals(
30443044
if (LowerBadUsers) {
30453045
SetVector<Value *> ToRemove;
30463046
for (auto &BadUser : UsersToLower) {
3047-
replaceUseWithLoweredEM(dyn_cast<Instruction>(BadUser.getValue()),
3047+
replaceUseWithLoweredEM(cast<Instruction>(BadUser.getValue()),
30483048
BadUser.getIndex(), ToRemove);
30493049
}
30503050
for (auto Inst : ToRemove) {
@@ -3233,7 +3233,7 @@ void GenXSimdCFConformance::resolveBitCastChains() {
32333233
continue;
32343234

32353235
std::set<Value *> Visited;
3236-
Instruction *I = dyn_cast<Instruction>(Val.getValue());
3236+
Instruction *I = cast<Instruction>(Val.getValue());
32373237
Value *EMProd = getEMProducer(I, Visited, true);
32383238

32393239
if (!EMProd) {

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXStructSplitter.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -883,6 +883,7 @@ void DependencyGraph::remakeParent(Node &SNode, Node &SNodeToChange,
883883
Index + ExpandIndicies++);
884884
}
885885
// The Index will be inc, so there is no need of extra offset.
886+
IGC_ASSERT_EXIT(ExpandIndicies > 0);
886887
--ExpandIndicies;
887888
} else {
888889
// If element of structure is not changed, then just copies info about it

‎IGC/VectorCompiler/lib/GenXCodeGen/GenXUtil.cpp‎

Lines changed: 23 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2205,6 +2205,7 @@ unsigned genx::getLogAlignment(VISA_Align Align, unsigned GRFWidth) {
22052205
case ALIGN_GRF:
22062206
return Log2_32(GRFWidth);
22072207
case ALIGN_2_GRF:
2208+
IGC_ASSERT_EXIT(GRFWidth > 0);
22082209
return Log2_32(GRFWidth) + 1;
22092210
default:
22102211
report_fatal_error("Unknown alignment");
@@ -2214,39 +2215,41 @@ unsigned genx::getLogAlignment(VISA_Align Align, unsigned GRFWidth) {
22142215
VISA_Align genx::getVISA_Align(unsigned LogAlignment, unsigned GRFWidth) {
22152216
if (LogAlignment == Log2_32(ByteBytes))
22162217
return ALIGN_BYTE;
2217-
else if (LogAlignment == Log2_32(WordBytes))
2218+
if (LogAlignment == Log2_32(WordBytes))
22182219
return ALIGN_WORD;
2219-
else if (LogAlignment == Log2_32(DWordBytes))
2220+
if (LogAlignment == Log2_32(DWordBytes))
22202221
return ALIGN_DWORD;
2221-
else if (LogAlignment == Log2_32(QWordBytes))
2222+
if (LogAlignment == Log2_32(QWordBytes))
22222223
return ALIGN_QWORD;
2223-
else if (LogAlignment == Log2_32(OWordBytes))
2224+
if (LogAlignment == Log2_32(OWordBytes))
22242225
return ALIGN_OWORD;
2225-
else if (LogAlignment == Log2_32(GRFWidth))
2226-
return ALIGN_GRF;
2227-
else if (LogAlignment == Log2_32(GRFWidth) + 1)
2228-
return ALIGN_2_GRF;
2229-
else
2230-
report_fatal_error("Unknown log alignment");
2226+
if (GRFWidth > 0) {
2227+
if (LogAlignment == Log2_32(GRFWidth))
2228+
return ALIGN_GRF;
2229+
if (LogAlignment == Log2_32(GRFWidth) + 1)
2230+
return ALIGN_2_GRF;
2231+
}
2232+
report_fatal_error("Unknown log alignment");
22312233
}
22322234

22332235
unsigned genx::ceilLogAlignment(unsigned LogAlignment, unsigned GRFWidth) {
22342236
if (LogAlignment <= Log2_32(ByteBytes))
22352237
return Log2_32(ByteBytes);
2236-
else if (LogAlignment <= Log2_32(WordBytes))
2238+
if (LogAlignment <= Log2_32(WordBytes))
22372239
return Log2_32(WordBytes);
2238-
else if (LogAlignment <= Log2_32(DWordBytes))
2240+
if (LogAlignment <= Log2_32(DWordBytes))
22392241
return Log2_32(DWordBytes);
2240-
else if (LogAlignment <= Log2_32(QWordBytes))
2242+
if (LogAlignment <= Log2_32(QWordBytes))
22412243
return Log2_32(QWordBytes);
2242-
else if (LogAlignment <= Log2_32(OWordBytes))
2244+
if (LogAlignment <= Log2_32(OWordBytes))
22432245
return Log2_32(OWordBytes);
2244-
else if (LogAlignment <= Log2_32(GRFWidth))
2245-
return Log2_32(GRFWidth);
2246-
else if (LogAlignment <= Log2_32(GRFWidth) + 1)
2247-
return Log2_32(GRFWidth) + 1;
2248-
else
2249-
report_fatal_error("Unknown log alignment");
2246+
if (GRFWidth > 0) {
2247+
if (LogAlignment <= Log2_32(GRFWidth))
2248+
return Log2_32(GRFWidth);
2249+
if (LogAlignment <= Log2_32(GRFWidth) + 1)
2250+
return Log2_32(GRFWidth) + 1;
2251+
}
2252+
report_fatal_error("Unknown log alignment");
22502253
}
22512254

22522255
bool genx::isWrPredRegionLegalSetP(const CallInst &WrPredRegion) {

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