[SYCL][NATIVECPU][LIBCLC] Use libclc for SYCL Native CPU (#10970)

This PR allows linking to libclc when compiling for SYCL Native CPU.
Currently only the `x86_64-unknown-linux-gnu` target triple is
supported, additional target triples (and possibly a more versatile way
of setting them) will come with follow up PRs.
Some useful information for reviewing:
* We start using an `AddrSpaceMap` (set in `TargetInfo.cpp`) because the
mangled names emitted by the device compiler need to match with the
names provided by `libclc`. The AddressSpaceMap is taken from the `PTX`
Target.
* Changes in `Driver` are needed to find and link to `libclc`.
* `libclc/ptx-nvidiacl/libspirv/atomic/loadstore_helpers.ll` has been
split into 4 modules, one for each memory ordering constraint. Copies of
these modules have been added in `generic` (because some functions in
`generic/libspirv/atomic` needed them), and the module split allows to
specialize the file for targets that may not support some orderings.
Currently only a couple of function for `acquire` and `seq_cst` have
been implemented for `generic`, but the others will be implemented in a
follow up PR.
* We've added a target in `libclc` for `x86_64-unknown-linux`. This has
been done because some math builtins in `generic` have been defined as
```
typedef char vec __attribute__((ext_vector_type(8)));
__attribute__((overloadable)) vec __clc_native_popcount(vec x) __asm("llvm.ctpop" ".v16i" "8");

vec call(vec x) {
  return __clc_native_popcount(x);
}
```
While this approach conveniently allows to call directly LLVM
intrinsics, it does seem to play well with the ABI for
`x86_64-unknown-linux`, since it leads to this IR:
```
define dso_local double @call(double noundef %x.coerce) #0 {
entry:
  %0 = bitcast double %x.coerce to <8 x i8>
  %1 = bitcast <8 x i8> %0 to double
  %call = call double @llvm.ctpop.v8i8(double noundef %1) #8
  %2 = bitcast double %call to <8 x i8>
  %3 = bitcast <8 x i8> %2 to double
  ret double %3
}
```
Which is invalid because `lvm.ctpop.v8i8` expect a vector of `i8` and
not a `double`, leading to failing asserts in the compiler that
prevented from building `libclc`.

As a temporary work around we have added empty files that override the
files in `generic` when building for `x86_64-unknown-linux`, allowing to
complete the build, even though the corresponding builtins will be
missing from the library. We are working on a proper solution for this.

---------

Co-authored-by: Uwe Dolinsky <uwe@codeplay.com>

Author: PietroGhg

buildbot/configure.py

@@ -65,7 +65,7 @@ def do_configure(args):
     if args.enable_esimd_emulator:
         sycl_enabled_plugins.append("esimd_emulator")
 
-    if args.cuda or args.hip:
+    if args.cuda or args.hip or args.native_cpu:
         llvm_enable_projects += ';libclc'
 
     if args.cuda:
@@ -87,6 +87,12 @@ def do_configure(args):
         sycl_build_pi_hip_platform = args.hip_platform
         sycl_enabled_plugins.append("hip")
 
+    if args.native_cpu:
+        #Todo: we should set whatever targets we support for native cpu
+        libclc_targets_to_build += ';x86_64-unknown-linux-gnu'
+        sycl_enabled_plugins.append("native_cpu")
+
+
     # all llvm compiler targets don't require 3rd party dependencies, so can be
     # built/tested even if specific runtimes are not available
     if args.enable_all_llvm_targets:
@@ -234,6 +240,7 @@ def main():
     parser.add_argument("-t", "--build-type",
                         metavar="BUILD_TYPE", default="Release", help="build type: Debug, Release")
     parser.add_argument("--cuda", action='store_true', help="switch from OpenCL to CUDA")
+    parser.add_argument("--native_cpu", action='store_true', help="Enable SYCL Native CPU")
     parser.add_argument("--hip", action='store_true', help="switch from OpenCL to HIP")
     parser.add_argument("--hip-platform", type=str, choices=['AMD', 'NVIDIA'], default='AMD', help="choose hardware platform for HIP backend")
     parser.add_argument("--host-target", default='X86',

clang/lib/Basic/TargetInfo.cpp

@@ -516,6 +516,38 @@ void TargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) {
 
   if (Opts.FakeAddressSpaceMap)
     AddrSpaceMap = &FakeAddrSpaceMap;
+
+  if (Opts.SYCLIsDevice && Opts.SYCLIsNativeCPU) {
+    // For SYCL Native CPU we use the NVPTXAddrSpaceMap because
+    // we need builtins to be mangled with AS information
+
+    static const unsigned SYCLNativeCPUASMap[] = {
+        0,  // Default
+        1,  // opencl_global
+        3,  // opencl_local
+        4,  // opencl_constant
+        0,  // opencl_private
+        0,  // opencl_generic
+        1,  // opencl_global_device
+        1,  // opencl_global_host
+        1,  // cuda_device
+        4,  // cuda_constant
+        3,  // cuda_shared
+        1,  // sycl_global
+        1,  // sycl_global_device
+        1,  // sycl_global_host
+        3,  // sycl_local
+        0,  // sycl_private
+        0,  // ptr32_sptr
+        0,  // ptr32_uptr
+        0,  // ptr64
+        0,  // hlsl_groupshared
+        20, // wasm_funcref
+    };
+
+    AddrSpaceMap = &SYCLNativeCPUASMap;
+    UseAddrSpaceMapMangling = true;
+  }
 }
 
 bool TargetInfo::initFeatureMap(

clang/lib/Driver/Driver.cpp

@@ -5274,6 +5274,53 @@ class OffloadingActionBuilder final {
       return needLibs;
     }
 
+    bool addSYCLNativeCPULibs(const ToolChain *TC,
+                              ActionList &DeviceLinkObjects) {
+      std::string LibSpirvFile;
+      if (Args.hasArg(options::OPT_fsycl_libspirv_path_EQ)) {
+        auto ProvidedPath =
+            Args.getLastArgValue(options::OPT_fsycl_libspirv_path_EQ).str();
+        if (llvm::sys::fs::exists(ProvidedPath))
+          LibSpirvFile = ProvidedPath;
+      } else {
+        SmallVector<StringRef, 8> LibraryPaths;
+
+        // Expected path w/out install.
+        SmallString<256> WithoutInstallPath(C.getDriver().ResourceDir);
+        llvm::sys::path::append(WithoutInstallPath, Twine("../../clc"));
+        LibraryPaths.emplace_back(WithoutInstallPath.c_str());
+
+        // Expected path w/ install.
+        SmallString<256> WithInstallPath(C.getDriver().ResourceDir);
+        llvm::sys::path::append(WithInstallPath, Twine("../../../share/clc"));
+        LibraryPaths.emplace_back(WithInstallPath.c_str());
+
+        // Select libclc variant based on target triple
+        std::string LibSpirvTargetName = "builtins.link.libspirv-";
+        LibSpirvTargetName.append(TC->getTripleString() + ".bc");
+
+        for (StringRef LibraryPath : LibraryPaths) {
+          SmallString<128> LibSpirvTargetFile(LibraryPath);
+          llvm::sys::path::append(LibSpirvTargetFile, LibSpirvTargetName);
+          if (llvm::sys::fs::exists(LibSpirvTargetFile) ||
+              Args.hasArg(options::OPT__HASH_HASH_HASH)) {
+            LibSpirvFile = std::string(LibSpirvTargetFile.str());
+            break;
+          }
+        }
+      }
+
+      if (!LibSpirvFile.empty()) {
+        Arg *LibClcInputArg = MakeInputArg(Args, C.getDriver().getOpts(),
+                                           Args.MakeArgString(LibSpirvFile));
+        auto *SYCLLibClcInputAction =
+            C.MakeAction<InputAction>(*LibClcInputArg, types::TY_LLVM_BC);
+        DeviceLinkObjects.push_back(SYCLLibClcInputAction);
+        return true;
+      }
+      return false;
+    }
+
     bool addSYCLDeviceLibs(const ToolChain *TC, ActionList &DeviceLinkObjects,
                            bool isSpirvAOT, bool isMSVCEnv) {
       struct DeviceLibOptInfo {
@@ -5684,6 +5731,9 @@ class OffloadingActionBuilder final {
               TC, DeviceLibs, UseAOTLink,
               C.getDefaultToolChain().getTriple().isWindowsMSVCEnvironment());
         }
+        if (isSYCLNativeCPU) {
+          SYCLDeviceLibLinked |= addSYCLNativeCPULibs(TC, DeviceLibs);
+        }
         JobAction *LinkSYCLLibs =
             C.MakeAction<LinkJobAction>(DeviceLibs, types::TY_LLVM_BC);
         for (Action *FullLinkObject : FullLinkObjects) {

clang/lib/Driver/ToolChains/SYCL.cpp

@@ -7,6 +7,7 @@
 //===----------------------------------------------------------------------===//
 #include "SYCL.h"
 #include "CommonArgs.h"
+#include "clang/Driver/Action.h"
 #include "clang/Driver/Compilation.h"
 #include "clang/Driver/Driver.h"
 #include "clang/Driver/DriverDiagnostic.h"
@@ -170,6 +171,8 @@ const char *SYCL::Linker::constructLLVMLinkCommand(
   // instead of the original object.
   if (JA.isDeviceOffloading(Action::OFK_SYCL)) {
     bool IsRDC = !shouldDoPerObjectFileLinking(C);
+    const bool IsSYCLNativeCPU = isSYCLNativeCPU(
+        this->getToolChain(), *C.getSingleOffloadToolChain<Action::OFK_Host>());
     auto isNoRDCDeviceCodeLink = [&](const InputInfo &II) {
       if (IsRDC)
         return false;
@@ -190,12 +193,14 @@ const char *SYCL::Linker::constructLLVMLinkCommand(
 
       std::string FileName = this->getToolChain().getInputFilename(II);
       StringRef InputFilename = llvm::sys::path::filename(FileName);
-      if (this->getToolChain().getTriple().isNVPTX()) {
+      const bool IsNVPTX = this->getToolChain().getTriple().isNVPTX();
+      if (IsNVPTX || IsSYCLNativeCPU) {
         // Linking SYCL Device libs requires libclc as well as libdevice
         if ((InputFilename.find("libspirv") != InputFilename.npos ||
              InputFilename.find("libdevice") != InputFilename.npos))
           return true;
-        LibPostfix = ".cubin";
+        if (IsNVPTX)
+          LibPostfix = ".cubin";
       }
       StringRef LibSyclPrefix("libsycl-");
       if (!InputFilename.startswith(LibSyclPrefix) ||

clang/test/Driver/sycl-native-cpu-fsycl.cpp

@@ -1,7 +1,7 @@
-//RUN: %clang -fsycl -fsycl-targets=native_cpu -ccc-print-phases %s 2>&1 | FileCheck %s --check-prefix=CHECK_ACTIONS
-//RUN: %clang -fsycl -fsycl-targets=native_cpu -ccc-print-bindings %s 2>&1 | FileCheck %s --check-prefix=CHECK_BINDINGS
-//RUN: %clang -fsycl -fsycl-targets=native_cpu -### %s 2>&1 | FileCheck %s --check-prefix=CHECK_INVO
-//RUN: %clang -fsycl -fsycl-targets=native_cpu -target aarch64-unknown-linux-gnu -ccc-print-phases %s 2>&1 | FileCheck %s --check-prefix=CHECK_ACTIONS-AARCH64
+//RUN: %clang -fsycl -fsycl-targets=native_cpu -fsycl-libspirv-path=%S/Inputs/SYCL/libspirv.bc -ccc-print-phases %s 2>&1 | FileCheck %s --check-prefix=CHECK_ACTIONS
+//RUN: %clang -fsycl -fsycl-targets=native_cpu -fsycl-libspirv-path=%S/Inputs/SYCL/libspirv.bc -ccc-print-bindings %s 2>&1 | FileCheck %s --check-prefix=CHECK_BINDINGS
+//RUN: %clang -fsycl -fsycl-targets=native_cpu -fsycl-libspirv-path=%S/Inputs/SYCL/libspirv.bc -### %s 2>&1 | FileCheck %s --check-prefix=CHECK_INVO
+//RUN: %clang -fsycl -fsycl-targets=native_cpu -fsycl-libspirv-path=%S/Inputs/SYCL/libspirv.bc -target aarch64-unknown-linux-gnu -ccc-print-phases %s 2>&1 | FileCheck %s --check-prefix=CHECK_ACTIONS-AARCH64
 
 
 //CHECK_ACTIONS:                     +- 0: input, "{{.*}}sycl-native-cpu-fsycl.cpp", c++, (host-sycl)
@@ -15,20 +15,23 @@
 //CHECK_ACTIONS:      +- 8: backend, {7}, assembler, (host-sycl)
 //CHECK_ACTIONS:   +- 9: assembler, {8}, object, (host-sycl)
 //CHECK_ACTIONS:+- 10: linker, {9}, image, (host-sycl)
+//CHECK_ACTIONS:        +- 11: linker, {5}, ir, (device-sycl)
+//CHECK_ACTIONS:        |- 12: input, "{{.*}}libspirv{{.*}}", ir, (device-sycl)
+//CHECK_ACTIONS:     +- 13: linker, {11, 12}, ir, (device-sycl)
 //this is where we compile the device code to a shared lib, and we link the host shared lib and the device shared lib
-//CHECK_ACTIONS:|     +- 11: linker, {5}, ir, (device-sycl)
-//CHECK_ACTIONS:|  +- 12: backend, {11}, assembler, (device-sycl)
-//CHECK_ACTIONS:|- 13: assembler, {12}, object, (device-sycl)
+//CHECK_ACTIONS:|  +- 14: backend, {13}, assembler, (device-sycl)
+//CHECK_ACTIONS:|- 15: assembler, {14}, object, (device-sycl)
 //call sycl-post-link and clang-offload-wrapper
-//CHECK_ACTIONS:|  +- 14: sycl-post-link, {11}, tempfiletable, (device-sycl)
-//CHECK_ACTIONS:|- 15: clang-offload-wrapper, {14}, object, (device-sycl)
-//CHECK_ACTIONS:16: offload, "host-sycl ({{.*}})" {10}, "device-sycl ({{.*}})" {13}, "device-sycl ({{.*}})" {15}, image
+//CHECK_ACTIONS:|  +- 16: sycl-post-link, {13}, tempfiletable, (device-sycl)
+//CHECK_ACTIONS:|- 17: clang-offload-wrapper, {16}, object, (device-sycl)
+//CHECK_ACTIONS:18: offload, "host-sycl ({{.*}})" {10}, "device-sycl ({{.*}})" {15}, "device-sycl ({{.*}})" {17}, image
 
 
 //CHECK_BINDINGS:# "{{.*}}" - "clang", inputs: ["{{.*}}sycl-native-cpu-fsycl.cpp"], output: "[[KERNELIR:.*]].bc"
 //CHECK_BINDINGS:# "{{.*}}" - "SYCL::Linker", inputs: ["[[KERNELIR]].bc"], output: "[[KERNELLINK:.*]].bc"
-//CHECK_BINDINGS:# "{{.*}}" - "clang", inputs: ["[[KERNELLINK]].bc"], output: "[[KERNELOBJ:.*]].o"
-//CHECK_BINDINGS:# "{{.*}}" - "SYCL post link", inputs: ["[[KERNELLINK]].bc"], output: "[[TABLEFILE:.*]].table"
+//CHECK_BINDINGS:# "{{.*}}" - "SYCL::Linker", inputs: ["[[KERNELLINK]].bc", "{{.*}}.bc"], output: "[[KERNELLINKWLIB:.*]].bc"
+//CHECK_BINDINGS:# "{{.*}}" - "clang", inputs: ["[[KERNELLINKWLIB]].bc"], output: "[[KERNELOBJ:.*]].o"
+//CHECK_BINDINGS:# "{{.*}}" - "SYCL post link", inputs: ["[[KERNELLINKWLIB]].bc"], output: "[[TABLEFILE:.*]].table"
 //CHECK_BINDINGS:# "{{.*}}" - "offload wrapper", inputs: ["[[TABLEFILE]].table"], output: "[[WRAPPEROBJ:.*]].o"
 //CHECK_BINDINGS:# "{{.*}}" - "Append Footer to source", inputs: ["{{.*}}sycl-native-cpu-fsycl.cpp"], output: "[[SRCWFOOTER:.*]].cpp"
 //CHECK_BINDINGS:# "{{.*}}" - "clang", inputs: ["[[SRCWFOOTER]].cpp", "[[KERNELIR]].bc"], output: "[[HOSTOBJ:.*]].o"
@@ -38,21 +41,6 @@
 //CHECK_INVO:{{.*}}clang{{.*}}"-x" "ir"
 //CHECK_INVO:{{.*}}clang{{.*}}"-fsycl-is-host"{{.*}}
 
-// checkes that the device and host triple is correct in the generated actions when it is set explicitly
-//CHECK_ACTIONS-AARCH64:                     +- 0: input, "{{.*}}sycl-native-cpu-fsycl.cpp", c++, (host-sycl)
-//CHECK_ACTIONS-AARCH64:                  +- 1: append-footer, {0}, c++, (host-sycl)
-//CHECK_ACTIONS-AARCH64:               +- 2: preprocessor, {1}, c++-cpp-output, (host-sycl)
-//CHECK_ACTIONS-AARCH64:               |     +- 3: input, "{{.*}}sycl-native-cpu-fsycl.cpp", c++, (device-sycl)
-//CHECK_ACTIONS-AARCH64:               |  +- 4: preprocessor, {3}, c++-cpp-output, (device-sycl)
-//CHECK_ACTIONS-AARCH64:               |- 5: compiler, {4}, ir, (device-sycl)
+// checks that the device and host triple is correct in the generated actions when it is set explicitly
 //CHECK_ACTIONS-AARCH64:            +- 6: offload, "host-sycl (aarch64-unknown-linux-gnu)" {2}, "device-sycl (aarch64-unknown-linux-gnu)" {5}, c++-cpp-output
-//CHECK_ACTIONS-AARCH64:         +- 7: compiler, {6}, ir, (host-sycl)
-//CHECK_ACTIONS-AARCH64:      +- 8: backend, {7}, assembler, (host-sycl)
-//CHECK_ACTIONS-AARCH64:   +- 9: assembler, {8}, object, (host-sycl)
-//CHECK_ACTIONS-AARCH64:+- 10: linker, {9}, image, (host-sycl)
-//CHECK_ACTIONS-AARCH64:|     +- 11: linker, {5}, ir, (device-sycl)
-//CHECK_ACTIONS-AARCH64:|  +- 12: backend, {11}, assembler, (device-sycl)
-//CHECK_ACTIONS-AARCH64:|- 13: assembler, {12}, object, (device-sycl)
-//CHECK_ACTIONS-AARCH64:|  +- 14: sycl-post-link, {11}, tempfiletable, (device-sycl)
-//CHECK_ACTIONS-AARCH64:|- 15: clang-offload-wrapper, {14}, object, (device-sycl)
-//CHECK_ACTIONS-AARCH64:16: offload, "host-sycl (aarch64-unknown-linux-gnu)" {10}, "device-sycl (aarch64-unknown-linux-gnu)" {13}, "device-sycl (aarch64-unknown-linux-gnu)" {15}, image
+//CHECK_ACTIONS-AARCH64:{{[0-9]*}}: offload, "host-sycl (aarch64-unknown-linux-gnu)" {{{[0-9]*}}}, "device-sycl (aarch64-unknown-linux-gnu)" {{{[0-9]*}}}, "device-sycl (aarch64-unknown-linux-gnu)" {{{[0-9]*}}}, image

libclc/CMakeLists.txt

@@ -181,6 +181,8 @@ set( nvptx--nvidiacl_devices none )
 set( nvptx64--nvidiacl_devices none )
 set( spirv-mesa3d-_devices none )
 set( spirv64-mesa3d-_devices none )
+# TODO: Does this need to be set for each possible triple?
+set( x86_64-unknown-linux-gnu_devices none )
 
 # Setup aliases
 set( cedar_aliases palm sumo sumo2 redwood juniper )
@@ -342,6 +344,10 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} )
 				# AMDGCN needs libclc to be compiled to high bc version since all atomic
 				# clang builtins need to be accessible
 				set( flags "SHELL:-mcpu=gfx940")
+      elseif( ${ARCH}  STREQUAL x86_64)
+        # TODO: This is used by native cpu, we should define an option to set this flags
+        set( flags "SHELL:-Xclang -target-feature -Xclang +avx"
+            "SHELL:-Xclang -target-feature -Xclang +avx512f")
 			else()
 				set ( flags )
 			endif()

libclc/generic/libspirv/SOURCES

@@ -1,3 +1,7 @@
+atomic/loadstore_helpers_unordered.ll
+atomic/loadstore_helpers_release.ll
+atomic/loadstore_helpers_acquire.ll
+atomic/loadstore_helpers_seq_cst.ll
 float16.cl
 subnormal_config.cl
 subnormal_helper_func.ll

libclc/generic/libspirv/atomic/loadstore_helpers_acquire.ll

@@ -0,0 +1,58 @@
+#if __clang_major__ >= 7
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+#else
+target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+#endif
+; This file contains helper functions for the acquire memory ordering constraint.
+; Other targets can specialize this file to account for unsupported features in their backend.
+
+declare void @llvm.trap()
+
+define i32 @__clc__atomic_load_global_4_acquire(i32 addrspace(1)* nocapture %ptr) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define i32 @__clc__atomic_load_local_4_acquire(i32 addrspace(3)* nocapture %ptr) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define i64 @__clc__atomic_load_global_8_acquire(i64 addrspace(1)* nocapture %ptr) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define i64 @__clc__atomic_load_local_8_acquire(i64 addrspace(3)* nocapture %ptr) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define i32 @__clc__atomic_uload_global_4_acquire(i32 addrspace(1)* nocapture %ptr) nounwind alwaysinline {
+entry:
+  %0 = load atomic volatile i32, i32 addrspace(1)* %ptr acquire, align 4
+  ret i32 %0
+}
+
+define i32 @__clc__atomic_uload_local_4_acquire(i32 addrspace(3)* nocapture %ptr) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define i64 @__clc__atomic_uload_global_8_acquire(i64 addrspace(1)* nocapture %ptr) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define i64 @__clc__atomic_uload_local_8_acquire(i64 addrspace(3)* nocapture %ptr) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+

libclc/generic/libspirv/atomic/loadstore_helpers_release.ll

@@ -0,0 +1,58 @@
+#if __clang_major__ >= 7
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+#else
+target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+#endif
+; This file contains helper functions for the release memory ordering constraint.
+; Other targets can specialize this file to account for unsupported features in their backend.
+
+declare void @llvm.trap()
+
+define void @__clc__atomic_store_global_4_release(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define void @__clc__atomic_store_local_4_release(i32 addrspace(3)* nocapture %ptr, i32 %value) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define void @__clc__atomic_store_global_8_release(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define void @__clc__atomic_store_local_8_release(i64 addrspace(3)* nocapture %ptr, i64 %value) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define void @__clc__atomic_ustore_global_4_release(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define void @__clc__atomic_ustore_local_4_release(i32 addrspace(3)* nocapture %ptr, i32 %value) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define void @__clc__atomic_ustore_global_8_release(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+
+define void @__clc__atomic_ustore_local_8_release(i64 addrspace(3)* nocapture %ptr, i64 %value) nounwind alwaysinline {
+entry:
+  tail call void @llvm.trap()
+  unreachable
+}
+