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[X86][GlobalISel] Improve carry value selection (#146586)
Generally G_UADDE, G_UADDO, G_USUBE, G_USUBO are used together and it was enough to simply define EFLAGS. But if extractvalue is used, we end up with a copy of EFLAGS into GPR. Always generate SETB instruction to put the carry bit on GPR and CMP to set the carry bit back. It gives the correct lowering in all the cases. Closes #120029
1 parent d81ffd4 commit 706ffa1

14 files changed

+171
-101
lines changed

‎llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp‎

Lines changed: 20 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1164,14 +1164,13 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
11641164
I.getOpcode() == TargetOpcode::G_USUBO) &&
11651165
"unexpected instruction");
11661166

1167-
const Register DstReg = I.getOperand(0).getReg();
1168-
const Register CarryOutReg = I.getOperand(1).getReg();
1169-
const Register Op0Reg = I.getOperand(2).getReg();
1170-
const Register Op1Reg = I.getOperand(3).getReg();
1171-
bool IsSub = I.getOpcode() == TargetOpcode::G_USUBE ||
1172-
I.getOpcode() == TargetOpcode::G_USUBO;
1173-
bool HasCarryIn = I.getOpcode() == TargetOpcode::G_UADDE ||
1174-
I.getOpcode() == TargetOpcode::G_USUBE;
1167+
auto &CarryMI = cast<GAddSubCarryOut>(I);
1168+
1169+
const Register DstReg = CarryMI.getDstReg();
1170+
const Register CarryOutReg = CarryMI.getCarryOutReg();
1171+
const Register Op0Reg = CarryMI.getLHSReg();
1172+
const Register Op1Reg = CarryMI.getRHSReg();
1173+
bool IsSub = CarryMI.isSub();
11751174

11761175
const LLT DstTy = MRI.getType(DstReg);
11771176
assert(DstTy.isScalar() && "selectUAddSub only supported for scalar types");
@@ -1207,14 +1206,15 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
12071206
llvm_unreachable("selectUAddSub unsupported type.");
12081207
}
12091208

1210-
const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
1211-
const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
1209+
const RegisterBank &CarryRB = *RBI.getRegBank(CarryOutReg, MRI, TRI);
1210+
const TargetRegisterClass *CarryRC =
1211+
getRegClass(MRI.getType(CarryOutReg), CarryRB);
12121212

12131213
unsigned Opcode = IsSub ? OpSUB : OpADD;
12141214

12151215
// G_UADDE/G_USUBE - find CarryIn def instruction.
1216-
if (HasCarryIn) {
1217-
Register CarryInReg = I.getOperand(4).getReg();
1216+
if (auto CarryInMI = dyn_cast<GAddSubCarryInOut>(&I)) {
1217+
Register CarryInReg = CarryInMI->getCarryInReg();
12181218
MachineInstr *Def = MRI.getVRegDef(CarryInReg);
12191219
while (Def->getOpcode() == TargetOpcode::G_TRUNC) {
12201220
CarryInReg = Def->getOperand(1).getReg();
@@ -1227,11 +1227,12 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
12271227
Def->getOpcode() == TargetOpcode::G_USUBE ||
12281228
Def->getOpcode() == TargetOpcode::G_USUBO) {
12291229
// carry set by prev ADD/SUB.
1230-
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY),
1231-
X86::EFLAGS)
1232-
.addReg(CarryInReg);
12331230

1234-
if (!RBI.constrainGenericRegister(CarryInReg, *DstRC, MRI))
1231+
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::CMP8ri))
1232+
.addReg(CarryInReg)
1233+
.addImm(1);
1234+
1235+
if (!RBI.constrainGenericRegister(CarryInReg, *CarryRC, MRI))
12351236
return false;
12361237

12371238
Opcode = IsSub ? OpSBB : OpADC;
@@ -1250,11 +1251,11 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
12501251
.addReg(Op0Reg)
12511252
.addReg(Op1Reg);
12521253

1253-
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg)
1254-
.addReg(X86::EFLAGS);
1254+
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), CarryOutReg)
1255+
.addImm(X86::COND_B);
12551256

12561257
if (!constrainSelectedInstRegOperands(Inst, TII, TRI, RBI) ||
1257-
!RBI.constrainGenericRegister(CarryOutReg, *DstRC, MRI))
1258+
!RBI.constrainGenericRegister(CarryOutReg, *CarryRC, MRI))
12581259
return false;
12591260

12601261
I.eraseFromParent();

‎llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -194,11 +194,11 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
194194
.scalarize(0);
195195

196196
getActionDefinitionsBuilder({G_UADDE, G_UADDO, G_USUBE, G_USUBO})
197-
.legalFor({{s8, s1}, {s16, s1}, {s32, s1}})
198-
.legalFor(Is64Bit, {{s64, s1}})
197+
.legalFor({{s8, s8}, {s16, s8}, {s32, s8}})
198+
.legalFor(Is64Bit, {{s64, s8}})
199199
.widenScalarToNextPow2(0, /*Min=*/32)
200200
.clampScalar(0, s8, sMaxScalar)
201-
.clampScalar(1, s1, s1)
201+
.clampScalar(1, s8, s8)
202202
.scalarize(0);
203203

204204
// integer multiply

‎llvm/test/CodeGen/X86/GlobalISel/add-scalar.ll‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,15 @@ define i128 @test_add_i128(i128 %arg1, i128 %arg2) nounwind {
77
; X64: # %bb.0:
88
; X64-NEXT: movq %rdx, %rax
99
; X64-NEXT: addq %rdi, %rax
10+
; X64-NEXT: setb %dl
11+
; X64-NEXT: cmpb $1, %dl
1012
; X64-NEXT: adcq %rsi, %rcx
1113
; X64-NEXT: movq %rcx, %rdx
1214
; X64-NEXT: retq
1315
;
1416
; X86-LABEL: test_add_i128:
1517
; X86: # %bb.0:
18+
; X86-NEXT: pushl %ebx
1619
; X86-NEXT: pushl %edi
1720
; X86-NEXT: pushl %esi
1821
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -21,15 +24,22 @@ define i128 @test_add_i128(i128 %arg1, i128 %arg2) nounwind {
2124
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
2225
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
2326
; X86-NEXT: addl {{[0-9]+}}(%esp), %ecx
27+
; X86-NEXT: setb %bl
28+
; X86-NEXT: cmpb $1, %bl
2429
; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx
30+
; X86-NEXT: setb %bl
31+
; X86-NEXT: cmpb $1, %bl
2532
; X86-NEXT: adcl {{[0-9]+}}(%esp), %esi
33+
; X86-NEXT: setb %bl
34+
; X86-NEXT: cmpb $1, %bl
2635
; X86-NEXT: adcl {{[0-9]+}}(%esp), %edi
2736
; X86-NEXT: movl %ecx, (%eax)
2837
; X86-NEXT: movl %edx, 4(%eax)
2938
; X86-NEXT: movl %esi, 8(%eax)
3039
; X86-NEXT: movl %edi, 12(%eax)
3140
; X86-NEXT: popl %esi
3241
; X86-NEXT: popl %edi
42+
; X86-NEXT: popl %ebx
3343
; X86-NEXT: retl
3444
%ret = add i128 %arg1, %arg2
3545
ret i128 %ret
@@ -46,6 +56,8 @@ define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
4656
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
4757
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
4858
; X86-NEXT: addl {{[0-9]+}}(%esp), %eax
59+
; X86-NEXT: setb %cl
60+
; X86-NEXT: cmpb $1, %cl
4961
; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx
5062
; X86-NEXT: retl
5163
%ret = add i64 %arg1, %arg2

‎llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -157,8 +157,8 @@ body: |
157157
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
158158
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
159159
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
160-
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
161-
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
160+
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[UV]], [[UV2]]
161+
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
162162
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
163163
; X86-NEXT: $rax = COPY [[MV]](s64)
164164
; X86-NEXT: RET 0
@@ -192,8 +192,8 @@ body: |
192192
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
193193
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
194194
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
195-
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
196-
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
195+
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[UV]], [[UV2]]
196+
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
197197
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
198198
; X86-NEXT: $rax = COPY [[MV]](s64)
199199
; X86-NEXT: RET 0
@@ -219,8 +219,8 @@ body: |
219219
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
220220
; X64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](s128)
221221
; X64-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF1]](s128)
222-
; X64-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV2]]
223-
; X64-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
222+
; X64-NEXT: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[UV]], [[UV2]]
223+
; X64-NEXT: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[UV1]], [[UV3]], [[UADDO1]]
224224
; X64-NEXT: $rax = COPY [[UADDO]](s64)
225225
; X64-NEXT: $rdx = COPY [[UADDE]](s64)
226226
; X64-NEXT: RET 0
@@ -230,10 +230,10 @@ body: |
230230
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
231231
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
232232
; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
233-
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[UV]], [[UV4]]
234-
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV5]], [[UADDO1]]
235-
; X86-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV2]], [[UV6]], [[UADDE1]]
236-
; X86-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[UV3]], [[UV7]], [[UADDE3]]
233+
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[UV]], [[UV4]]
234+
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[UV1]], [[UV5]], [[UADDO1]]
235+
; X86-NEXT: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s8) = G_UADDE [[UV2]], [[UV6]], [[UADDE1]]
236+
; X86-NEXT: [[UADDE4:%[0-9]+]]:_(s32), [[UADDE5:%[0-9]+]]:_(s8) = G_UADDE [[UV3]], [[UV7]], [[UADDE3]]
237237
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDO]](s32), [[UADDE]](s32)
238238
; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE2]](s32), [[UADDE4]](s32)
239239
; X86-NEXT: $rax = COPY [[MV]](s64)

‎llvm/test/CodeGen/X86/GlobalISel/legalize-leading-zeros.mir‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ body: |
2525
; X64-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[CTLZ]], [[C1]]
2626
; X64-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C]]
2727
; X64-NEXT: RET 0, implicit [[AND1]](s64)
28+
;
2829
; X86-LABEL: name: test_ctlz35
2930
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
3031
; X86-NEXT: [[TRUNC:%[0-9]+]]:_(s35) = G_TRUNC [[COPY]](s64)
@@ -46,12 +47,15 @@ body: |
4647
; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C2]](s32), [[C]](s32)
4748
; X86-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
4849
; X86-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV1]](s64)
49-
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV6]], [[UV8]]
50-
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV7]], [[UV9]], [[USUBO1]]
50+
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV6]], [[UV8]]
51+
; X86-NEXT: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[USUBO1]](s8)
52+
; X86-NEXT: [[ZEXT2:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC1]](s1)
53+
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV7]], [[UV9]], [[ZEXT2]]
54+
; X86-NEXT: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[USUBE1]](s8)
5155
; X86-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
52-
; X86-NEXT: [[TRUNC1:%[0-9]+]]:_(s35) = G_TRUNC [[MV2]](s64)
53-
; X86-NEXT: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s35)
54-
; X86-NEXT: RET 0, implicit [[ZEXT2]](s64)
56+
; X86-NEXT: [[TRUNC3:%[0-9]+]]:_(s35) = G_TRUNC [[MV2]](s64)
57+
; X86-NEXT: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC3]](s35)
58+
; X86-NEXT: RET 0, implicit [[ZEXT3]](s64)
5559
%0(s64) = COPY $rdx
5660
%1:_(s35) = G_TRUNC %0(s64)
5761
%2:_(s35) = G_CTLZ %1
@@ -97,6 +101,7 @@ body: |
97101
; X64-NEXT: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[DEF]](s64)
98102
; X64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[CTLZ]](s64)
99103
; X64-NEXT: RET 0, implicit [[COPY]](s64)
104+
;
100105
; X86-LABEL: name: test_ctlz64
101106
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
102107
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)

‎llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -157,8 +157,8 @@ body: |
157157
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
158158
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
159159
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
160-
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
161-
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
160+
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV2]]
161+
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
162162
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
163163
; X86-NEXT: $rax = COPY [[MV]](s64)
164164
; X86-NEXT: RET 0
@@ -192,8 +192,8 @@ body: |
192192
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
193193
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
194194
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
195-
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
196-
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
195+
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV2]]
196+
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
197197
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
198198
; X86-NEXT: $rax = COPY [[MV]](s64)
199199
; X86-NEXT: RET 0
@@ -219,8 +219,8 @@ body: |
219219
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
220220
; X64-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF]](s128)
221221
; X64-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[DEF1]](s128)
222-
; X64-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
223-
; X64-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
222+
; X64-NEXT: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV2]]
223+
; X64-NEXT: [[USUBE:%[0-9]+]]:_(s64), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
224224
; X64-NEXT: $rax = COPY [[USUBO]](s64)
225225
; X64-NEXT: $rdx = COPY [[USUBE]](s64)
226226
; X64-NEXT: RET 0
@@ -230,10 +230,10 @@ body: |
230230
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s128) = IMPLICIT_DEF
231231
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s128)
232232
; X86-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s128)
233-
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV4]]
234-
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV5]], [[USUBO1]]
235-
; X86-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s1) = G_USUBE [[UV2]], [[UV6]], [[USUBE1]]
236-
; X86-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s1) = G_USUBE [[UV3]], [[UV7]], [[USUBE3]]
233+
; X86-NEXT: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s8) = G_USUBO [[UV]], [[UV4]]
234+
; X86-NEXT: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s8) = G_USUBE [[UV1]], [[UV5]], [[USUBO1]]
235+
; X86-NEXT: [[USUBE2:%[0-9]+]]:_(s32), [[USUBE3:%[0-9]+]]:_(s8) = G_USUBE [[UV2]], [[UV6]], [[USUBE1]]
236+
; X86-NEXT: [[USUBE4:%[0-9]+]]:_(s32), [[USUBE5:%[0-9]+]]:_(s8) = G_USUBE [[UV3]], [[UV7]], [[USUBE3]]
237237
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
238238
; X86-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBE2]](s32), [[USUBE4]](s32)
239239
; X86-NEXT: $rax = COPY [[MV]](s64)

‎llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros-undef.mir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@ body: |
3232
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
3333
; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
3434
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
35-
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
36-
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
35+
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
36+
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
3737
; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
3838
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
3939
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -97,8 +97,8 @@ body: |
9797
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[UV]](s32), [[C]]
9898
; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s32)
9999
; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
100-
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C1]]
101-
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
100+
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C1]]
101+
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
102102
; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
103103
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
104104
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1

‎llvm/test/CodeGen/X86/GlobalISel/legalize-trailing-zeros.mir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,8 @@ body: |
3232
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
3333
; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
3434
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
35-
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
36-
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
35+
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ_ZERO_UNDEF]], [[C2]]
36+
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
3737
; X86-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
3838
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
3939
; X86-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -99,8 +99,8 @@ body: |
9999
; X86-NEXT: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(eq), [[UV]](s32), [[C]]
100100
; X86-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[UV1]](s32)
101101
; X86-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
102-
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[CTTZ]], [[C1]]
103-
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[C]], [[C]], [[UADDO1]]
102+
; X86-NEXT: [[UADDO:%[0-9]+]]:_(s32), [[UADDO1:%[0-9]+]]:_(s8) = G_UADDO [[CTTZ]], [[C1]]
103+
; X86-NEXT: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s8) = G_UADDE [[C]], [[C]], [[UADDO1]]
104104
; X86-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
105105
; X86-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
106106
; X86-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1

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