Revert "[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants"

david-arm · david-arm · commit ba471ba8d2a3 · 2022-01-13T15:59:43.000Z
This reverts commit 31009f0. It seems to be causing SVE VLA buildbot failures and has introduced a genuine regression. Reverting for now.
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2647,9 +2647,9 @@ class TargetLoweringBase {
                       getApproximateEVTForLLT(ToTy, DL, Ctx));
   }
 
-  /// Return true if sign-extension of value \p V from FromTy to ToTy is
-  /// cheaper than zero-extension, where \p V can be SDValue() if unknown.
-  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy, SDValue V) const {
+  /// Return true if sign-extension from FromTy to ToTy is cheaper than
+  /// zero-extension.
+  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
     return false;
   }
 
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -7004,7 +7004,7 @@ bool CodeGenPrepare::optimizeSwitchInst(SwitchInst *SI) {
   // matching the argument extension instead.
   Instruction::CastOps ExtType = Instruction::ZExt;
   // Some targets prefer SExt over ZExt.
-  if (TLI->isSExtCheaperThanZExt(OldVT, RegType, SDValue()))
+  if (TLI->isSExtCheaperThanZExt(OldVT, RegType))
     ExtType = Instruction::SExt;
 
   if (auto *Arg = dyn_cast<Argument>(Cond)) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1704,7 +1704,7 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
   SDValue OpL = GetPromotedInteger(LHS);
   SDValue OpR = GetPromotedInteger(RHS);
 
-  if (TLI.isSExtCheaperThanZExt(LHS.getValueType(), OpL.getValueType(), LHS)) {
+  if (TLI.isSExtCheaperThanZExt(LHS.getValueType(), OpL.getValueType())) {
     // The target would prefer to promote the comparison operand with sign
     // extension. Honor that unless the promoted values are already zero
     // extended.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -283,7 +283,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
     EVT OldVT = Op.getValueType();
     SDLoc DL(Op);
     Op = GetPromotedInteger(Op);
-    if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType(), Op))
+    if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType()))
       return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
                          DAG.getValueType(OldVT));
     return DAG.getZeroExtendInReg(Op, DL, OldVT);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4767,7 +4767,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
                          C->isTargetOpcode(), C->isOpaque());
     case ISD::ANY_EXTEND:
       // Some targets like RISCV prefer to sign extend some types.
-      if (TLI->isSExtCheaperThanZExt(Operand.getValueType(), VT, Operand))
+      if (TLI->isSExtCheaperThanZExt(Operand.getValueType(), VT))
         return getConstant(Val.sextOrTrunc(VT.getSizeInBits()), DL, VT,
                            C->isTargetOpcode(), C->isOpaque());
       return getConstant(Val.zextOrTrunc(VT.getSizeInBits()), DL, VT,
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3844,7 +3844,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
     } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
                (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
                !isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(),
-                                      OpVT, N0.getOperand(1))) {
+                                      OpVT)) {
       EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
       unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
       EVT ExtDstTy = N0.getValueType();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -1138,14 +1138,6 @@ class AArch64TargetLowering : public TargetLowering {
 
   bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
                                               LLT Ty2) const override;
-
-  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT, SDValue V) const override {
-    if (!V)
-      return false;
-    if (ConstantSDNode *C = isConstOrConstSplat(V))
-      return C->getAPIntValue().isNegative();
-    return false;
-  }
 };
 
 namespace AArch64 {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1198,8 +1198,7 @@ bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
   return TargetLowering::isZExtFree(Val, VT2);
 }
 
-bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT,
-                                                SDValue V) const {
+bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
   return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -326,7 +326,7 @@ class RISCVTargetLowering : public TargetLowering {
   bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
   bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
   bool isZExtFree(SDValue Val, EVT VT2) const override;
-  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT, SDValue V) const override;
+  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
   bool isCheapToSpeculateCttz() const override;
   bool isCheapToSpeculateCtlz() const override;
   bool hasAndNotCompare(SDValue Y) const override;
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll b/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
@@ -14,8 +14,18 @@ entry:
   ret <8 x i1> %Shuff
 }
 
+; CHECK: lCPI1_0:
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   1                       ; 0x1
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   0                       ; 0x0
+; CHECK:          .byte   0                       ; 0x0
 ; CHECK: test2
-; CHECK: movi    d{{[0-9]+}}, #0x0000ff00000000
+; CHECK: adrp    x[[REG2:[0-9]+]], lCPI1_0@PAGE
+; CHECK: ldr     d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF]
 define <8 x i1>@test2() {
 bb:
   %Shuff = shufflevector <8 x i1> zeroinitializer,
@@ -26,7 +36,7 @@ bb:
 }
 
 ; CHECK: test3
-; CHECK: movi.2d v{{[0-9]+}}, #0x0000ff000000ff
+; CHECK: movi.4s v{{[0-9]+}}, #1
 define <16 x i1> @test3(i1* %ptr, i32 %v) {
 bb:
   %Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef,
@@ -35,13 +45,11 @@ bb:
                  i32 14, i32 0>
   ret <16 x i1> %Shuff
 }
-
-
 ; CHECK: lCPI3_0:
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
-; CHECK:         .byte   255                     ; 0xff
+; CHECK:         .byte   1                       ; 0x1
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
 ; CHECK:         .byte   0                       ; 0x0
diff --git a/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll b/llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
@@ -249,7 +249,7 @@ define {i8*, i1} @test_cmpxchg_ptr(i8** %addr, i8* %cmp, i8* %new) {
 ; CHECK:     stlxr [[SUCCESS:w[0-9]+]], w2, [x0]
 ; CHECK:     cbnz [[SUCCESS]], [[LOOP]]
 
-; CHECK:     mov w1, #-1
+; CHECK:     mov w1, #1
 ; CHECK:     mov w0, [[OLD]]
 ; CHECK:     ret
 
diff --git a/llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll b/llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
@@ -15,7 +15,7 @@ define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) {
 ; CHECK-NEXT:    stlxr w8, w2, [x0]
 ; CHECK-NEXT:    cbnz w8, LBB0_1
 ; CHECK-NEXT:  ; %bb.3:
-; CHECK-NEXT:    mov w0, #-1
+; CHECK-NEXT:    mov w0, #1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  LBB0_4: ; %cmpxchg.nostore
 ; CHECK-NEXT:    mov w0, wzr
@@ -64,7 +64,7 @@ define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) {
 ; CHECK-NEXT:    stlxrb w9, w2, [x0]
 ; CHECK-NEXT:    cbnz w9, LBB1_1
 ; CHECK-NEXT:  ; %bb.3:
-; CHECK-NEXT:    mov w8, #-1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    eor w0, w8, #0x1
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  LBB1_4: ; %cmpxchg.nostore
@@ -188,7 +188,7 @@ define i1 @test_conditional2(i32 %a, i32 %b, i32* %c) {
 ; CHECK-NEXT:    stlxr w8, w20, [x19]
 ; CHECK-NEXT:    cbnz w8, LBB3_1
 ; CHECK-NEXT:  ; %bb.3:
-; CHECK-NEXT:    mov w8, #-1
+; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    b LBB3_5
 ; CHECK-NEXT:  LBB3_4: ; %cmpxchg.nostore
 ; CHECK-NEXT:    mov w8, wzr
diff --git a/llvm/test/CodeGen/AArch64/dag-numsignbits.ll b/llvm/test/CodeGen/AArch64/dag-numsignbits.ll
@@ -8,13 +8,18 @@ define void @signbits_vXi1(<4 x i16> %a1) {
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI0_0
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    movi v2.4h, #1
-; CHECK-NEXT:    dup v0.4h, v0.h[0]
 ; CHECK-NEXT:    mov w1, wzr
+; CHECK-NEXT:    dup v0.4h, v0.h[0]
 ; CHECK-NEXT:    mov w2, wzr
 ; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_0]
+; CHECK-NEXT:    adrp x8, .LCPI0_1
 ; CHECK-NEXT:    add v0.4h, v0.4h, v1.4h
-; CHECK-NEXT:    cmgt v0.4h, v2.4h, v0.4h
+; CHECK-NEXT:    movi v1.4h, #1
+; CHECK-NEXT:    cmgt v0.4h, v1.4h, v0.4h
+; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_1]
+; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
+; CHECK-NEXT:    shl v0.4h, v0.4h, #15
+; CHECK-NEXT:    cmlt v0.4h, v0.4h, #0
 ; CHECK-NEXT:    umov w0, v0.h[0]
 ; CHECK-NEXT:    umov w3, v0.h[3]
 ; CHECK-NEXT:    b foo
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll b/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
@@ -25,10 +25,8 @@ bb2:
 define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) {
 ; CHECK-LABEL: icmp_constfold_v2i32:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    movi.2d v0, #0xffffffffffffffff
-; CHECK-NEXT:  ; %bb.1: ; %bb2
-; CHECK-NEXT:    movi.2s v1, #1
-; CHECK-NEXT:    and.8b v0, v0, v1
+; CHECK-NEXT:    movi.2s v0, #1
+; CHECK-NEXT:    and.8b v0, v0, v0
 ; CHECK-NEXT:    ret
   %1 = icmp eq <2 x i32> %a, %a
   br label %bb2
@@ -57,10 +55,9 @@ bb2:
 define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) {
 ; CHECK-LABEL: icmp_constfold_v4i32:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    movi.2d v0, #0xffffffffffffffff
+; CHECK-NEXT:    movi.4h v0, #1
 ; CHECK-NEXT:  ; %bb.1: ; %bb2
-; CHECK-NEXT:    movi.4h v1, #1
-; CHECK-NEXT:    and.8b v0, v0, v1
+; CHECK-NEXT:    and.8b v0, v0, v0
 ; CHECK-NEXT:    ushll.4s v0, v0, #0
 ; CHECK-NEXT:    ret
   %1 = icmp eq <4 x i32> %a, %a
@@ -88,10 +85,8 @@ bb2:
 define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: icmp_constfold_v16i8:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT:    movi.2d v0, #0xffffffffffffffff
-; CHECK-NEXT:  ; %bb.1: ; %bb2
-; CHECK-NEXT:    movi.16b v1, #1
-; CHECK-NEXT:    and.16b v0, v0, v1
+; CHECK-NEXT:    movi.16b v0, #1
+; CHECK-NEXT:    and.16b v0, v0, v0
 ; CHECK-NEXT:    ret
   %1 = icmp eq <16 x i8> %a, %a
   br label %bb2
diff --git a/llvm/test/CodeGen/AArch64/funnel-shift.ll b/llvm/test/CodeGen/AArch64/funnel-shift.ll
@@ -93,7 +93,7 @@ declare i7 @llvm.fshl.i7(i7, i7, i7)
 define i7 @fshl_i7_const_fold() {
 ; CHECK-LABEL: fshl_i7_const_fold:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #-61
+; CHECK-NEXT:    mov w0, #67
 ; CHECK-NEXT:    ret
   %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
   ret i7 %f
@@ -102,7 +102,7 @@ define i7 @fshl_i7_const_fold() {
 define i8 @fshl_i8_const_fold_overshift_1() {
 ; CHECK-LABEL: fshl_i8_const_fold_overshift_1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #-128
+; CHECK-NEXT:    mov w0, #128
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)
   ret i8 %f
@@ -164,7 +164,7 @@ define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
 define i8 @fshl_i8_const_fold() {
 ; CHECK-LABEL: fshl_i8_const_fold:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #-128
+; CHECK-NEXT:    mov w0, #128
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
   ret i8 %f
@@ -241,7 +241,7 @@ define i7 @fshr_i7_const_fold() {
 define i8 @fshr_i8_const_fold_overshift_1() {
 ; CHECK-LABEL: fshr_i8_const_fold_overshift_1:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #-2
+; CHECK-NEXT:    mov w0, #254
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)
   ret i8 %f
@@ -250,7 +250,7 @@ define i8 @fshr_i8_const_fold_overshift_1() {
 define i8 @fshr_i8_const_fold_overshift_2() {
 ; CHECK-LABEL: fshr_i8_const_fold_overshift_2:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #-31
+; CHECK-NEXT:    mov w0, #225
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11)
   ret i8 %f
@@ -259,7 +259,7 @@ define i8 @fshr_i8_const_fold_overshift_2() {
 define i8 @fshr_i8_const_fold_overshift_3() {
 ; CHECK-LABEL: fshr_i8_const_fold_overshift_3:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #-1
+; CHECK-NEXT:    mov w0, #255
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)
   ret i8 %f
@@ -303,7 +303,7 @@ define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
 define i8 @fshr_i8_const_fold() {
 ; CHECK-LABEL: fshr_i8_const_fold:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w0, #-2
+; CHECK-NEXT:    mov w0, #254
 ; CHECK-NEXT:    ret
   %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
   ret i8 %f
diff --git a/llvm/test/CodeGen/AArch64/reduce-and.ll b/llvm/test/CodeGen/AArch64/reduce-and.ll
@@ -223,7 +223,8 @@ define i8 @test_redand_v3i8(<3 x i8> %a) {
 ; CHECK-LABEL: test_redand_v3i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, w1
-; CHECK-NEXT:    and w0, w8, w2
+; CHECK-NEXT:    and w8, w8, w2
+; CHECK-NEXT:    and w0, w8, #0xff
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_redand_v3i8:
diff --git a/llvm/test/CodeGen/AArch64/redundant-copy-elim-empty-mbb.ll b/llvm/test/CodeGen/AArch64/redundant-copy-elim-empty-mbb.ll
@@ -9,7 +9,7 @@ declare i8* @bar()
 
 ; CHECK-LABEL: foo:
 ; CHECK: tbz
-; CHECK: mov{{.*}}, #-1
+; CHECK: mov{{.*}}, #1
 ; CHECK: ret
 ; CHECK: bl bar
 ; CHECK: cbnz
diff --git a/llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll b/llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
@@ -177,7 +177,7 @@ define i1 @test_cross_bb(i32 addrspace(1)* %a, i1 %external_cond) gc "statepoint
 ; CHECK-NEXT:    bl consume
 ; CHECK-NEXT:    b .LBB8_3
 ; CHECK-NEXT:  .LBB8_2:
-; CHECK-NEXT:    mov w19, #-1
+; CHECK-NEXT:    mov w19, #1
 ; CHECK-NEXT:  .LBB8_3: // %common.ret
 ; CHECK-NEXT:    and w0, w19, #0x1
 ; CHECK-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
diff --git a/llvm/test/CodeGen/AArch64/sve-vector-splat.ll b/llvm/test/CodeGen/AArch64/sve-vector-splat.ll
@@ -119,7 +119,8 @@ define <vscale x 8 x i8> @sve_splat_8xi8(i8 %val) {
 define <vscale x 8 x i8> @sve_splat_8xi8_imm() {
 ; CHECK-LABEL: sve_splat_8xi8_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.h, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov w8, #255
+; CHECK-NEXT:    mov z0.h, w8
 ; CHECK-NEXT:    ret
   %ins = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
   %splat = shufflevector <vscale x 8 x i8> %ins, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@@ -150,7 +151,8 @@ define <vscale x 4 x i16> @sve_splat_4xi16(i16 %val) {
 define <vscale x 4 x i16> @sve_splat_4xi16_imm() {
 ; CHECK-LABEL: sve_splat_4xi16_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.s, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    mov z0.s, w8
 ; CHECK-NEXT:    ret
   %ins = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
   %splat = shufflevector <vscale x 4 x i16> %ins, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
@@ -171,7 +173,8 @@ define <vscale x 2 x i32> @sve_splat_2xi32(i32 %val) {
 define <vscale x 2 x i32> @sve_splat_2xi32_imm() {
 ; CHECK-LABEL: sve_splat_2xi32_imm:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov z0.d, #-1 // =0xffffffffffffffff
+; CHECK-NEXT:    mov w8, #-1
+; CHECK-NEXT:    mov z0.d, x8
 ; CHECK-NEXT:    ret
   %ins = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
   %splat = shufflevector <vscale x 2 x i32> %ins, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll b/llvm/test/CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll

Original file line number	Diff line number	Diff line change
`@@ -2647,9 +2647,9 @@ class TargetLoweringBase {`
`2647`	`2647`	`getApproximateEVTForLLT(ToTy, DL, Ctx));`
`2648`	`2648`	`}`
`2649`	`2649`
`2650`		`- /// Return true if sign-extension of value \p V from FromTy to ToTy is`
`2651`		`- /// cheaper than zero-extension, where \p V can be SDValue() if unknown.`
`2652`		`- virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy, SDValue V) const {`
	`2650`	`+ /// Return true if sign-extension from FromTy to ToTy is cheaper than`
	`2651`	`+ /// zero-extension.`
	`2652`	`+ virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {`
`2653`	`2653`	`return false;`
`2654`	`2654`	`}`
`2655`	`2655`
Original file line number	Diff line number	Diff line change
`@@ -1198,8 +1198,7 @@ bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {`
`1198`	`1198`	`return TargetLowering::isZExtFree(Val, VT2);`
`1199`	`1199`	`}`
`1200`	`1200`
`1201`		`-bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT,`
`1202`		`- SDValue V) const {`
	`1201`	`+bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {`
`1203`	`1202`	`return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;`
`1204`	`1203`	`}`
`1205`	`1204`