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format and push/pop macros
1 parent 98aaa34 commit be3b553

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3 files changed

+49
-33
lines changed

3 files changed

+49
-33
lines changed

‎clang/include/clang/Basic/BuiltinsNVPTX.def‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2037,25 +2037,29 @@ TARGET_BUILTIN(__nvvm_atom_acq_rel_cas_shared_ll, "LLiLLiD*LLiLLi", "n", SM_70)
20372037
TARGET_BUILTIN(__nvvm_atom_acq_rel_cta_cas_shared_ll, "LLiLLiD*LLiLLi", "n", SM_70)
20382038
TARGET_BUILTIN(__nvvm_atom_acq_rel_sys_cas_shared_ll, "LLiLLiD*LLiLLi", "n", SM_70)
20392039

2040+
#pragma push_macro("LD_VOLATILE_BUILTIN_TYPES")
20402041
#define LD_VOLATILE_BUILTIN_TYPES(ADDR_SPACE) \
20412042
BUILTIN(__nvvm_volatile_ld##ADDR_SPACE##_i, "iiD*", "n") \
20422043
BUILTIN(__nvvm_volatile_ld##ADDR_SPACE##_l, "LiLiD*", "n") \
20432044
BUILTIN(__nvvm_volatile_ld##ADDR_SPACE##_ll, "LLiLLiD*", "n") \
20442045
BUILTIN(__nvvm_volatile_ld##ADDR_SPACE##_f, "ffD*", "n") \
20452046
BUILTIN(__nvvm_volatile_ld##ADDR_SPACE##_d, "ddD*", "n")
20462047

2048+
#pragma push_macro("LD_BUILTIN_TYPES")
20472049
#define LD_BUILTIN_TYPES(ORDER, SCOPE, ADDR_SPACE) \
20482050
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_i, "iiD*", "n", SM_70) \
20492051
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_l, "LiLiD*", "n", SM_70) \
20502052
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_ll, "LLiLLiD*", "n", SM_70) \
20512053
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_f, "ffD*", "n", SM_70) \
20522054
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_ld##ADDR_SPACE##_d, "ddD*", "n", SM_70)
20532055

2056+
#pragma push_macro("LD_BUILTIN_AS_TYPES")
20542057
#define LD_BUILTIN_AS_TYPES(ORDER, SCOPE) \
20552058
LD_BUILTIN_TYPES(ORDER, SCOPE, _gen) \
20562059
LD_BUILTIN_TYPES(ORDER, SCOPE, _global) \
20572060
LD_BUILTIN_TYPES(ORDER, SCOPE, _shared)
20582061

2062+
#pragma push_macro("LD_BUILTIN_SCOPES_AS_TYPES")
20592063
#define LD_BUILTIN_SCOPES_AS_TYPES(ORDER) \
20602064
LD_BUILTIN_AS_TYPES(ORDER, ) \
20612065
LD_BUILTIN_AS_TYPES(ORDER, _cta) \
@@ -2068,29 +2072,37 @@ LD_VOLATILE_BUILTIN_TYPES(_global)
20682072
LD_VOLATILE_BUILTIN_TYPES(_shared)
20692073

20702074
#undef LD_VOLATILE_BUILTIN_TYPES
2075+
#pragma pop_macro("LD_VOLATILE_BUILTIN_TYPES")
20712076
#undef LD_BUILTIN_TYPES
2077+
#pragma pop_macro("LD_BUILTIN_TYPES")
20722078
#undef LD_BUILTIN_AS_TYPES
2079+
#pragma pop_macro("LD_BUILTIN_AS_TYPES")
20732080
#undef LD_BUILTIN_SCOPES_AS_TYPES
2081+
#pragma pop_macro("LD_BUILTIN_SCOPES_AS_TYPES")
20742082

2083+
#pragma push_macro("ST_VOLATILE_BUILTIN_TYPES")
20752084
#define ST_VOLATILE_BUILTIN_TYPES(ADDR_SPACE) \
20762085
BUILTIN(__nvvm_volatile_st##ADDR_SPACE##_i, "viD*i", "n") \
20772086
BUILTIN(__nvvm_volatile_st##ADDR_SPACE##_l, "vLiD*Li", "n") \
20782087
BUILTIN(__nvvm_volatile_st##ADDR_SPACE##_ll, "vLLiD*LLi", "n") \
20792088
BUILTIN(__nvvm_volatile_st##ADDR_SPACE##_f, "vfD*f", "n") \
20802089
BUILTIN(__nvvm_volatile_st##ADDR_SPACE##_d, "vdD*d", "n")
20812090

2091+
#pragma push_macro("ST_BUILTIN_TYPES")
20822092
#define ST_BUILTIN_TYPES(ORDER, SCOPE, ADDR_SPACE) \
20832093
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_i, "viD*i", "n", SM_70) \
20842094
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_l, "vLiD*Li", "n", SM_70) \
20852095
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_ll, "vLLiD*LLi", "n", SM_70) \
20862096
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_f, "vfD*f", "n", SM_70) \
20872097
TARGET_BUILTIN(__nvvm##ORDER##SCOPE##_st##ADDR_SPACE##_d, "vdD*d", "n", SM_70)
20882098

2099+
#pragma push_macro("ST_BUILTIN_AS_TYPES")
20892100
#define ST_BUILTIN_AS_TYPES(ORDER, SCOPE) \
20902101
ST_BUILTIN_TYPES(ORDER, SCOPE, _gen) \
20912102
ST_BUILTIN_TYPES(ORDER, SCOPE, _global) \
20922103
ST_BUILTIN_TYPES(ORDER, SCOPE, _shared)
20932104

2105+
#pragma push_macro("ST_BUILTIN_SCOPES_AS_TYPES")
20942106
#define ST_BUILTIN_SCOPES_AS_TYPES(ORDER) \
20952107
ST_BUILTIN_AS_TYPES(ORDER, ) \
20962108
ST_BUILTIN_AS_TYPES(ORDER, _cta) \
@@ -2103,9 +2115,13 @@ ST_VOLATILE_BUILTIN_TYPES(_global)
21032115
ST_VOLATILE_BUILTIN_TYPES(_shared)
21042116

21052117
#undef ST_VOLATILE_BUILTIN_TYPES
2118+
#pragma pop_macro("ST_VOLATILE_BUILTIN_TYPES")
21062119
#undef ST_BUILTIN_TYPES
2120+
#pragma pop_macro("ST_BUILTIN_TYPES")
21072121
#undef ST_BUILTIN_AS_TYPES
2122+
#pragma pop_macro("ST_BUILTIN_AS_TYPES")
21082123
#undef ST_BUILTIN_SCOPES_AS_TYPES
2124+
#pragma pop_macro("ST_BUILTIN_SCOPES_AS_TYPES")
21092125

21102126
// Compiler Error Warn
21112127
BUILTIN(__nvvm_compiler_error, "vcC*4", "n")

‎libclc/ptx-nvidiacl/libspirv/atomic/atomic_load.cl‎

100755100644
Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -17,50 +17,50 @@ extern int __clc_nvvm_reflect_arch();
1717
case Subgroup: \
1818
case Workgroup: { \
1919
TYPE_NV res = __nvvm##ORDER##_cta_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \
20-
(ADDR_SPACE TYPE_NV *)pointer); \
20+
(ADDR_SPACE TYPE_NV *)pointer); \
2121
return *(TYPE *)&res; \
2222
} \
2323
case Device: { \
2424
TYPE_NV res = __nvvm##ORDER##_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \
25-
(ADDR_SPACE TYPE_NV *)pointer); \
25+
(ADDR_SPACE TYPE_NV *)pointer); \
2626
return *(TYPE *)&res; \
2727
} \
2828
case CrossDevice: \
2929
default: { \
3030
TYPE_NV res = __nvvm##ORDER##_sys_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \
31-
(ADDR_SPACE TYPE_NV *)pointer); \
31+
(ADDR_SPACE TYPE_NV *)pointer); \
3232
return *(TYPE *)&res; \
3333
} \
3434
}
3535

36-
#define __CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, \
37-
TYPE_MANGLED_NV, ADDR_SPACE, \
38-
ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \
39-
_CLC_DECL TYPE \
36+
#define __CLC_NVVM_ATOMIC_LOAD_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, \
37+
TYPE_MANGLED_NV, ADDR_SPACE, \
38+
ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \
39+
_CLC_DECL TYPE \
4040
_Z18__spirv_AtomicLoadPU3##ADDR_SPACE_MANGLED##K##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
41-
const volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
42-
enum MemorySemanticsMask semantics) { \
43-
/* Semantics mask may include memory order, storage class and other info \
44-
Memory order is stored in the lowest 5 bits */ \
45-
unsigned int order = semantics & 0x1F; \
46-
if (__clc_nvvm_reflect_arch() >= 700) { \
47-
switch (order) { \
48-
case None: \
49-
__CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
50-
ADDR_SPACE, ADDR_SPACE_NV, ) \
51-
case Acquire: \
52-
__CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
53-
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
54-
} \
55-
} else{ \
56-
if(order == None){ \
57-
TYPE_NV res = __nvvm_volatile_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \
58-
(ADDR_SPACE TYPE_NV *)pointer); \
59-
return *(TYPE *)&res; \
60-
} \
61-
} \
62-
__builtin_trap(); \
63-
__builtin_unreachable(); \
41+
const volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
42+
enum MemorySemanticsMask semantics) { \
43+
/* Semantics mask may include memory order, storage class and other info \
44+
Memory order is stored in the lowest 5 bits */ \
45+
unsigned int order = semantics & 0x1F; \
46+
if (__clc_nvvm_reflect_arch() >= 700) { \
47+
switch (order) { \
48+
case None: \
49+
__CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
50+
ADDR_SPACE, ADDR_SPACE_NV, ) \
51+
case Acquire: \
52+
__CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
53+
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
54+
} \
55+
} else { \
56+
if (order == None) { \
57+
TYPE_NV res = __nvvm_volatile_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \
58+
(ADDR_SPACE TYPE_NV *)pointer); \
59+
return *(TYPE *)&res; \
60+
} \
61+
} \
62+
__builtin_trap(); \
63+
__builtin_unreachable(); \
6464
}
6565

6666
#define __CLC_NVVM_ATOMIC_LOAD(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV) \

‎libclc/ptx-nvidiacl/libspirv/atomic/atomic_store.cl‎

100755100644
Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,16 +46,16 @@ Memory order is stored in the lowest 5 bits */
4646
if (__clc_nvvm_reflect_arch() >= 700) { \
4747
switch (order) { \
4848
case None: \
49-
__CLC_NVVM_ATOMIC_STORE_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
49+
__CLC_NVVM_ATOMIC_STORE_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
5050
ADDR_SPACE, ADDR_SPACE_NV, ) \
5151
case Release: \
52-
__CLC_NVVM_ATOMIC_STORE_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
52+
__CLC_NVVM_ATOMIC_STORE_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
5353
ADDR_SPACE, ADDR_SPACE_NV, \
5454
_release) \
5555
} \
5656
} else { \
5757
if (order == None) { \
58-
__nvvm_volatile_st##ADDR_SPACE_NV##TYPE_MANGLED_NV( \
58+
__nvvm_volatile_st##ADDR_SPACE_NV##TYPE_MANGLED_NV( \
5959
(ADDR_SPACE TYPE_NV *)pointer, *(TYPE_NV *)&value); \
6060
return; \
6161
} \

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