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[SYCL][FPGA] Remove deprecated attribute functionality (#4532)
Several FPGA specific attributes in the intelfpga vendor namespace were deprecated in favor of a name in the intel vendor namespace on PR #2568. Specifically, we deprecated the [[intelfpga::attr]] spellings in favor of [[intel::fpga_attr]], [[intelfpga::register]] spelling in favor of [[intel::fpga_register]], and [[intelfpga::memory]] spelling in favor of [[intel::fpga_memory]]. This patch 1. removes the deprecated functionality for the intelfpga:: spellings. The affected attributes are: intelfpga::num_simd_work_items intelfpga::max_work_group_size intelfpga::max_global_work_dim intelfpga::no_global_work_offset intelfpga::ivdep intelfpga::ii intelfpga::max_concurrency intelfpga::loop_coalesce intelfpga::disable_loop_pipelining intelfpga::max_interleaving intelfpga::speculated_iterations intelfpga::doublepump intelfpga::singlepump intelfpga::memory intelfpga::register intelfpga::bankwidth intelfpga::numbanks intelfpga::private_copies intelfpga::merge intelfpga::max_replicates intelfpga::simple_dual_port intelfpga::bank_bits intelfpga::force_pow2_depth intelfpga::scheduler_target_fmax_mhz 2. Updates tests so that tests use at least one removed spelling of each attributes and now shows a warning with unknown attribute spelling. Signed-off-by: Soumi Manna soumi.manna@intel.com
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‎clang/include/clang/Basic/Attr.td‎

Lines changed: 24 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1346,8 +1346,7 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr {
13461346
}
13471347

13481348
def SYCLIntelNumSimdWorkItems : InheritableAttr {
1349-
let Spellings = [CXX11<"intelfpga","num_simd_work_items">,
1350-
CXX11<"intel","num_simd_work_items">];
1349+
let Spellings = [CXX11<"intel", "num_simd_work_items">];
13511350
let Args = [ExprArgument<"Value">];
13521351
let LangOpts = [SYCLIsDevice, SYCLIsHost];
13531352
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1364,8 +1363,7 @@ def SYCLIntelUseStallEnableClusters : InheritableAttr {
13641363
}
13651364

13661365
def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
1367-
let Spellings = [CXX11<"intelfpga","scheduler_target_fmax_mhz">,
1368-
CXX11<"intel","scheduler_target_fmax_mhz">];
1366+
let Spellings = [CXX11<"intel", "scheduler_target_fmax_mhz">];
13691367
let Args = [ExprArgument<"Value">];
13701368
let LangOpts = [SYCLIsDevice, SYCLIsHost];
13711369
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1374,8 +1372,7 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
13741372
}
13751373

13761374
def SYCLIntelMaxWorkGroupSize : InheritableAttr {
1377-
let Spellings = [CXX11<"intelfpga","max_work_group_size">,
1378-
CXX11<"intel","max_work_group_size">];
1375+
let Spellings = [CXX11<"intel", "max_work_group_size">];
13791376
let Args = [ExprArgument<"XDim">,
13801377
ExprArgument<"YDim">,
13811378
ExprArgument<"ZDim">];
@@ -1400,8 +1397,7 @@ def SYCLIntelMaxWorkGroupSize : InheritableAttr {
14001397
}
14011398

14021399
def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
1403-
let Spellings = [CXX11<"intelfpga","max_global_work_dim">,
1404-
CXX11<"intel","max_global_work_dim">];
1400+
let Spellings = [CXX11<"intel", "max_global_work_dim">];
14051401
let Args = [ExprArgument<"Value">];
14061402
let LangOpts = [SYCLIsDevice, SYCLIsHost];
14071403
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1410,8 +1406,7 @@ def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
14101406
}
14111407

14121408
def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
1413-
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
1414-
CXX11<"intel","no_global_work_offset">];
1409+
let Spellings = [CXX11<"intel", "no_global_work_offset">];
14151410
let Args = [ExprArgument<"Value", /*optional*/1>];
14161411
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
14171412
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1933,8 +1928,7 @@ def Mode : Attr {
19331928
}
19341929

19351930
def SYCLIntelFPGAIVDep : StmtAttr {
1936-
let Spellings = [CXX11<"intelfpga","ivdep">,
1937-
CXX11<"intel","ivdep">];
1931+
let Spellings = [CXX11<"intel", "ivdep">];
19381932
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
19391933
ErrorDiag, "'for', 'while', and 'do' statements">;
19401934
let Args = [
@@ -1979,8 +1973,7 @@ def SYCLIntelFPGAIVDep : StmtAttr {
19791973
}
19801974

19811975
def SYCLIntelFPGAInitiationInterval : DeclOrStmtAttr {
1982-
let Spellings = [CXX11<"intelfpga","ii">,
1983-
CXX11<"intel","ii">,
1976+
let Spellings = [CXX11<"intel", "ii">,
19841977
CXX11<"intel", "initiation_interval">];
19851978
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function],
19861979
ErrorDiag,
@@ -1993,8 +1986,7 @@ def SYCLIntelFPGAInitiationInterval : DeclOrStmtAttr {
19931986
}
19941987

19951988
def SYCLIntelFPGAMaxConcurrency : DeclOrStmtAttr {
1996-
let Spellings = [CXX11<"intelfpga","max_concurrency">,
1997-
CXX11<"intel","max_concurrency">];
1989+
let Spellings = [CXX11<"intel", "max_concurrency">];
19981990
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function],
19991991
ErrorDiag,
20001992
"'for', 'while', 'do' statements, and functions">;
@@ -2006,8 +1998,7 @@ def SYCLIntelFPGAMaxConcurrency : DeclOrStmtAttr {
20061998
}
20071999

20082000
def SYCLIntelFPGALoopCoalesce : StmtAttr {
2009-
let Spellings = [CXX11<"intelfpga","loop_coalesce">,
2010-
CXX11<"intel","loop_coalesce">];
2001+
let Spellings = [CXX11<"intel", "loop_coalesce">];
20112002
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
20122003
ErrorDiag, "'for', 'while', and 'do' statements">;
20132004
let Args = [ExprArgument<"NExpr", /*opt*/1>];
@@ -2017,8 +2008,7 @@ def SYCLIntelFPGALoopCoalesce : StmtAttr {
20172008
}
20182009

20192010
def SYCLIntelFPGADisableLoopPipelining : DeclOrStmtAttr {
2020-
let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">,
2021-
CXX11<"intel","disable_loop_pipelining">];
2011+
let Spellings = [CXX11<"intel", "disable_loop_pipelining">];
20222012
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt, Function],
20232013
ErrorDiag,
20242014
"'for', 'while', 'do' statements, and functions">;
@@ -2053,8 +2043,7 @@ def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency,
20532043
SYCLIntelFPGADisableLoopPipelining]>;
20542044

20552045
def SYCLIntelFPGAMaxInterleaving : StmtAttr {
2056-
let Spellings = [CXX11<"intelfpga","max_interleaving">,
2057-
CXX11<"intel","max_interleaving">];
2046+
let Spellings = [CXX11<"intel", "max_interleaving">];
20582047
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
20592048
ErrorDiag, "'for', 'while', and 'do' statements">;
20602049
let Args = [ExprArgument<"NExpr">];
@@ -2066,8 +2055,7 @@ def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining,
20662055
SYCLIntelFPGAMaxInterleaving]>;
20672056

20682057
def SYCLIntelFPGASpeculatedIterations : StmtAttr {
2069-
let Spellings = [CXX11<"intelfpga","speculated_iterations">,
2070-
CXX11<"intel","speculated_iterations">];
2058+
let Spellings = [CXX11<"intel", "speculated_iterations">];
20712059
let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt],
20722060
ErrorDiag, "'for', 'while', and 'do' statements">;
20732061
let Args = [ExprArgument<"NExpr">];
@@ -2120,26 +2108,23 @@ def IntelFPGALocalOrStaticVar : SubsetSubject<Var,
21202108
"local variables, static variables">;
21212109

21222110
def IntelFPGADoublePump : Attr {
2123-
let Spellings = [CXX11<"intelfpga", "doublepump">,
2124-
CXX11<"intel", "doublepump">];
2111+
let Spellings = [CXX11<"intel", "doublepump">];
21252112
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
21262113
Field], ErrorDiag>;
21272114
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
21282115
let Documentation = [IntelFPGADoublePumpAttrDocs];
21292116
}
21302117

21312118
def IntelFPGASinglePump : Attr {
2132-
let Spellings = [CXX11<"intelfpga", "singlepump">,
2133-
CXX11<"intel", "singlepump">];
2119+
let Spellings = [CXX11<"intel", "singlepump">];
21342120
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
21352121
Field], ErrorDiag>;
21362122
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
21372123
let Documentation = [IntelFPGASinglePumpAttrDocs];
21382124
}
21392125

21402126
def IntelFPGAMemory : Attr {
2141-
let Spellings = [CXX11<"intelfpga", "memory">,
2142-
CXX11<"intel", "fpga_memory">];
2127+
let Spellings = [CXX11<"intel", "fpga_memory">];
21432128
let Args = [EnumArgument<"Kind", "MemoryKind",
21442129
["MLAB", "BLOCK_RAM", ""],
21452130
["MLAB", "BlockRAM", "Default"], 1>];
@@ -2159,8 +2144,7 @@ def IntelFPGAMemory : Attr {
21592144
}
21602145

21612146
def IntelFPGARegister : Attr {
2162-
let Spellings = [CXX11<"intelfpga", "register">,
2163-
CXX11<"intel", "fpga_register">];
2147+
let Spellings = [CXX11<"intel", "fpga_register">];
21642148
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
21652149
Field], ErrorDiag>;
21662150
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
@@ -2171,8 +2155,7 @@ def : MutualExclusions<[IntelFPGADoublePump, IntelFPGASinglePump,
21712155

21722156
// One integral argument.
21732157
def IntelFPGABankWidth : InheritableAttr {
2174-
let Spellings = [CXX11<"intelfpga","bankwidth">,
2175-
CXX11<"intel","bankwidth">];
2158+
let Spellings = [CXX11<"intel", "bankwidth">];
21762159
let Args = [ExprArgument<"Value">];
21772160
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
21782161
Field], ErrorDiag>;
@@ -2182,8 +2165,7 @@ def IntelFPGABankWidth : InheritableAttr {
21822165
def : MutualExclusions<[IntelFPGARegister, IntelFPGABankWidth]>;
21832166

21842167
def IntelFPGANumBanks : InheritableAttr {
2185-
let Spellings = [CXX11<"intelfpga","numbanks">,
2186-
CXX11<"intel","numbanks">];
2168+
let Spellings = [CXX11<"intel", "numbanks">];
21872169
let Args = [ExprArgument<"Value">];
21882170
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
21892171
Field], ErrorDiag>;
@@ -2192,8 +2174,7 @@ def IntelFPGANumBanks : InheritableAttr {
21922174
}
21932175

21942176
def IntelFPGAPrivateCopies : InheritableAttr {
2195-
let Spellings = [CXX11<"intelfpga","private_copies">,
2196-
CXX11<"intel","private_copies">];
2177+
let Spellings = [CXX11<"intel", "private_copies">];
21972178
let Args = [ExprArgument<"Value">];
21982179
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
21992180
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
@@ -2203,8 +2184,7 @@ def : MutualExclusions<[IntelFPGARegister, IntelFPGAPrivateCopies]>;
22032184

22042185
// Two string arguments.
22052186
def IntelFPGAMerge : Attr {
2206-
let Spellings = [CXX11<"intelfpga","merge">,
2207-
CXX11<"intel","merge">];
2187+
let Spellings = [CXX11<"intel", "merge">];
22082188
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
22092189
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
22102190
Field], ErrorDiag>;
@@ -2214,8 +2194,7 @@ def IntelFPGAMerge : Attr {
22142194
def : MutualExclusions<[IntelFPGARegister, IntelFPGAMerge]>;
22152195

22162196
def IntelFPGAMaxReplicates : InheritableAttr {
2217-
let Spellings = [CXX11<"intelfpga","max_replicates">,
2218-
CXX11<"intel","max_replicates">];
2197+
let Spellings = [CXX11<"intel", "max_replicates">];
22192198
let Args = [ExprArgument<"Value">];
22202199
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
22212200
Field], ErrorDiag>;
@@ -2225,8 +2204,7 @@ def IntelFPGAMaxReplicates : InheritableAttr {
22252204
def : MutualExclusions<[IntelFPGARegister, IntelFPGAMaxReplicates]>;
22262205

22272206
def IntelFPGASimpleDualPort : Attr {
2228-
let Spellings = [CXX11<"intelfpga","simple_dual_port">,
2229-
CXX11<"intel","simple_dual_port">];
2207+
let Spellings = [CXX11<"intel", "simple_dual_port">];
22302208
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
22312209
Field], ErrorDiag>;
22322210
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
@@ -2251,8 +2229,7 @@ def SYCLIntelPipeIO : Attr {
22512229

22522230
// Variadic integral arguments.
22532231
def IntelFPGABankBits : Attr {
2254-
let Spellings = [CXX11<"intelfpga", "bank_bits">,
2255-
CXX11<"intel", "bank_bits">];
2232+
let Spellings = [CXX11<"intel", "bank_bits">];
22562233
let Args = [VariadicExprArgument<"Args">];
22572234
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
22582235
Field], ErrorDiag>;
@@ -2263,8 +2240,7 @@ def : MutualExclusions<[IntelFPGARegister, IntelFPGABankBits]>;
22632240
def : MutualExclusions<[IntelFPGARegister, IntelFPGANumBanks]>;
22642241

22652242
def IntelFPGAForcePow2Depth : InheritableAttr {
2266-
let Spellings = [CXX11<"intelfpga","force_pow2_depth">,
2267-
CXX11<"intel","force_pow2_depth">];
2243+
let Spellings = [CXX11<"intel", "force_pow2_depth">];
22682244
let Args = [ExprArgument<"Value">];
22692245
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar,
22702246
Field], ErrorDiag>;

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