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Create a way to make a chain of Muxs in a less verbose way #13

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mkorbel1 opened this issue Sep 23, 2021 · 1 comment · Fixed by #188
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Create a way to make a chain of Muxs in a less verbose way #13

mkorbel1 opened this issue Sep 23, 2021 · 1 comment · Fixed by #188
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enhancement New feature or request good first issue Good for newcomers

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mkorbel1 commented Sep 23, 2021 •
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The implementation for Mux maps to a SystemVerilog ternary operator (? :). Chaining together a bunch of ternary operators in SystemVerilog is a common pattern, but requires nested Muxs and lots of parentheses in ROHD. A module that supports chained mux behavior would be nice.
@mkorbel1 mkorbel1 added enhancement New feature or request good first issue Good for newcomers labels Sep 23, 2021
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mkorbel1 commented Apr 7, 2022

It would also be nice if there's a way to construct a Mux without needing to access the output explicitly. Maybe as simple as a mux function that gets the output.

@mkorbel1 mkorbel1 self-assigned this Oct 21, 2022
@mkorbel1 mkorbel1 mentioned this issue Oct 21, 2022
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Clean up names for ports mkorbel1/rohd
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