You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
The implementation for Mux maps to a SystemVerilog ternary operator (? :). Chaining together a bunch of ternary operators in SystemVerilog is a common pattern, but requires nested Muxs and lots of parentheses in ROHD. A module that supports chained mux behavior would be nice.
The text was updated successfully, but these errors were encountered:
It would also be nice if there's a way to construct a Mux without needing to access the output explicitly. Maybe as simple as a mux function that gets the output.
The implementation for
Mux
maps to a SystemVerilog ternary operator (? :
). Chaining together a bunch of ternary operators in SystemVerilog is a common pattern, but requires nestedMux
s and lots of parentheses in ROHD. A module that supports chained mux behavior would be nice.The text was updated successfully, but these errors were encountered: