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[Exegesis][RISCV] Add RISCV support for llvm-exegesis (llvm#120467)
This patch also makes following amendments to core exegesis: * Added distinction between regular registers aliasing check and registers used as memory address in instruction. * Added scratch memory space pointer register. * General exegesis options were amended: * mattr - new option to pass a list of enabled target features Llvm-exegesis RISCV port is a result of team effort. Below everyone involved listed. Co-authored-by: Konstantin Vladimirov <konstantin.vladimirov@syntacore.com> Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com> Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com> Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com> Co-authored-by: Anastasiya Chernikova <anastasiya.chernikova@syntacore.com> Original pr: llvm#89047 --------- Co-authored-by: Kazu Hirata <kazu@google.com>
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‎llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s‎

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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOAND_D -mattr="+a" | FileCheck --check-prefix=AMOAND_D %s
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AMOAND_D: ---
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AMOAND_D-NEXT: mode: latency
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AMOAND_D-NEXT: key:
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AMOAND_D-NEXT: instructions:
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AMOAND_D-NEXT: - 'AMOAND_D [[RE01:X[0-9]+]] X10 [[RE01:X[0-9]+]]'
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AMOAND_D-NEXT: config: ''
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AMOAND_D-NEXT: register_initial_values:
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AMOAND_D-NEXT: - '[[RE01:X[0-9]+]]=0x0'
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AMOAND_D-DAG: ...
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOADD_W -mattr="+a" | FileCheck --check-prefix=AMOADD_W %s
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AMOADD_W: ---
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AMOADD_W-NEXT: mode: latency
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AMOADD_W-NEXT: key:
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AMOADD_W-NEXT: instructions:
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AMOADD_W-NEXT: - 'AMOADD_W [[RE02:X[0-9]+]] X10 [[RE02:X[0-9]+]]'
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AMOADD_W-NEXT: config: ''
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AMOADD_W-NEXT: register_initial_values:
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AMOADD_W-NEXT: - '[[RE02:X[0-9]+]]=0x0'
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AMOADD_W-DAG: ...
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOMAXU_D -mattr="+a" | FileCheck --check-prefix=AMOMAXU_D %s
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AMOMAXU_D: ---
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AMOMAXU_D-NEXT: mode: latency
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AMOMAXU_D-NEXT: key:
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AMOMAXU_D-NEXT: instructions:
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AMOMAXU_D-NEXT: - 'AMOMAXU_D [[RE03:X[0-9]+]] X10 [[RE03:X[0-9]+]]'
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AMOMAXU_D-NEXT: config: ''
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AMOMAXU_D-NEXT: register_initial_values:
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AMOMAXU_D-NEXT: - '[[RE03:X[0-9]+]]=0x0'
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AMOMAXU_D-DAG: ...
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOMIN_W -mattr="+a" | FileCheck --check-prefix=AMOMIN_W %s
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AMOMIN_W: ---
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AMOMIN_W-NEXT: mode: latency
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AMOMIN_W-NEXT: key:
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AMOMIN_W-NEXT: instructions:
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AMOMIN_W-NEXT: - 'AMOMIN_W [[RE04:X[0-9]+]] X10 [[RE04:X[0-9]+]]'
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AMOMIN_W-NEXT: config: ''
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AMOMIN_W-NEXT: register_initial_values:
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AMOMIN_W-NEXT: - '[[RE04:X[0-9]+]]=0x0'
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AMOMIN_W-DAG: ...
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=AMOXOR_D -mattr="+a" | FileCheck --check-prefix=AMOXOR_D %s
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AMOXOR_D: ---
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AMOXOR_D-NEXT: mode: latency
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AMOXOR_D-NEXT: key:
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AMOXOR_D-NEXT: instructions:
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AMOXOR_D-NEXT: - 'AMOXOR_D [[RE05:X[0-9]+]] X10 [[RE05:X[0-9]+]]'
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AMOXOR_D-NEXT: config: ''
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AMOXOR_D-NEXT: register_initial_values:
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AMOXOR_D-NEXT: - '[[RE05:X[0-9]+]]=0x0'
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AMOXOR_D-DAG: ...

‎llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s‎

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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_ADDI -mattr=+c | FileCheck --check-prefix=C_ADDI %s
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C_ADDI: ---
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C_ADDI-NEXT: mode: latency
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C_ADDI-NEXT: key:
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C_ADDI-NEXT: instructions:
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C_ADDI-NEXT: - 'C_ADDI [[REG01:X[0-9]+]] [[RE02:X[0-9]+]] [[IMM0:i_0x[0-9]+]]'
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_ADDIW -mattr=+c | FileCheck --check-prefix=C_ADDIW %s
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C_ADDIW: ---
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C_ADDIW-NEXT: mode: latency
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C_ADDIW-NEXT: key:
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C_ADDIW-NEXT: instructions:
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C_ADDIW-NEXT: - 'C_ADDIW [[REG11:X[0-9]+]] [[RE12:X[0-9]+]] [[IMM1:i_0x[0-9]+]]'
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_ANDI -mattr=+c | FileCheck --check-prefix=C_ANDI %s
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C_ANDI: ---
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C_ANDI-NEXT: mode: latency
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C_ANDI-NEXT: key:
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C_ANDI-NEXT: instructions:
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C_ANDI-NEXT: - 'C_ANDI [[REG31:X[0-9]+]] [[REG32:X[0-9]+]] [[IMM3:i_0x[0-9]+]]'
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_SLLI -mattr=+c | FileCheck --check-prefix=C_SLLI %s
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C_SLLI: ---
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C_SLLI-NEXT: mode: latency
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C_SLLI-NEXT: key:
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C_SLLI-NEXT: instructions:
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C_SLLI-NEXT: - 'C_SLLI [[REG81:X[0-9]+]] [[REG82:X[0-9]+]] [[IMM8:i_0x[0-9]+]]'
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_SRAI -mattr=+c | FileCheck --check-prefix=C_SRAI %s
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C_SRAI: ---
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C_SRAI-NEXT: mode: latency
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C_SRAI-NEXT: key:
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C_SRAI-NEXT: instructions:
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C_SRAI-NEXT: - 'C_SRAI [[REG91:X[0-9]+]] [[REG92:X[0-9]+]] [[IMM9:i_0x[0-9]+]]'
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# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux-gnu --mcpu=generic --benchmark-phase=assemble-measured-code -opcode-name=C_SRLI -mattr=+c | FileCheck --check-prefix=C_SRLI %s
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C_SRLI: ---
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C_SRLI-NEXT: mode: latency
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C_SRLI-NEXT: key:
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C_SRLI-NEXT: instructions:
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C_SRLI-NEXT: - 'C_SRLI [[REG101:X[0-9]+]] [[REG102:X[0-9]+]] [[IMM10:i_0x[0-9]+]]'
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C_SRLI-DAG: ...

‎llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s‎

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# RUN: llvm-exegesis -mtriple=riscv64-unknown-linux-gnu --mcpu=generic -mode=latency --benchmark-phase=assemble-measured-code -mattr=+d -opcode-name=FADD_D | FileCheck %s
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CHECK: ---
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CHECK-NEXT: mode: latency
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CHECK-NEXT: key:
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CHECK-NEXT: instructions:
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CHECK-NEXT: - 'FADD_D [[REG1:F[0-9]+_D]] [[REG2:F[0-9]+_D]] [[REG3:F[0-9]+_D]] i_0x7'
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CHECK-NEXT: config: ''
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CHECK-NEXT: register_initial_values:
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CHECK-DAG: - '[[REG1]]=0x0'
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CHECK-DAG: ...

‎llvm/test/tools/llvm-exegesis/RISCV/lit.local.cfg‎

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if not ("RISCV" in config.root.targets):
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# We need support for RISCV.
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config.unsupported = True

‎llvm/tools/llvm-exegesis/lib/CMakeLists.txt‎

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if (LLVM_TARGETS_TO_BUILD MATCHES "Mips")
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list(APPEND LLVM_EXEGESIS_TARGETS "Mips")
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endif()
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if(LLVM_TARGETS_TO_BUILD MATCHES "RISCV")
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list(APPEND LLVM_EXEGESIS_TARGETS "RISCV")
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endif()
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set(LLVM_EXEGESIS_TARGETS ${LLVM_EXEGESIS_TARGETS} PARENT_SCOPE)
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‎llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp‎

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@@ -95,11 +95,12 @@ Instruction::Instruction(const MCInstrDesc *Description, StringRef Name,
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const BitVector *ImplDefRegs,
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const BitVector *ImplUseRegs,
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const BitVector *AllDefRegs,
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const BitVector *AllUseRegs)
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const BitVector *AllUseRegs,
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const BitVector *NonMemoryRegs)
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: Description(*Description), Name(Name), Operands(std::move(Operands)),
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Variables(std::move(Variables)), ImplDefRegs(*ImplDefRegs),
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ImplUseRegs(*ImplUseRegs), AllDefRegs(*AllDefRegs),
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AllUseRegs(*AllUseRegs) {}
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AllUseRegs(*AllUseRegs), NonMemoryRegs(*NonMemoryRegs) {}
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std::unique_ptr<Instruction>
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Instruction::create(const MCInstrInfo &InstrInfo,
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BitVector ImplUseRegs = RATC.emptyRegisters();
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BitVector AllDefRegs = RATC.emptyRegisters();
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BitVector AllUseRegs = RATC.emptyRegisters();
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BitVector NonMemoryRegs = RATC.emptyRegisters();
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for (const auto &Op : Operands) {
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if (Op.isReg()) {
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const auto &AliasingBits = Op.getRegisterAliasing().aliasedBits();
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ImplDefRegs |= AliasingBits;
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if (Op.isUse() && Op.isImplicit())
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ImplUseRegs |= AliasingBits;
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if (Op.isUse() && !Op.isMemory())
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NonMemoryRegs |= AliasingBits;
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}
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}
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// Can't use make_unique because constructor is private.
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std::move(Variables), BVC.getUnique(std::move(ImplDefRegs)),
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BVC.getUnique(std::move(ImplUseRegs)),
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BVC.getUnique(std::move(AllDefRegs)),
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BVC.getUnique(std::move(AllUseRegs))));
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BVC.getUnique(std::move(AllUseRegs)),
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BVC.getUnique(std::move(NonMemoryRegs))));
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}
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const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
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ForbiddenRegisters);
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}
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bool Instruction::hasAliasingNotMemoryRegisters(
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const BitVector &ForbiddenRegisters) const {
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return anyCommonExcludingForbidden(AllDefRegs, NonMemoryRegs,
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ForbiddenRegisters);
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}
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bool Instruction::hasOneUseOrOneDef() const {
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return AllDefRegs.count() || AllUseRegs.count();
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}

‎llvm/tools/llvm-exegesis/lib/MCInstrDescView.h‎

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// aliasing Use and Def registers.
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bool hasAliasingRegisters(const BitVector &ForbiddenRegisters) const;
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// Whether this instruction is self aliasing through some registers.
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// Repeating this instruction may execute sequentially by picking aliasing
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// Def and Not Memory Use registers. It may also execute in parallel by
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// picking non aliasing Def and Not Memory Use registers.
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bool hasAliasingNotMemoryRegisters(const BitVector &ForbiddenRegisters) const;
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// Whether this instruction's registers alias with OtherInstr's registers.
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bool hasAliasingRegistersThrough(const Instruction &OtherInstr,
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const BitVector &ForbiddenRegisters) const;
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const BitVector &ImplUseRegs; // The set of aliased implicit use registers.
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const BitVector &AllDefRegs; // The set of all aliased def registers.
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const BitVector &AllUseRegs; // The set of all aliased use registers.
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// The set of all aliased not memory use registers.
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const BitVector &NonMemoryRegs;
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private:
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Instruction(const MCInstrDesc *Description, StringRef Name,
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SmallVector<Operand, 8> Operands,
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SmallVector<Variable, 4> Variables, const BitVector *ImplDefRegs,
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const BitVector *ImplUseRegs, const BitVector *AllDefRegs,
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const BitVector *AllUseRegs);
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const BitVector *AllUseRegs, const BitVector *NonMemoryRegs);
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};
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// Instructions are expensive to instantiate. This class provides a cache of

‎llvm/tools/llvm-exegesis/lib/RISCV/CMakeLists.txt‎

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include_directories(
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${LLVM_MAIN_SRC_DIR}/lib/Target/RISCV
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${LLVM_BINARY_DIR}/lib/Target/RISCV
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)
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set(LLVM_LINK_COMPONENTS
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CodeGen
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RISCV
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Exegesis
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Core
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Support
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)
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add_llvm_library(LLVMExegesisRISCV
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DISABLE_LLVM_LINK_LLVM_DYLIB
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STATIC
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Target.cpp
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DEPENDS
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intrinsics_gen
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RISCVCommonTableGen
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)

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