lpc1752.svd

<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.1"
    xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
    xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
    <name>lpc1752</name>
    <version>0.2</version>
    <description>LPC176x/LPC175x M3</description>
    <cpu>
        <name>CM3</name>
        <revision>r0p0</revision>
        <endian>little</endian>
        <mpuPresent>1</mpuPresent>
        <fpuPresent>0</fpuPresent>
        <nvicPrioBits>5</nvicPrioBits>
        <vendorSystickConfig>0</vendorSystickConfig>
    </cpu>
    <addressUnitBits>8</addressUnitBits>
    <width>32</width>
    <size>32</size>
    <!--
		Software that is described herein is for illustrative purposes only
		which provides customers with programming information regarding the
		products. This software is supplied "AS IS" without any warranties.
		NXP Semiconductors assumes no responsibility or liability for the
		use of the software, conveys no license or title under any patent,
		copyright, or mask work right to the product. NXP Semiconductors
		reserves the right to make changes in the software without
		notification. NXP Semiconductors also make no representation or
		warranty that such application will be suitable for the specified
		use without further testing or modification.	
		
	-->
    <peripherals>
        <peripheral>
            <name>WDT</name>
            <description>Watchdog Timer (WDT) </description>
            <groupName>WDT</groupName>
            <baseAddress>0x40000000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>WDT</name>
                <value>0</value>
            </interrupt>
            <registers>
                <register>
                    <name>MOD</name>
                    <description>Watchdog mode register. This register determines the basic mode and
                        status of the Watchdog Timer.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>WDEN</name>
                            <description>Watchdog enable bit. This bit is Set Only.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>STOP</name>
                                    <description>The watchdog timer is stopped.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RUN</name>
                                    <description>The watchdog timer is running.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>WDRESET</name>
                            <description>Watchdog reset enable bit. This bit is Set Only. See Table
                                652.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NORESET</name>
                                    <description>A watchdog timeout will not cause a chip reset.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>A watchdog timeout will cause a chip reset.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>WDTOF</name>
                            <description>Watchdog time-out flag. Set when the watchdog timer times
                                out, cleared by software.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>WDINT</name>
                            <description>Watchdog interrupt flag. Cleared by software.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TC</name>
                    <description>Watchdog timer constant register. The value in this register
                        determines the time-out value.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0xFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>Count</name>
                            <description>Watchdog time-out interval.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FEED</name>
                    <description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to
                        this register reloads the Watchdog timer with the value contained in WDTC.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>Feed</name>
                            <description>Feed value should be 0xAA followed by 0x55.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TV</name>
                    <description>Watchdog timer value register. This register reads out the current
                        value of the Watchdog timer.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0xFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>Count</name>
                            <description>Counter timer value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CLKSEL</name>
                    <description>Watchdog clock select register.</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CLKSEL</name>
                            <description>Selects source of WDT clock</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>IRC</name>
                                    <description>IRC</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>PCLK</name>
                                    <description>Peripheral clock</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RTCOSC</name>
                                    <description>RTC oscillator</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESERVED</name>
                                    <description>Reserved.</description>
                                    <isDefault>true</isDefault>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[30:1]</bitRange>
                        </field>
                        <field>
                            <name>LOCK</name>
                            <description>If this bit is set to one writing to this register does not
                                affect bit 0. The clock source can only be changed by first clearing
                                this bit, then writing the new value of bit 0.</description>
                            <bitRange>[31:31]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>UNLOCKED</name>
                                    <description>This bit is set to 0 on any reset. It cannot be
                                        cleared by software.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>LOCKED</name>
                                    <description>Software can set this bit to 1 at any time. Once
                                        WDLOCK is set, the bits of this register
                                        cannot be modified.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>TIMER0</name>
            <description>Timer0/1/2/3 </description>
            <groupName>TIMER0</groupName>
            <baseAddress>0x40004000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>TIMER0</name>
                <value>1</value>
            </interrupt>
            <registers>
                <register>
                    <name>IR</name>
                    <description>Interrupt Register. The IR can be written to clear interrupts. The
                        IR can be read to identify which of eight possible interrupt sources are
                        pending.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MR0INT</name>
                            <description>Interrupt flag for match channel 0.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>MR1INT</name>
                            <description>Interrupt flag for match channel 1.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>MR2INT</name>
                            <description>Interrupt flag for match channel 2.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>MR3INT</name>
                            <description>Interrupt flag for match channel 3.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CR0INT</name>
                            <description>Interrupt flag for capture channel 0 event.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>CR1INT</name>
                            <description>Interrupt flag for capture channel 1 event.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TCR</name>
                    <description>Timer Control Register. The TCR is used to control the Timer
                        Counter functions. The Timer Counter can be disabled or reset through the
                        TCR.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CEN</name>
                            <description>When one, the Timer Counter and Prescale Counter are
                                enabled for counting. When zero, the counters are disabled.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>CRST</name>
                            <description>When one, the Timer Counter and the Prescale Counter are
                                synchronously reset on the next positive edge of PCLK. The counters
                                remain reset until TCR[1] is returned to zero.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TC</name>
                    <description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of
                        PCLK. The TC is controlled through the TCR.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TC</name>
                            <description>Timer counter value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PR</name>
                    <description>Prescale Register. When the Prescale Counter (PC) is equal to this
                        value, the next clock increments the TC and clears the PC.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PM</name>
                            <description>Prescale counter maximum value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PC</name>
                    <description>Prescale Counter. The 32 bit PC is a counter which is incremented
                        to the value stored in PR. When the value in PR is reached, the TC is
                        incremented and the PC is cleared. The PC is observable and controllable
                        through the bus interface.</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PC</name>
                            <description>Prescale counter value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MCR</name>
                    <description>Match Control Register. The MCR is used to control if an interrupt
                        is generated and if the TC is reset when a Match occurs.</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MR0I</name>
                            <description>Interrupt on MR0</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_IS_GENERAT</name>
                                    <description>Interrupt is generated when MR0 matches the value
                                        in the TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_IS_DISABLE</name>
                                    <description>Interrupt is disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR0R</name>
                            <description>Reset on MR0</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TC_WILL_BE_RESET_IF_</name>
                                    <description>TC will be reset if MR0 matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FEATURE_DISABLED_</name>
                                    <description>Feature disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR0S</name>
                            <description>Stop on MR0</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TC_AND_PC_WILL_BE_ST</name>
                                    <description>TC and PC will be stopped and TCR[0] will be set to
                                        0 if MR0 matches the TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FEATURE_DISABLED_</name>
                                    <description>Feature disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR1I</name>
                            <description>Interrupt on MR1</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_IS_GENERAT</name>
                                    <description>Interrupt is generated when MR1 matches the value
                                        in the TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_IS_DISABLE</name>
                                    <description>Interrupt is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR1R</name>
                            <description>Reset on MR1</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TC_WILL_BE_RESET_IF_</name>
                                    <description>TC will be reset if MR1 matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FEATURE_DISABLED_</name>
                                    <description>Feature disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR1S</name>
                            <description>Stop on MR1</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TC_AND_PC_WILL_BE_ST</name>
                                    <description>TC and PC will be stopped and TCR[0] will be set to
                                        0 if MR1 matches the TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FEATURE_DISABLED_</name>
                                    <description>Feature disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR2I</name>
                            <description>Interrupt on MR2</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_IS_GENERAT</name>
                                    <description>Interrupt is generated when MR2 matches the value
                                        in the TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_IS_DISABLE</name>
                                    <description>Interrupt is disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR2R</name>
                            <description>Reset on MR2</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TC_WILL_BE_RESET_IF_</name>
                                    <description>TC will be reset if MR2 matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FEATURE_DISABLED_</name>
                                    <description>Feature disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR2S</name>
                            <description>Stop on MR2.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TC_AND_PC_WILL_BE_ST</name>
                                    <description>TC and PC will be stopped and TCR[0] will be set to
                                        0 if MR2 matches the TC</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FEATURE_DISABLED_</name>
                                    <description>Feature disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR3I</name>
                            <description>Interrupt on MR3</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_IS_GENERAT</name>
                                    <description>Interrupt is generated when MR3 matches the value
                                        in the TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_IS_DI</name>
                                    <description>This interrupt is disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR3R</name>
                            <description>Reset on MR3</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TC_WILL_BE_RESET_IF_</name>
                                    <description>TC will be reset if MR3 matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FEATURE_DISABLED_</name>
                                    <description>Feature disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MR3S</name>
                            <description>Stop on MR3</description>
                            <bitRange>[11:11]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TC_AND_PC_WILL_BE_ST</name>
                                    <description>TC and PC will be stopped and TCR[0] will be set to
                                        0 if MR3 matches the TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FEATURE_DISABLED_</name>
                                    <description>Feature disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>4</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-3</dimIndex>
                    <name>MR[%s]</name>
                    <displayName>MR[%s]</displayName>
                    <description>Match Register 0. MR0 can be enabled through the MCR to reset the
                        TC, stop both the TC and PC, and/or generate an interrupt every time MR0
                        matches the TC.</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MATCH</name>
                            <description>Timer counter match value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CCR</name>
                    <description>Capture Control Register. The CCR controls which edges of the
                        capture inputs are used to load the Capture Registers and whether or not an
                        interrupt is generated when a capture takes place.</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CAP0RE</name>
                            <description>Capture on CAPn.0 rising edge</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>A sequence of 0 then 1 on CAPn.0 will cause CR0 to
                                        be loaded with the contents of TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP0FE</name>
                            <description>Capture on CAPn.0 falling edge</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>A sequence of 1 then 0 on CAPn.0 will cause CR0 to
                                        be loaded with the contents of TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP0I</name>
                            <description>Interrupt on CAPn.0 event</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>A CR0 load due to a CAPn.0 event will generate an
                                        interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP1RE</name>
                            <description>Capture on CAPn.1 rising edge</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>A sequence of 0 then 1 on CAPn.1 will cause CR1 to
                                        be loaded with the contents of TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP1FE</name>
                            <description>Capture on CAPn.1 falling edge</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>A sequence of 1 then 0 on CAPn.1 will cause CR1 to
                                        be loaded with the contents of TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP1I</name>
                            <description>Interrupt on CAPn.1 event</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>A CR1 load due to a CAPn.1 event will generate an
                                        interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>2</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-1</dimIndex>
                    <name>CR[%s]</name>
                    <displayName>CR[%s]</displayName>
                    <description>Capture Register 0. CR0 is loaded with the value of TC when there
                        is an event on the CAPn.0 input.</description>
                    <addressOffset>0x02C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CAP</name>
                            <description>Timer counter capture value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EMR</name>
                    <description>External Match Register. The EMR controls the external match pins.</description>
                    <addressOffset>0x03C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EM0</name>
                            <description>External Match 0. When a match occurs between the TC and
                                MR0, this bit can either toggle, go low, go high, or do nothing,
                                depending on bits 5:4 of this register. This bit can be driven onto
                                a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EM1</name>
                            <description>External Match 1. When a match occurs between the TC and
                                MR1, this bit can either toggle, go low, go high, or do nothing,
                                depending on bits 7:6 of this register. This bit can be driven onto
                                a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EM2</name>
                            <description>External Match 2. When a match occurs between the TC and
                                MR2, this bit can either toggle, go low, go high, or do nothing,
                                depending on bits 9:8 of this register. This bit can be driven onto
                                a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EM3</name>
                            <description>External Match 3. When a match occurs between the TC and
                                MR3, this bit can either toggle, go low, go high, or do nothing,
                                depending on bits 11:10 of this register. This bit can be driven
                                onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EMC0</name>
                            <description>External Match Control 0. Determines the functionality of
                                External Match 0.</description>
                            <bitRange>[5:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DO_NOTHING_</name>
                                    <description>Do Nothing.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CLEAR_THE_CORRESPOND</name>
                                    <description>Clear the corresponding External Match bit/output
                                        to 0 (MATn.m pin is LOW if pinned out).</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET_THE_CORRESPONDIN</name>
                                    <description>Set the corresponding External Match bit/output to
                                        1 (MATn.m pin is HIGH if pinned out).</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TOGGLE_THE_CORRESPON</name>
                                    <description>Toggle the corresponding External Match bit/output.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EMC1</name>
                            <description>External Match Control 1. Determines the functionality of
                                External Match 1.</description>
                            <bitRange>[7:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DO_NOTHING_</name>
                                    <description>Do Nothing.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CLEAR_THE_CORRESPOND</name>
                                    <description>Clear the corresponding External Match bit/output
                                        to 0 (MATn.m pin is LOW if pinned out).</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET_THE_CORRESPONDIN</name>
                                    <description>Set the corresponding External Match bit/output to
                                        1 (MATn.m pin is HIGH if pinned out).</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TOGGLE_THE_CORRESPON</name>
                                    <description>Toggle the corresponding External Match bit/output.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EMC2</name>
                            <description>External Match Control 2. Determines the functionality of
                                External Match 2.</description>
                            <bitRange>[9:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DO_NOTHING_</name>
                                    <description>Do Nothing.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CLEAR_THE_CORRESPOND</name>
                                    <description>Clear the corresponding External Match bit/output
                                        to 0 (MATn.m pin is LOW if pinned out).</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET_THE_CORRESPONDIN</name>
                                    <description>Set the corresponding External Match bit/output to
                                        1 (MATn.m pin is HIGH if pinned out).</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TOGGLE_THE_CORRESPON</name>
                                    <description>Toggle the corresponding External Match bit/output.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EMC3</name>
                            <description>External Match Control 3. Determines the functionality of
                                External Match 3.</description>
                            <bitRange>[11:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DO_NOTHING_</name>
                                    <description>Do Nothing.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CLEAR_THE_CORRESPOND</name>
                                    <description>Clear the corresponding External Match bit/output
                                        to 0 (MATn.m pin is LOW if pinned out).</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET_THE_CORRESPONDIN</name>
                                    <description>Set the corresponding External Match bit/output to
                                        1 (MATn.m pin is HIGH if pinned out).</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TOGGLE_THE_CORRESPON</name>
                                    <description>Toggle the corresponding External Match bit/output.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CTCR</name>
                    <description>Count Control Register. The CTCR selects between Timer and Counter
                        mode, and in Counter mode selects the signal and edge(s) for counting.</description>
                    <addressOffset>0x070</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CTMODE</name>
                            <description>Counter/Timer Mode This field selects which rising PCLK
                                edges can increment Timer's Prescale Counter (PC), or clear PC and
                                increment Timer Counter (TC). Timer Mode: the TC is incremented when
                                the Prescale Counter matches the Prescale Register.</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TIMER_MODE_EVERY_RI</name>
                                    <description>Timer Mode: every rising PCLK edge</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>Counter Mode: TC is incremented on rising edges on
                                        the CAP input selected by bits 3:2.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING</name>
                                    <description>Counter Mode: TC is incremented on falling edges on
                                        the CAP input selected by bits 3:2.</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DUALEDGE</name>
                                    <description>Counter Mode: TC is incremented on both edges on
                                        the CAP input selected by bits 3:2.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CINSEL</name>
                            <description>Count Input Select When bits 1:0 in this register are not
                                00, these bits select which CAP pin is sampled for clocking. Note:
                                If Counter mode is selected for a particular CAPn input in the
                                TnCTCR, the 3 bits for that input in the Capture Control Register
                                (TnCCR) must be programmed as 000. However, capture and/or interrupt
                                can be selected for the other 3 CAPn inputs in the same timer.</description>
                            <bitRange>[3:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CAPN_0_FOR_TIMERN</name>
                                    <description>CAPn.0 for TIMERn</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CAPN_1_FOR_TIMERN</name>
                                    <description>CAPn.1 for TIMERn</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral derivedFrom="TIMER0">
            <name>TIMER1</name>
            <baseAddress>0x40008000</baseAddress>
            <interrupt>
                <name>TIMER1</name>
                <value>2</value>
            </interrupt>
        </peripheral>
        <peripheral>
            <name>UART0</name>
            <description>UART0/2/3 </description>
            <groupName>UART0</groupName>
            <baseAddress>0x4000C000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>UART0</name>
                <value>5</value>
            </interrupt>
            <registers>
                <register>
                    <name>RBR</name>
                    <description>Receiver Buffer Register. Contains the next received character to
                        be read (DLAB =0).</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <readAction>modify</readAction>
                    <fields>
                        <field>
                            <name>RBR</name>
                            <description>The UARTn Receiver Buffer Register contains the oldest
                                received byte in the UARTn Rx FIFO.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>THR</name>
                    <description>Transmit Holding Regiter. The next character to be transmitted is
                        written here (DLAB =0).</description>
                    <alternateRegister>RBR</alternateRegister>
                    <addressOffset>0x000</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>THR</name>
                            <description>Writing to the UARTn Transmit Holding Register causes the
                                data to be stored in the UARTn transmit FIFO. The byte will be sent
                                when it reaches the bottom of the FIFO and the transmitter is
                                available.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DLL</name>
                    <description>Divisor Latch LSB. Least significant byte of the baud rate divisor
                        value. The full divisor is used to generate a baud rate from the fractional
                        rate divider (DLAB =1).</description>
                    <alternateRegister>RBR</alternateRegister>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x01</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DLLSB</name>
                            <description>The UARTn Divisor Latch LSB Register, along with the UnDLM
                                register, determines the baud rate of the UARTn.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DLM</name>
                    <description>Divisor Latch MSB. Most significant byte of the baud rate divisor
                        value. The full divisor is used to generate a baud rate from the fractional
                        rate divider (DLAB =1).</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DLMSB</name>
                            <description>The UARTn Divisor Latch MSB Register, along with the U0DLL
                                register, determines the baud rate of the UARTn.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IER</name>
                    <description>Interrupt Enable Register. Contains individual interrupt enable
                        bits for the 7 potential UART interrupts (DLAB =0).</description>
                    <alternateRegister>DLM</alternateRegister>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RBRIE</name>
                            <description>RBR Interrupt Enable. Enables the Receive Data Available
                                interrupt for UARTn. It also controls the Character Receive Time-out
                                interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_RDA_INTE</name>
                                    <description>Disable the RDA interrupts.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_RDA_INTER</name>
                                    <description>Enable the RDA interrupts.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>THREIE</name>
                            <description>THRE Interrupt Enable. Enables the THRE interrupt for
                                UARTn. The status of this can be read from UnLSR[5].</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_THRE_INT</name>
                                    <description>Disable the THRE interrupts.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_THRE_INTE</name>
                                    <description>Enable the THRE interrupts.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RXIE</name>
                            <description>RX Line Status Interrupt Enable. Enables the UARTn RX line
                                status interrupts. The status of this interrupt can be read from
                                UnLSR[4:1].</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_RX_LINE_</name>
                                    <description>Disable the RX line status interrupts.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_RX_LINE_S</name>
                                    <description>Enable the RX line status interrupts.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[7:3]</bitRange>
                        </field>
                        <field>
                            <name>ABEOINTEN</name>
                            <description>Enables the end of auto-baud interrupt.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_END_OF_AUTO_</name>
                                    <description>Disable end of auto-baud Interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_END_OF_AUTO_B</name>
                                    <description>Enable end of auto-baud Interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ABTOINTEN</name>
                            <description>Enables the auto-baud time-out interrupt.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_AUTO_BAUD_TI</name>
                                    <description>Disable auto-baud time-out Interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_AUTO_BAUD_TIM</name>
                                    <description>Enable auto-baud time-out Interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IIR</name>
                    <description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x01</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>INTSTATUS</name>
                            <description>Interrupt status. Note that UnIIR[0] is active low. The
                                pending interrupt can be determined by evaluating UnIIR[3:1].</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>AT_LEAST_ONE_INTERRU</name>
                                    <description>At least one interrupt is pending.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NO_INTERRUPT_IS_PEND</name>
                                    <description>No interrupt is pending.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>INTID</name>
                            <description>Interrupt identification. UnIER[3:1] identifies an
                                interrupt corresponding to the UARTn Rx or TX FIFO. All other
                                combinations of UnIER[3:1] not listed below are reserved
                                (000,100,101,111).</description>
                            <bitRange>[3:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>1_RECEIVE_LINE_S</name>
                                    <description>1 - Receive Line Status (RLS).</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>2A__RECEIVE_DATA_AV</name>
                                    <description>2a - Receive Data Available (RDA).</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>2B__CHARACTER_TIME_</name>
                                    <description>2b - Character Time-out Indicator (CTI).</description>
                                    <value>0x6</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>3_THRE_INTERRUPT</name>
                                    <description>3 - THRE Interrupt</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[5:4]</bitRange>
                        </field>
                        <field>
                            <name>FIFOENABLE</name>
                            <description>Copies of UnFCR[0].</description>
                            <bitRange>[7:6]</bitRange>
                        </field>
                        <field>
                            <name>ABEOINT</name>
                            <description>End of auto-baud interrupt. True if auto-baud has finished
                                successfully and interrupt is enabled.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>ABTOINT</name>
                            <description>Auto-baud time-out interrupt. True if auto-baud has timed
                                out and interrupt is enabled.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FCR</name>
                    <description>FIFO Control Register. Controls UART FIFO usage and modes.</description>
                    <alternateRegister>IIR</alternateRegister>
                    <addressOffset>0x008</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FIFOEN</name>
                            <description>FIFO Enable.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>UARTN_FIFOS_ARE_DISA</name>
                                    <description>UARTn FIFOs are disabled. Must not be used in the
                                        application.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE_HIGH_ENABLE_F</name>
                                    <description>Active high enable for both UARTn Rx and TX FIFOs
                                        and UnFCR[7:1] access. This bit must be set for proper UART
                                        operation. Any transition on this bit will automatically
                                        clear the related UART FIFOs.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RXFIFORES</name>
                            <description>RX FIFO Reset.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_IMPACT_ON_EITHER_</name>
                                    <description>No impact on either of UARTn FIFOs.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>WRITING_A_LOGIC_1_TO</name>
                                    <description>Writing a logic 1 to UnFCR[1] will clear all bytes
                                        in UARTn Rx FIFO, reset the pointer logic. This bit is
                                        self-clearing.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TXFIFORES</name>
                            <description>TX FIFO Reset.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_IMPACT_ON_EITHER_</name>
                                    <description>No impact on either of UARTn FIFOs.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>WRITING_A_LOGIC_1_TO</name>
                                    <description>Writing a logic 1 to UnFCR[2] will clear all bytes
                                        in UARTn TX FIFO, reset the pointer logic. This bit is
                                        self-clearing.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DMAMODE</name>
                            <description>DMA Mode Select. When the FIFO enable (bit 0 of this
                                register) is set, this bit selects the DMA mode. See Section
                                18.6.6.1.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[5:4]</bitRange>
                        </field>
                        <field>
                            <name>RXTRIGLVL</name>
                            <description>RX Trigger Level. These two bits determine how many
                                receiver UARTn FIFO characters must be written before an interrupt
                                or DMA request is activated.</description>
                            <bitRange>[7:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TRIGGER_LEVEL_0_1_C</name>
                                    <description>Trigger level 0 (1 character or 0x01).</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRIGGER_LEVEL_1_4_C</name>
                                    <description>Trigger level 1 (4 characters or 0x04).</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRIGGER_LEVEL_2_8_C</name>
                                    <description>Trigger level 2 (8 characters or 0x08).</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRIGGER_LEVEL_3_14_</name>
                                    <description>Trigger level 3 (14 characters or 0x0E).</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>LCR</name>
                    <description>Line Control Register. Contains controls for frame formatting and
                        break generation.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>WLS</name>
                            <description>Word Length Select.</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>5_BIT_CHARACTER_LENG</name>
                                    <description>5-bit character length</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>6_BIT_CHARACTER_LENG</name>
                                    <description>6-bit character length</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>7_BIT_CHARACTER_LENG</name>
                                    <description>7-bit character length</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>8_BIT_CHARACTER_LENG</name>
                                    <description>8-bit character length</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SBS</name>
                            <description>Stop Bit Select</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>1_STOP_BIT_</name>
                                    <description>1 stop bit.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>2_STOP_BITS_1_5_IF_</name>
                                    <description>2 stop bits (1.5 if UnLCR[1:0]=00).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PE</name>
                            <description>Parity Enable.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_PARITY_GENER</name>
                                    <description>Disable parity generation and checking.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_PARITY_GENERA</name>
                                    <description>Enable parity generation and checking.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PS</name>
                            <description>Parity Select</description>
                            <bitRange>[5:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ODD_PARITY_NUMBER_O</name>
                                    <description>Odd parity. Number of 1s in the transmitted
                                        character and the attached parity bit will be odd.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EVEN_PARITY_NUMBER_</name>
                                    <description>Even Parity. Number of 1s in the transmitted
                                        character and the attached parity bit will be even.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FORCED_1_STICK_PARIT</name>
                                    <description>Forced 1 stick parity.</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FORCED_0_STICK_PARIT</name>
                                    <description>Forced 0 stick parity.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>BC</name>
                            <description>Break Control</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_BREAK_TRANSM</name>
                                    <description>Disable break transmission.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_BREAK_TRANSMI</name>
                                    <description>Enable break transmission. Output pin UARTn TXD is
                                        forced to logic 0 when UnLCR[6] is active high.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DLAB</name>
                            <description>Divisor Latch Access Bit</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_ACCESS_TO_DI</name>
                                    <description>Disable access to Divisor Latches.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_ACCESS_TO_DIV</name>
                                    <description>Enable access to Divisor Latches.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>LSR</name>
                    <description>Line Status Register. Contains flags for transmit and receive
                        status, including line errors.</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x60</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <readAction>modify</readAction>
                    <fields>
                        <field>
                            <name>RDR</name>
                            <description>Receiver Data Ready. UnLSR[0] is set when the UnRBR holds
                                an unread character and is cleared when the UARTn RBR FIFO is empty.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>EMPTY</name>
                                    <description>The UARTn receiver FIFO is empty.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NOTEMPTY</name>
                                    <description>The UARTn receiver FIFO is not empty.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>OE</name>
                            <description>Overrun Error. The overrun error condition is set as soon
                                as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when
                                UARTn RSR has a new character assembled and the UARTn RBR FIFO is
                                full. In this case, the UARTn RBR FIFO will not be overwritten and
                                the character in the UARTn RSR will be lost.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INACTIVE</name>
                                    <description>Overrun error status is inactive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE</name>
                                    <description>Overrun error status is active.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PE</name>
                            <description>Parity Error. When the parity bit of a received character
                                is in the wrong state, a parity error occurs. An UnLSR read clears
                                UnLSR[2]. Time of parity error detection is dependent on UnFCR[0].
                                Note: A parity error is associated with the character at the top of
                                the UARTn RBR FIFO.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INACTIVE</name>
                                    <description>Parity error status is inactive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE</name>
                                    <description>Parity error status is active.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>FE</name>
                            <description>Framing Error. When the stop bit of a received character is
                                a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3].
                                The time of the framing error detection is dependent on UnFCR[0].
                                Upon detection of a framing error, the Rx will attempt to
                                resynchronize to the data and assume that the bad stop bit is
                                actually an early start bit. However, it cannot be assumed that the
                                next received byte will be correct even if there is no Framing
                                Error. Note: A framing error is associated with the character at the
                                top of the UARTn RBR FIFO.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INACTIVE</name>
                                    <description>Framing error status is inactive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE</name>
                                    <description>Framing error status is active.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>BI</name>
                            <description>Break Interrupt. When RXDn is held in the spacing state
                                (all zeroes) for one full character transmission (start, data,
                                parity, stop), a break interrupt occurs. Once the break condition
                                has been detected, the receiver goes idle until RXDn goes to marking
                                state (all ones). An UnLSR read clears this status bit. The time of
                                break detection is dependent on UnFCR[0]. Note: The break interrupt
                                is associated with the character at the top of the UARTn RBR FIFO.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INACTIVE</name>
                                    <description>Break interrupt status is inactive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE</name>
                                    <description>Break interrupt status is active.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>THRE</name>
                            <description>Transmitter Holding Register Empty. THRE is set immediately
                                upon detection of an empty UARTn THR and is cleared on a UnTHR
                                write.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>VALIDDATA</name>
                                    <description>UnTHR contains valid data.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EMPTY</name>
                                    <description>UnTHR is empty.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TEMT</name>
                            <description>Transmitter Empty. TEMT is set when both UnTHR and UnTSR
                                are empty; TEMT is cleared when either the UnTSR or the UnTHR
                                contain valid data.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>VALIDDATA</name>
                                    <description>UnTHR and/or the UnTSR contains valid data.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EMPTY</name>
                                    <description>UnTHR and the UnTSR are empty.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RXFE</name>
                            <description>Error in RX FIFO . UnLSR[7] is set when a character with a
                                Rx error such as framing error, parity error or break interrupt, is
                                loaded into the UnRBR. This bit is cleared when the UnLSR register
                                is read and there are no subsequent errors in the UARTn FIFO.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NOERROR</name>
                                    <description>UnRBR contains no UARTn RX errors or UnFCR[0]=0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ERRORS</name>
                                    <description>UARTn RBR contains at least one UARTn RX error.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SCR</name>
                    <description>Scratch Pad Register. 8-bit temporary storage for software.</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PAD</name>
                            <description>A readable, writable byte.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ACR</name>
                    <description>Auto-baud Control Register. Contains controls for the auto-baud
                        feature.</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>START</name>
                            <description>Start bit. This bit is automatically cleared after
                                auto-baud completion.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>AUTO_BAUD_STOP_AUTO</name>
                                    <description>Auto-baud stop (auto-baud is not running).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>AUTO_BAUD_START_AUT</name>
                                    <description>Auto-baud start (auto-baud is running). Auto-baud
                                        run bit. This bit is automatically cleared after auto-baud
                                        completion.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MODE</name>
                            <description>Auto-baud mode select bit.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MODE_0_</name>
                                    <description>Mode 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MODE_1_</name>
                                    <description>Mode 1.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>AUTORESTART</name>
                            <description>Restart bit.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_RESTART_</name>
                                    <description>No restart.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESTART_IN_CASE_OF_T</name>
                                    <description>Restart in case of time-out (counter restarts at
                                        next UARTn Rx falling edge)</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[7:3]</bitRange>
                        </field>
                        <field>
                            <name>ABEOINTCLR</name>
                            <description>End of auto-baud interrupt clear bit (write-only
                                accessible). Writing a 1 will clear the corresponding interrupt in
                                the UnIIR. Writing a 0 has no impact.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_IMPACT_</name>
                                    <description>No impact.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CLEAR_THE_CORRESPOND</name>
                                    <description>Clear the corresponding interrupt in the IIR.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ABTOINTCLR</name>
                            <description>Auto-baud time-out interrupt clear bit (write-only
                                accessible). Writing a 1 will clear the corresponding interrupt in
                                the UnIIR. Writing a 0 has no impact.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_IMPACT_</name>
                                    <description>No impact.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CLEAR_THE_CORRESPOND</name>
                                    <description>Clear the corresponding interrupt in the IIR.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FDR</name>
                    <description>Fractional Divider Register. Generates a clock input for the baud
                        rate divider.</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x10</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DIVADDVAL</name>
                            <description>Baud-rate generation pre-scaler divisor value. If this
                                field is 0, fractional baud-rate generator will not impact the UARTn
                                baudrate.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>MULVAL</name>
                            <description>Baud-rate pre-scaler multiplier value. This field must be
                                greater or equal 1 for UARTn to operate properly, regardless of
                                whether the fractional baud-rate generator is used or not.</description>
                            <bitRange>[7:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TER</name>
                    <description>Transmit Enable Register. Turns off UART transmitter for use with
                        software flow control.</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x80</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[6:0]</bitRange>
                        </field>
                        <field>
                            <name>TXEN</name>
                            <description>When this bit is 1, as it is after a Reset, data written to
                                the THR is output on the TXD pin as soon as any preceding data has
                                been sent. If this bit is cleared to 0 while a character is being
                                sent, the transmission of that character is completed, but no
                                further characters are sent until this bit is set again. In other
                                words, a 0 in this bit blocks the transfer of characters from the
                                THR or TX FIFO into the transmit shift register. Software
                                implementing software-handshaking can clear this bit when it
                                receives an XOFF character (DC3). Software can set this bit again
                                when it receives an XON (DC1) character.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RS485CTRL</name>
                    <description>RS-485/EIA-485 Control. Contains controls to configure various
                        aspects of RS-485/EIA-485 modes.</description>
                    <addressOffset>0x04C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>NMMEN</name>
                            <description>NMM enable.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is
                                        disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED</name>
                                    <description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is
                                        enabled. In this mode, an address is detected when a
                                        received byte has the parity bit = 1, generating a received
                                        data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of
                                        operation.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RXDIS</name>
                            <description>Receiver enable.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLED</name>
                                    <description>The receiver is enabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>The receiver is disabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>AADEN</name>
                            <description>AAD enable.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Auto Address Detect (AAD) is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED</name>
                                    <description>Auto Address Detect (AAD) is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>DCTRL</name>
                            <description>Direction control enable.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_AUTO_DIRECTI</name>
                                    <description>Disable Auto Direction Control.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_AUTO_DIRECTIO</name>
                                    <description>Enable Auto Direction Control.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>OINV</name>
                            <description>Direction control pin polarity. This bit reverses the
                                polarity of the direction control signal on the Un_OE pin.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DIRLOW</name>
                                    <description>The direction control pin will be driven to logic 0
                                        when the transmitter has data to be sent. It will be driven
                                        to logic 1 after the last bit of data has been transmitted.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DIRHIGH</name>
                                    <description>The direction control pin will be driven to logic 1
                                        when the transmitter has data to be sent. It will be driven
                                        to logic 0 after the last bit of data has been transmitted.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RS485ADRMATCH</name>
                    <description>RS-485/EIA-485 address match. Contains the address match value for
                        RS-485/EIA-485 mode.</description>
                    <addressOffset>0x050</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ADRMATCH</name>
                            <description>Contains the address match value.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RS485DLY</name>
                    <description>RS-485/EIA-485 direction control delay.</description>
                    <addressOffset>0x054</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DLY</name>
                            <description>Contains the direction control (UnOE) delay value. This
                                register works in conjunction with an 8-bit counter.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>UART1</name>
            <description>UART1 </description>
            <groupName>UART1</groupName>
            <baseAddress>0x40010000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>UART1</name>
                <value>6</value>
            </interrupt>
            <registers>
                <register>
                    <name>RBR</name>
                    <description>DLAB =0 Receiver Buffer Register. Contains the next received
                        character to be read.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <readAction>modify</readAction>
                    <fields>
                        <field>
                            <name>RBR</name>
                            <description>The UART1 Receiver Buffer Register contains the oldest
                                received byte in the UART1 RX FIFO.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>THR</name>
                    <description>DLAB =0. Transmit Holding Register. The next character to be
                        transmitted is written here.</description>
                    <alternateRegister>RBR</alternateRegister>
                    <addressOffset>0x000</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>THR</name>
                            <description>Writing to the UART1 Transmit Holding Register causes the
                                data to be stored in the UART1 transmit FIFO. The byte will be sent
                                when it reaches the bottom of the FIFO and the transmitter is
                                available.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DLL</name>
                    <description>DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate
                        divisor value. The full divisor is used to generate a baud rate from the
                        fractional rate divider.</description>
                    <alternateRegister>RBR</alternateRegister>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x01</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DLLSB</name>
                            <description>The UART1 Divisor Latch LSB Register, along with the U1DLM
                                register, determines the baud rate of the UART1.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DLM</name>
                    <description>DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate
                        divisor value. The full divisor is used to generate a baud rate from the
                        fractional rate divider.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DLMSB</name>
                            <description>The UART1 Divisor Latch MSB Register, along with the U1DLL
                                register, determines the baud rate of the UART1.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IER</name>
                    <description>DLAB =0. Interrupt Enable Register. Contains individual interrupt
                        enable bits for the 7 potential UART1 interrupts.</description>
                    <alternateRegister>DLM</alternateRegister>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RBRIE</name>
                            <description>RBR Interrupt Enable. Enables the Receive Data Available
                                interrupt for UART1. It also controls the Character Receive Time-out
                                interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_RDA_INTE</name>
                                    <description>Disable the RDA interrupts.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_RDA_INTER</name>
                                    <description>Enable the RDA interrupts.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>THREIE</name>
                            <description>THRE Interrupt Enable. Enables the THRE interrupt for
                                UART1. The status of this interrupt can be read from LSR[5].</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_THRE_INT</name>
                                    <description>Disable the THRE interrupts.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_THRE_INTE</name>
                                    <description>Enable the THRE interrupts.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RXIE</name>
                            <description>RX Line Interrupt Enable. Enables the UART1 RX line status
                                interrupts. The status of this interrupt can be read from LSR[4:1].</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_RX_LINE_</name>
                                    <description>Disable the RX line status interrupts.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_RX_LINE_S</name>
                                    <description>Enable the RX line status interrupts.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MSIE</name>
                            <description>Modem Status Interrupt Enable. Enables the modem interrupt.
                                The status of this interrupt can be read from MSR[3:0].</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_MODEM_IN</name>
                                    <description>Disable the modem interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_MODEM_INT</name>
                                    <description>Enable the modem interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[6:4]</bitRange>
                        </field>
                        <field>
                            <name>CTSIE</name>
                            <description>CTS Interrupt Enable. If auto-cts mode is enabled this bit
                                enables/disables the modem status interrupt generation on a CTS1
                                signal transition. If auto-cts mode is disabled a CTS1 transition
                                will generate an interrupt if Modem Status Interrupt Enable (IER[3])
                                is set. In normal operation a CTS1 signal transition will generate a
                                Modem Status Interrupt unless the interrupt has been disabled by
                                clearing the IER[3] bit in the IER register. In auto-cts mode a
                                transition on the CTS1 bit will trigger an interrupt only if both
                                the IER[3] and IER[7] bits are set.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_CTS_INTE</name>
                                    <description>Disable the CTS interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_CTS_INTER</name>
                                    <description>Enable the CTS interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ABEOIE</name>
                            <description>Enables the end of auto-baud interrupt.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_END_OF_AUTO_</name>
                                    <description>Disable end of auto-baud Interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_END_OF_AUTO_B</name>
                                    <description>Enable end of auto-baud Interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ABTOIE</name>
                            <description>Enables the auto-baud time-out interrupt.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_AUTO_BAUD_TI</name>
                                    <description>Disable auto-baud time-out Interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_AUTO_BAUD_TIM</name>
                                    <description>Enable auto-baud time-out Interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IIR</name>
                    <description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x01</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>INTSTATUS</name>
                            <description>Interrupt status. Note that IIR[0] is active low. The
                                pending interrupt can be determined by evaluating IIR[3:1].</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>AT_LEAST_ONE_INTERRU</name>
                                    <description>At least one interrupt is pending.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NO_INTERRUPT_IS_PEND</name>
                                    <description>No interrupt is pending.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>INTID</name>
                            <description>Interrupt identification. IER[3:1] identifies an interrupt
                                corresponding to the UART1 Rx or TX FIFO. All other combinations of
                                IER[3:1] not listed below are reserved (100,101,111).</description>
                            <bitRange>[3:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RLS</name>
                                    <description>1 - Receive Line Status (RLS).</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RDA</name>
                                    <description>2a - Receive Data Available (RDA).</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CTI</name>
                                    <description>2b - Character Time-out Indicator (CTI).</description>
                                    <value>0x6</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THRE</name>
                                    <description>3 - THRE Interrupt.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MODEM</name>
                                    <description>4 - Modem Interrupt.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[5:4]</bitRange>
                        </field>
                        <field>
                            <name>FIFOENABLE</name>
                            <description>Copies of FCR[0].</description>
                            <bitRange>[7:6]</bitRange>
                        </field>
                        <field>
                            <name>ABEOINT</name>
                            <description>End of auto-baud interrupt. True if auto-baud has finished
                                successfully and interrupt is enabled.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>ABTOINT</name>
                            <description>Auto-baud time-out interrupt. True if auto-baud has timed
                                out and interrupt is enabled.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FCR</name>
                    <description>FIFO Control Register. Controls UART1 FIFO usage and modes.</description>
                    <alternateRegister>IIR</alternateRegister>
                    <addressOffset>0x008</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FIFOEN</name>
                            <description>FIFO enable.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MUST_NOT_BE_USED_IN_</name>
                                    <description>Must not be used in the application.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE_HIGH_ENABLE_F</name>
                                    <description>Active high enable for both UART1 Rx and TX FIFOs
                                        and FCR[7:1] access. This bit must be set for proper UART1
                                        operation. Any transition on this bit will automatically
                                        clear the UART1 FIFOs.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RXFIFORES</name>
                            <description>RX FIFO Reset.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_IMPACT_ON_EITHER_</name>
                                    <description>No impact on either of UART1 FIFOs.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>WRITING_A_LOGIC_1_TO</name>
                                    <description>Writing a logic 1 to FCR[1] will clear all bytes in
                                        UART1 Rx FIFO, reset the pointer logic. This bit is
                                        self-clearing.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TXFIFORES</name>
                            <description>TX FIFO Reset.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_IMPACT_ON_EITHER_</name>
                                    <description>No impact on either of UART1 FIFOs.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>WRITING_A_LOGIC_1_TO</name>
                                    <description>Writing a logic 1 to FCR[2] will clear all bytes in
                                        UART1 TX FIFO, reset the pointer logic. This bit is
                                        self-clearing.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DMAMODE</name>
                            <description>DMA Mode Select. When the FIFO enable bit (bit 0 of this
                                register) is set, this bit selects the DMA mode. See Section
                                36.6.6.1.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[5:4]</bitRange>
                        </field>
                        <field>
                            <name>RXTRIGLVL</name>
                            <description>RX Trigger Level. These two bits determine how many
                                receiver UART1 FIFO characters must be written before an interrupt
                                is activated.</description>
                            <bitRange>[7:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TRIGGER_LEVEL_0_1_C</name>
                                    <description>Trigger level 0 (1 character or 0x01).</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRIGGER_LEVEL_1_4_C</name>
                                    <description>Trigger level 1 (4 characters or 0x04).</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRIGGER_LEVEL_2_8_C</name>
                                    <description>Trigger level 2 (8 characters or 0x08).</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRIGGER_LEVEL_3_14_</name>
                                    <description>Trigger level 3 (14 characters or 0x0E).</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>LCR</name>
                    <description>Line Control Register. Contains controls for frame formatting and
                        break generation.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>WLS</name>
                            <description>Word Length Select.</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>5_BIT_CHARACTER_LENG</name>
                                    <description>5-bit character length.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>6_BIT_CHARACTER_LENG</name>
                                    <description>6-bit character length.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>7_BIT_CHARACTER_LENG</name>
                                    <description>7-bit character length.</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>8_BIT_CHARACTER_LENG</name>
                                    <description>8-bit character length.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SBS</name>
                            <description>Stop Bit Select.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>1_STOP_BIT_</name>
                                    <description>1 stop bit.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>2_STOP_BITS_1_5_IF_</name>
                                    <description>2 stop bits (1.5 if LCR[1:0]=00).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PE</name>
                            <description>Parity Enable.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_PARITY_GENER</name>
                                    <description>Disable parity generation and checking.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_PARITY_GENERA</name>
                                    <description>Enable parity generation and checking.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PS</name>
                            <description>Parity Select.</description>
                            <bitRange>[5:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ODD_PARITY_NUMBER_O</name>
                                    <description>Odd parity. Number of 1s in the transmitted
                                        character and the attached parity bit will be odd.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EVEN_PARITY_NUMBER_</name>
                                    <description>Even Parity. Number of 1s in the transmitted
                                        character and the attached parity bit will be even.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FORCED1STICK_PAR</name>
                                    <description>Forced 1 stick parity.</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FORCED0STICK_PAR</name>
                                    <description>Forced 0 stick parity.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>BC</name>
                            <description>Break Control.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_BREAK_TRANSM</name>
                                    <description>Disable break transmission.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_BREAK_TRANSMI</name>
                                    <description>Enable break transmission. Output pin UART1 TXD is
                                        forced to logic 0 when LCR[6] is active high.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DLAB</name>
                            <description>Divisor Latch Access Bit (DLAB)</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_ACCESS_TO_DI</name>
                                    <description>Disable access to Divisor Latches.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_ACCESS_TO_DIV</name>
                                    <description>Enable access to Divisor Latches.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MCR</name>
                    <description>Modem Control Register. Contains controls for flow control
                        handshaking and loopback mode.</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DTRCTRL</name>
                            <description>DTR Control. Source for modem output pin, DTR. This bit
                                reads as 0 when modem loopback mode is active.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RTSCTRL</name>
                            <description>RTS Control. Source for modem output pin RTS. This bit
                                reads as 0 when modem loopback mode is active.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[3:2]</bitRange>
                        </field>
                        <field>
                            <name>LMS</name>
                            <description>Loopback Mode Select. The modem loopback mode provides a
                                mechanism to perform diagnostic loopback testing. Serial data from
                                the transmitter is connected internally to serial input of the
                                receiver. Input pin, RXD1, has no effect on loopback and output pin,
                                TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and
                                DCD) are disconnected externally. Externally, the modem outputs
                                (RTS, DTR) are set inactive. Internally, the 4 modem outputs are
                                connected to the 4 modem inputs. As a result of these connections,
                                the upper 4 bits of the MSR will be driven by the lower 4 bits of
                                the MCR rather than the 4 modem inputs in normal mode. This permits
                                modem status interrupts to be generated in loopback mode by writing
                                the lower 4 bits of MCR.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_MODEM_LOOPBA</name>
                                    <description>Disable modem loopback mode.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_MODEM_LOOPBAC</name>
                                    <description>Enable modem loopback mode.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RTSEN</name>
                            <description>RTS enable.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_AUTO_RTS_FLO</name>
                                    <description>Disable auto-rts flow control.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_AUTO_RTS_FLOW</name>
                                    <description>Enable auto-rts flow control.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CTSEN</name>
                            <description>CTS enable.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_AUTO_CTS_FLO</name>
                                    <description>Disable auto-cts flow control.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_AUTO_CTS_FLOW</name>
                                    <description>Enable auto-cts flow control.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>LSR</name>
                    <description>Line Status Register. Contains flags for transmit and receive
                        status, including line errors.</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x60</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <readAction>modify</readAction>
                    <fields>
                        <field>
                            <name>RDR</name>
                            <description>Receiver Data Ready. LSR[0] is set when the RBR holds an
                                unread character and is cleared when the UART1 RBR FIFO is empty.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>EMPTY</name>
                                    <description>The UART1 receiver FIFO is empty.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NOTEMPTY</name>
                                    <description>The UART1 receiver FIFO is not empty.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>OE</name>
                            <description>Overrun Error. The overrun error condition is set as soon
                                as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1
                                RSR has a new character assembled and the UART1 RBR FIFO is full. In
                                this case, the UART1 RBR FIFO will not be overwritten and the
                                character in the UART1 RSR will be lost.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INACTIVE</name>
                                    <description>Overrun error status is inactive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE</name>
                                    <description>Overrun error status is active.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PE</name>
                            <description>Parity Error. When the parity bit of a received character
                                is in the wrong state, a parity error occurs. An LSR read clears
                                LSR[2]. Time of parity error detection is dependent on FCR[0]. Note:
                                A parity error is associated with the character at the top of the
                                UART1 RBR FIFO.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INACTIVE</name>
                                    <description>Parity error status is inactive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE</name>
                                    <description>Parity error status is active.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>FE</name>
                            <description>Framing Error. When the stop bit of a received character is
                                a logic 0, a framing error occurs. An LSR read clears LSR[3]. The
                                time of the framing error detection is dependent on FCR0. Upon
                                detection of a framing error, the RX will attempt to resynchronize
                                to the data and assume that the bad stop bit is actually an early
                                start bit. However, it cannot be assumed that the next received byte
                                will be correct even if there is no Framing Error. Note: A framing
                                error is associated with the character at the top of the UART1 RBR
                                FIFO.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INACTIVE</name>
                                    <description>Framing error status is inactive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE</name>
                                    <description>Framing error status is active.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>BI</name>
                            <description>Break Interrupt. When RXD1 is held in the spacing state
                                (all zeroes) for one full character transmission (start, data,
                                parity, stop), a break interrupt occurs. Once the break condition
                                has been detected, the receiver goes idle until RXD1 goes to marking
                                state (all ones). An LSR read clears this status bit. The time of
                                break detection is dependent on FCR[0]. Note: The break interrupt is
                                associated with the character at the top of the UART1 RBR FIFO.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INACTIVE</name>
                                    <description>Break interrupt status is inactive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ACTIVE</name>
                                    <description>Break interrupt status is active.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>THRE</name>
                            <description>Transmitter Holding Register Empty. THRE is set immediately
                                upon detection of an empty UART1 THR and is cleared on a THR write.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>VALID</name>
                                    <description>THR contains valid data.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THR_IS_EMPTY_</name>
                                    <description>THR is empty.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TEMT</name>
                            <description>Transmitter Empty. TEMT is set when both THR and TSR are
                                empty; TEMT is cleared when either the TSR or the THR contain valid
                                data.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>VALID</name>
                                    <description>THR and/or the TSR contains valid data.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EMPTY</name>
                                    <description>THR and the TSR are empty.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RXFE</name>
                            <description>Error in RX FIFO. LSR[7] is set when a character with a RX
                                error such as framing error, parity error or break interrupt, is
                                loaded into the RBR. This bit is cleared when the LSR register is
                                read and there are no subsequent errors in the UART1 FIFO.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NOERROR</name>
                                    <description>RBR contains no UART1 RX errors or FCR[0]=0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ERRORS</name>
                                    <description>UART1 RBR contains at least one UART1 RX error.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MSR</name>
                    <description>Modem Status Register. Contains handshake signal status flags.</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <readAction>modify</readAction>
                    <fields>
                        <field>
                            <name>DCTS</name>
                            <description>Delta CTS. Set upon state change of input CTS. Cleared on
                                an MSR read.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_CHANGE_DETECTED_O</name>
                                    <description>No change detected on modem input, CTS.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STATE_CHANGE_DETECTE</name>
                                    <description>State change detected on modem input, CTS.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DDSR</name>
                            <description>Delta DSR. Set upon state change of input DSR. Cleared on
                                an MSR read.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_CHANGE_DETECTED_O</name>
                                    <description>No change detected on modem input, DSR.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STATE_CHANGE_DETECTE</name>
                                    <description>State change detected on modem input, DSR.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TERI</name>
                            <description>Trailing Edge RI. Set upon low to high transition of input
                                RI. Cleared on an MSR read.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_CHANGE_DETECTED_O</name>
                                    <description>No change detected on modem input, RI.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>LOW_TO_HIGH_TRANSITI</name>
                                    <description>Low-to-high transition detected on RI.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DDCD</name>
                            <description>Delta DCD. Set upon state change of input DCD. Cleared on
                                an MSR read.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_CHANGE_DETECTED_O</name>
                                    <description>No change detected on modem input, DCD.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STATE_CHANGE_DETECTE</name>
                                    <description>State change detected on modem input, DCD.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CTS</name>
                            <description>Clear To Send State. Complement of input signal CTS. This
                                bit is connected to MCR[1] in modem loopback mode.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>DSR</name>
                            <description>Data Set Ready State. Complement of input signal DSR. This
                                bit is connected to MCR[0] in modem loopback mode.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RI</name>
                            <description>Ring Indicator State. Complement of input RI. This bit is
                                connected to MCR[2] in modem loopback mode.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>DCD</name>
                            <description>Data Carrier Detect State. Complement of input DCD. This
                                bit is connected to MCR[3] in modem loopback mode.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SCR</name>
                    <description>Scratch Pad Register. 8-bit temporary storage for software.</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>Pad</name>
                            <description>A readable, writable byte.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ACR</name>
                    <description>Auto-baud Control Register. Contains controls for the auto-baud
                        feature.</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>START</name>
                            <description>Auto-baud start bit. This bit is automatically cleared
                                after auto-baud completion.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>STOP</name>
                                    <description>Auto-baud stop (auto-baud is not running).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>START</name>
                                    <description>Auto-baud start (auto-baud is running). Auto-baud
                                        run bit. This bit is automatically cleared after auto-baud
                                        completion.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MODE</name>
                            <description>Auto-baud mode select bit.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MODE_0_</name>
                                    <description>Mode 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MODE_1_</name>
                                    <description>Mode 1.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>AUTORESTART</name>
                            <description>Auto-baud restart bit.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_RESTART</name>
                                    <description>No restart</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESTART_IN_CASE_OF_T</name>
                                    <description>Restart in case of time-out (counter restarts at
                                        next UART1 Rx falling edge)</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[7:3]</bitRange>
                        </field>
                        <field>
                            <name>ABEOINTCLR</name>
                            <description>End of auto-baud interrupt clear bit (write-only).</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>WRITING_A_0_HAS_NO_I</name>
                                    <description>Writing a 0 has no impact.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>WRITING_A_1_WILL_CLE</name>
                                    <description>Writing a 1 will clear the corresponding interrupt
                                        in the IIR.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ABTOINTCLR</name>
                            <description>Auto-baud time-out interrupt clear bit (write-only).</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>WRITING_A_0_HAS_NO_I</name>
                                    <description>Writing a 0 has no impact.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>WRITING_A_1_WILL_CLE</name>
                                    <description>Writing a 1 will clear the corresponding interrupt
                                        in the IIR.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FDR</name>
                    <description>Fractional Divider Register. Generates a clock input for the baud
                        rate divider.</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x10</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DIVADDVAL</name>
                            <description>Baud rate generation pre-scaler divisor value. If this
                                field is 0, fractional baud rate generator will not impact the UART1
                                baud rate.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>MULVAL</name>
                            <description>Baud rate pre-scaler multiplier value. This field must be
                                greater or equal 1 for UART1 to operate properly, regardless of
                                whether the fractional baud rate generator is used or not.</description>
                            <bitRange>[7:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TER</name>
                    <description>Transmit Enable Register. Turns off UART transmitter for use with
                        software flow control.</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x80</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[6:0]</bitRange>
                        </field>
                        <field>
                            <name>TXEN</name>
                            <description>When this bit is 1, as it is after a Reset, data written to
                                the THR is output on the TXD pin as soon as any preceding data has
                                been sent. If this bit cleared to 0 while a character is being sent,
                                the transmission of that character is completed, but no further
                                characters are sent until this bit is set again. In other words, a 0
                                in this bit blocks the transfer of characters from the THR or TX
                                FIFO into the transmit shift register. Software can clear this bit
                                when it detects that the a hardware-handshaking TX-permit signal
                                (CTS) has gone false, or with software handshaking, when it receives
                                an XOFF character (DC3). Software can set this bit again when it
                                detects that the TX-permit signal has gone true, or when it receives
                                an XON (DC1) character.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RS485CTRL</name>
                    <description>RS-485/EIA-485 Control. Contains controls to configure various
                        aspects of RS-485/EIA-485 modes.</description>
                    <addressOffset>0x04C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>NMMEN</name>
                            <description>RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED_IN_THIS_MOD</name>
                                    <description>Enabled. In this mode, an address is detected when
                                        a received byte causes the UART to set the parity error and
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RXDIS</name>
                            <description>Receive enable.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLED_</name>
                                    <description>Enabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>AADEN</name>
                            <description>Auto Address Detect (AAD) enable.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED_</name>
                                    <description>Enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SEL</name>
                            <description>Direction control.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RTS_IF_DIRECTION_CO</name>
                                    <description>RTS. If direction control is enabled (bit DCTRL =
                                        1), pin RTS is used for direction control.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DTR_IF_DIRECTION_CO</name>
                                    <description>DTR. If direction control is enabled (bit DCTRL =
                                        1), pin DTR is used for direction control.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DCTRL</name>
                            <description>Direction control enable.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_AUTO_DIRECTI</name>
                                    <description>Disable Auto Direction Control.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_AUTO_DIRECTIO</name>
                                    <description>Enable Auto Direction Control.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>OINV</name>
                            <description>Polarity. This bit reverses the polarity of the direction
                                control signal on the RTS (or DTR) pin.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LOW_THE_DIRECTION_C</name>
                                    <description>LOW. The direction control pin will be driven to
                                        logic 0 when the transmitter has data to be sent. It will be
                                        driven to logic 1 after the last bit of data has been
                                        transmitted.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>HIGH_THE_DIRECTION_</name>
                                    <description>HIGH. The direction control pin will be driven to
                                        logic 1 when the transmitter has data to be sent. It will be
                                        driven to logic 0 after the last bit of data has been
                                        transmitted.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RS485ADRMATCH</name>
                    <description>RS-485/EIA-485 address match. Contains the address match value for
                        RS-485/EIA-485 mode.</description>
                    <addressOffset>0x050</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ADRMATCH</name>
                            <description>Contains the address match value.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RS485DLY</name>
                    <description>RS-485/EIA-485 direction control delay.</description>
                    <addressOffset>0x054</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DLY</name>
                            <description>Contains the direction control (RTS or DTR) delay value.
                                This register works in conjunction with an 8-bit counter.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>PWM1</name>
            <description>Pulse Width Modulators (PWM1) </description>
            <groupName>PWM</groupName>
            <baseAddress>0x40018000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>PWM1</name>
                <value>9</value>
            </interrupt>
            <registers>
                <register>
                    <name>IR</name>
                    <description>Interrupt Register. The IR can be written to clear interrupts, or
                        read to identify which PWM interrupt sources are pending.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PWMMR0INT</name>
                            <description>Interrupt flag for PWM match channel 0.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PWMMR1INT</name>
                            <description>Interrupt flag for PWM match channel 1.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>PWMMR2INT</name>
                            <description>Interrupt flag for PWM match channel 2.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PWMMR3INT</name>
                            <description>Interrupt flag for PWM match channel 3.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>PWMCAP0INT</name>
                            <description>Interrupt flag for capture input 0</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>PWMCAP1INT</name>
                            <description>Interrupt flag for capture input 1 (available in PWM1IR
                                only; this bit is reserved in PWM0IR).</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[7:6]</bitRange>
                        </field>
                        <field>
                            <name>PWMMR4INT</name>
                            <description>Interrupt flag for PWM match channel 4.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>PWMMR5INT</name>
                            <description>Interrupt flag for PWM match channel 5.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PWMMR6INT</name>
                            <description>Interrupt flag for PWM match channel 6.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:11]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TCR</name>
                    <description>Timer Control Register. The TCR is used to control the Timer
                        Counter functions.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CE</name>
                            <description>Counter Enable</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_TIMER_COUNTE</name>
                                    <description>The PWM Timer Counter and PWM Prescale Counter are
                                        enabled for counting.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_COUNTERS_ARE_DIS</name>
                                    <description>The counters are disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CR</name>
                            <description>Counter Reset</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_TIMER_COUNTE</name>
                                    <description>The PWM Timer Counter and the PWM Prescale Counter
                                        are synchronously reset on the next positive edge of PCLK.
                                        The counters remain reset until this bit is returned to
                                        zero.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CLEAR_RESET_</name>
                                    <description>Clear reset.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PWMEN</name>
                            <description>PWM Enable</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>PWM_MODE_IS_ENABLED_</name>
                                    <description>PWM mode is enabled (counter resets to 1). PWM mode
                                        causes the shadow registers to operate in connection with
                                        the Match registers. A program write to a Match register
                                        will not have an effect on the Match result until the
                                        corresponding bit in PWMLER has been set, followed by the
                                        occurrence of a PWM Match 0 event. Note that the PWM Match
                                        register that determines the PWM rate (PWM Match Register 0
                                        - MR0) must be set up prior to the PWM being enabled.
                                        Otherwise a Match event will not occur to cause shadow
                                        register contents to become effective.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TIMER_MODE_IS_ENABLE</name>
                                    <description>Timer mode is enabled (counter resets to 0).</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MDIS</name>
                            <description>Master Disable (PWM0 only). The two PWMs may be
                                synchronized using the Master Disable control bit. The Master
                                disable bit of the Master PWM (PWM0 module) controls a secondary
                                enable input to both PWMs, as shown in Figure 141. This bit has no
                                function in the Slave PWM (PWM1).</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MASTER_USE_PWM0_IS_</name>
                                    <description>Master use. PWM0 is the master, and both PWMs are
                                        enabled for counting.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INDIVIDUAL_USE_THE_</name>
                                    <description>Individual use. The PWMs are used independently,
                                        and the individual Counter Enable bits are used to control
                                        the PWMs.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TC</name>
                    <description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of
                        PCLK. The TC is controlled through the TCR.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TC</name>
                            <description>Timer counter value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PR</name>
                    <description>Prescale Register. Determines how often the PWM counter is
                        incremented.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PM</name>
                            <description>Prescale counter maximum value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PC</name>
                    <description>Prescale Counter. Prescaler for the main PWM counter.</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PC</name>
                            <description>Prescale counter value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MCR</name>
                    <description>Match Control Register. The MCR is used to control whether an
                        interrupt is generated and if the PWM counter is reset when a Match occurs.</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PWMMR0I</name>
                            <description>Interrupt PWM0</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ON_PWMMR0</name>
                                    <description>Interrupt on PWMMR0: an interrupt is generated when
                                        PWMMR0 matches the value in the PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR0R</name>
                            <description>Reset PWM0</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET_ON_PWMMR0_THE</name>
                                    <description>Reset on PWMMR0: the PWMTC will be reset if PWMMR0
                                        matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR0S</name>
                            <description>Stop PWM0</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STOP_ON_PWMMR0_THE_</name>
                                    <description>Stop on PWMMR0: the PWMTC and PWMPC will be stopped
                                        and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the
                                        PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR1I</name>
                            <description>Interrupt PWM1</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ON_PWMMR1</name>
                                    <description>Interrupt on PWMMR1: an interrupt is generated when
                                        PWMMR1 matches the value in the PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR1R</name>
                            <description>Reset PWM1</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET_ON_PWMMR1_THE</name>
                                    <description>Reset on PWMMR1: the PWMTC will be reset if PWMMR1
                                        matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR1S</name>
                            <description>Stop PWM1</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STOP_ON_PWMMR1_THE_</name>
                                    <description>Stop on PWMMR1: the PWMTC and PWMPC will be stopped
                                        and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the
                                        PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR2I</name>
                            <description>Interrupt PWM0</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ON_PWMMR2</name>
                                    <description>Interrupt on PWMMR2: an interrupt is generated when
                                        PWMMR2 matches the value in the PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR2R</name>
                            <description>Reset PWM0</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET_ON_PWMMR2_THE</name>
                                    <description>Reset on PWMMR2: the PWMTC will be reset if PWMMR2
                                        matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR2S</name>
                            <description>Stop PWM0</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STOP_ON_PWMMR2_THE_</name>
                                    <description>Stop on PWMMR2: the PWMTC and PWMPC will be stopped
                                        and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the
                                        PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR3I</name>
                            <description>Interrupt PWM3</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ON_PWMMR3</name>
                                    <description>Interrupt on PWMMR3: an interrupt is generated when
                                        PWMMR3 matches the value in the PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR3R</name>
                            <description>Reset PWM3</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET_ON_PWMMR3_THE</name>
                                    <description>Reset on PWMMR3: the PWMTC will be reset if PWMMR3
                                        matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR3S</name>
                            <description>Stop PWM0</description>
                            <bitRange>[11:11]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STOP_ON_PWMMR3_THE_</name>
                                    <description>Stop on PWMMR3: the PWMTC and PWMPC will be stopped
                                        and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the
                                        PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR4I</name>
                            <description>Interrupt PWM4</description>
                            <bitRange>[12:12]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ON_PWMMR4</name>
                                    <description>Interrupt on PWMMR4: an interrupt is generated when
                                        PWMMR4 matches the value in the PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR4R</name>
                            <description>Reset PWM4</description>
                            <bitRange>[13:13]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET_ON_PWMMR4_THE</name>
                                    <description>Reset on PWMMR4: the PWMTC will be reset if PWMMR4
                                        matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR4S</name>
                            <description>Stop PWM4</description>
                            <bitRange>[14:14]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STOP_ON_PWMMR4_THE_</name>
                                    <description>Stop on PWMMR4: the PWMTC and PWMPC will be stopped
                                        and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the
                                        PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR5I</name>
                            <description>Interrupt PWM5</description>
                            <bitRange>[15:15]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ON_PWMMR5</name>
                                    <description>Interrupt on PWMMR5: an interrupt is generated when
                                        PWMMR5 matches the value in the PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR5R</name>
                            <description>Reset PWM5</description>
                            <bitRange>[16:16]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET_ON_PWMMR5_THE</name>
                                    <description>Reset on PWMMR5: the PWMTC will be reset if PWMMR5
                                        matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR5S</name>
                            <description>Stop PWM5</description>
                            <bitRange>[17:17]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STOP_ON_PWMMR5_THE_</name>
                                    <description>Stop on PWMMR5: the PWMTC and PWMPC will be stopped
                                        and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the
                                        PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR6I</name>
                            <description>Interrupt PWM6</description>
                            <bitRange>[18:18]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ON_PWMMR6</name>
                                    <description>Interrupt on PWMMR6: an interrupt is generated when
                                        PWMMR6 matches the value in the PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR6R</name>
                            <description>Reset PWM6</description>
                            <bitRange>[19:19]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET_ON_PWMMR6_THE</name>
                                    <description>Reset on PWMMR6: the PWMTC will be reset if PWMMR6
                                        matches it.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMMR6S</name>
                            <description>Stop PWM6</description>
                            <bitRange>[20:20]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STOP_ON_PWMMR6_THE_</name>
                                    <description>Stop on PWMMR6: the PWMTC and PWMPC will be stopped
                                        and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the
                                        PWMTC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:21]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>4</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-3</dimIndex>
                    <name>MR[%s]</name>
                    <displayName>MR[%s]</displayName>
                    <description>Match Register. Match registers are continuously compared to the
                        PWM counter in order to control PWM output edges.</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MATCH</name>
                            <description>Timer counter match value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CCR</name>
                    <description>Capture Control Register. The CCR controls which edges of the
                        capture inputs are used to load the Capture Registers and whether or not an
                        interrupt is generated for a capture event.</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CAP0_R</name>
                            <description>Capture on PWMn_CAP0 rising edge</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_THIS_FEATU</name>
                                    <description>Disabled. This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING_EDGE_A_SYNCH</name>
                                    <description>Rising edge. A synchronously sampled rising edge on
                                        PWMn_CAP0 will cause CR0 to be loaded with the contents of
                                        the TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP0_F</name>
                            <description>Capture on PWMn_CAP0 falling edge</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_THIS_FEATU</name>
                                    <description>Disabled. This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING_EDGE_A_SYNC</name>
                                    <description>Falling edge. A synchronously sampled falling edge
                                        on PWMn_CAP0 will cause CR0 to be loaded with the contents
                                        of TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP0_I</name>
                            <description>Interrupt on PWMn_CAP0 event</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_THIS_FEATU</name>
                                    <description>Disabled. This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_A_CR0_LOA</name>
                                    <description>Interrupt. A CR0 load due to a PWMn_CAP0 event will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP1_R</name>
                            <description>Capture on PWMn_CAP1 rising edge. Reserved for PWM0.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_THIS_FEATU</name>
                                    <description>Disabled. This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING_EDGE_A_SYNCH</name>
                                    <description>Rising edge. A synchronously sampled rising edge on
                                        PWMn_CAP1 will cause CR1 to be loaded with the contents of
                                        the TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP1_F</name>
                            <description>Capture on PWMn_CAP1 falling edge. Reserved for PWM0.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_THIS_FEATU</name>
                                    <description>Disabled. This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING_EDGE_A_SYNC</name>
                                    <description>Falling edge. A synchronously sampled falling edge
                                        on PWMn_CAP1 will cause CR1 to be loaded with the contents
                                        of TC.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CAP1_I</name>
                            <description>Interrupt on PWMn_CAP1 event. Reserved for PWM0.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_THIS_FEATU</name>
                                    <description>Disabled. This feature is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_A_CR1_LOA</name>
                                    <description>Interrupt. A CR1 load due to a PWMn_CAP1 event will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>2</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-1</dimIndex>
                    <name>CR[%s]</name>
                    <displayName>CR[%s]</displayName>
                    <description>PWM Control Register. Enables PWM outputs and selects either single
                        edge or double edge controlled PWM outputs.</description>
                    <addressOffset>0x02C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>PWMSEL2</name>
                            <description>PWM[2] output single/double edge mode control.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMSEL3</name>
                            <description>PWM[3] output edge control.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMSEL4</name>
                            <description>PWM[4] output edge control.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMSEL5</name>
                            <description>PWM[5] output edge control.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMSEL6</name>
                            <description>PWM[6] output edge control.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[8:7]</bitRange>
                        </field>
                        <field>
                            <name>PWMENA1</name>
                            <description>PWM[1] output enable control.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA2</name>
                            <description>PWM[2] output enable control.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA3</name>
                            <description>PWM[3] output enable control.</description>
                            <bitRange>[11:11]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA4</name>
                            <description>PWM[4] output enable control.</description>
                            <bitRange>[12:12]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA5</name>
                            <description>PWM[5] output enable control.</description>
                            <bitRange>[13:13]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA6</name>
                            <description>PWM[6] output enable control. See PWMENA1 for details.</description>
                            <bitRange>[14:14]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused, always zero.</description>
                            <bitRange>[31:15]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>4-6</dimIndex>
                    <name>MR%s</name>
                    <description>Match Register. Match registers are continuously compared to the
                        PWM counter in order to control PWM output edges.</description>
                    <addressOffset>0x040</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MATCH</name>
                            <description>Timer counter match value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PCR</name>
                    <description>PWM Control Register. Enables PWM outputs and selects either single
                        edge or double edge controlled PWM outputs.</description>
                    <addressOffset>0x04C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>PWMSEL2</name>
                            <description>PWM[2] output single/double edge mode control.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMSEL3</name>
                            <description>PWM[3] output edge control.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMSEL4</name>
                            <description>PWM[4] output edge control.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMSEL5</name>
                            <description>PWM[5] output edge control.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMSEL6</name>
                            <description>PWM[6] output edge control.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SINGLE_EDGE_CONTROLL</name>
                                    <description>Single edge controlled mode is selected.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DOUBLE_EDGE_CONTROLL</name>
                                    <description>Double edge controlled mode is selected.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[8:7]</bitRange>
                        </field>
                        <field>
                            <name>PWMENA1</name>
                            <description>PWM[1] output enable control.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA2</name>
                            <description>PWM[2] output enable control.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA3</name>
                            <description>PWM[3] output enable control.</description>
                            <bitRange>[11:11]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA4</name>
                            <description>PWM[4] output enable control.</description>
                            <bitRange>[12:12]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA5</name>
                            <description>PWM[5] output enable control.</description>
                            <bitRange>[13:13]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PWMENA6</name>
                            <description>PWM[6] output enable control. See PWMENA1 for details.</description>
                            <bitRange>[14:14]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_DI</name>
                                    <description>The PWM output is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_PWM_OUTPUT_IS_EN</name>
                                    <description>The PWM output is enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused, always zero.</description>
                            <bitRange>[31:15]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>LER</name>
                    <description>Load Enable Register. Enables use of updated PWM match values.</description>
                    <addressOffset>0x050</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MAT0LATCHEN</name>
                            <description>Enable PWM Match 0 Latch. PWM MR0 register update control.
                                Writing a one to this bit allows the last value written to the PWM
                                Match Register 0 to be become effective when the timer is next reset
                                by a PWM Match event. See Section 27.6.7.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>MAT1LATCHEN</name>
                            <description>Enable PWM Match 1 Latch. PWM MR1 register update control.
                                See bit 0 for details.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>MAT2LATCHEN</name>
                            <description>Enable PWM Match 2 Latch. PWM MR2 register update control.
                                See bit 0 for details.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>MAT3LATCHEN</name>
                            <description>Enable PWM Match 3 Latch. PWM MR3 register update control.
                                See bit 0 for details.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>MAT4LATCHEN</name>
                            <description>Enable PWM Match 4 Latch. PWM MR4 register update control.
                                See bit 0 for details.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>MAT5LATCHEN</name>
                            <description>Enable PWM Match 5 Latch. PWM MR5 register update control.
                                See bit 0 for details.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>MAT6LATCHEN</name>
                            <description>Enable PWM Match 6 Latch. PWM MR6 register update control.
                                See bit 0 for details.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:7]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CTCR</name>
                    <description>Count Control Register. The CTCR selects between Timer and Counter
                        mode, and in Counter mode selects the signal and edge(s) for counting.</description>
                    <addressOffset>0x070</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MOD</name>
                            <description>Counter/ Timer Mode</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TIMER_MODE_THE_TC_I</name>
                                    <description>Timer Mode: the TC is incremented when the Prescale
                                        Counter matches the Prescale register.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING_EDGE_COUNTER_</name>
                                    <description>Rising edge counter Mode: the TC is incremented on
                                        rising edges of the PWM_CAP input selected by bits 3:2.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING_EDGE_COUNTER</name>
                                    <description>Falling edge counter Mode: the TC is incremented on
                                        falling edges of the PWM_CAP input selected by bits 3:2.</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DUAL_EDGE_COUNTER_MO</name>
                                    <description>Dual edge counter Mode: the TC is incremented on
                                        both edges of the PWM_CAP input selected by bits 3:2.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CIS</name>
                            <description>Count Input Select. When bits 1:0 are not 00, these bits
                                select which PWM_CAP pin carries the signal used to increment the
                                TC. Other combinations are reserved.</description>
                            <bitRange>[3:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>FOR_PWM0_00_EQ_PWM0_</name>
                                    <description>For PWM0: 00 = PWM0_CAP0 (Other combinations are
                                        reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other
                                        combinations are reserved)</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>I2C0</name>
            <description>I2C bus interface</description>
            <groupName>I2C</groupName>
            <baseAddress>0x4001C000</baseAddress>
            <addressBlock>
                <offset>0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>I2C0</name>
                <value>10</value>
            </interrupt>
            <registers>
                <register>
                    <name>CONSET</name>
                    <description>I2C Control Set Register. When a one is written to a bit of this
                        register, the corresponding bit in the I2C control register is set. Writing
                        a zero has no effect on the corresponding bit in the I2C control register.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. User software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>AA</name>
                            <description>Assert acknowledge flag.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>SI</name>
                            <description>I2C interrupt flag.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>STO</name>
                            <description>STOP flag.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>STA</name>
                            <description>START flag.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>I2EN</name>
                            <description>I2C interface enable.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:7]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>STAT</name>
                    <description>I2C Status Register. During I2C operation, this register provides
                        detailed status codes that allow software to determine the next action
                        needed.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-only</access>
                    <resetValue>0xF8</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>These bits are unused and are always 0.</description>
                            <bitRange>[2:0]</bitRange>
                        </field>
                        <field>
                            <name>Status</name>
                            <description>These bits give the actual status information about the I
                                2C interface.</description>
                            <bitRange>[7:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DAT</name>
                    <description>I2C Data Register. During master or slave transmit mode, data to be
                        transmitted is written to this register. During master or slave receive
                        mode, data that has been received may be read from this register.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>Data</name>
                            <description>This register holds data values that have been received or
                                are to be transmitted.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ADR0</name>
                    <description>I2C Slave Address Register 0. Contains the 7-bit slave address for
                        operation of the I2C interface in slave mode, and is not used in master
                        mode. The least significant bit determines whether a slave responds to the
                        General Call address.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>GC</name>
                            <description>General Call enable bit.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>Address</name>
                            <description>The I2C device address for slave mode.</description>
                            <bitRange>[7:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SCLH</name>
                    <description>SCH Duty Cycle Register High Half Word. Determines the high time of
                        the I2C clock.</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x04</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SCLH</name>
                            <description>Count for SCL HIGH time period selection.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SCLL</name>
                    <description>SCL Duty Cycle Register Low Half Word. Determines the low time of
                        the I2C clock. SCLL and SCLH together determine the clock frequency
                        generated by an I2C master and certain times used in slave mode.</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x04</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SCLL</name>
                            <description>Count for SCL low time period selection.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CONCLR</name>
                    <description>I2C Control Clear Register. When a one is written to a bit of this
                        register, the corresponding bit in the I2C control register is cleared.
                        Writing a zero has no effect on the corresponding bit in the I2C control
                        register.</description>
                    <addressOffset>0x018</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. User software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>AAC</name>
                            <description>Assert acknowledge Clear bit.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>SIC</name>
                            <description>I2C interrupt Clear bit.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. User software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>STAC</name>
                            <description>START flag Clear bit.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>I2ENC</name>
                            <description>I2C interface Disable bit.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. User software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MMCTRL</name>
                    <description>Monitor mode control register.</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MM_ENA</name>
                            <description>Monitor mode enable.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MONITOR_MODE_DISABLE</name>
                                    <description>Monitor mode disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_I_2C_MODULE_WILL</name>
                                    <description>The I 2C module will enter monitor mode. In this
                                        mode the SDA output will be forced high. This will prevent
                                        the I2C module from outputting data of any kind (including
                                        ACK) onto the I2C data bus. Depending on the state of the
                                        ENA_SCL bit, the output may be also forced high, preventing
                                        the module from having control over the I2C clock line.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ENA_SCL</name>
                            <description>SCL output enable.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>WHEN_THIS_BIT_IS_CLE</name>
                                    <description>When this bit is cleared to 0, the SCL output will
                                        be forced high when the module is in monitor mode. As
                                        described above, this will prevent the module from having
                                        any control over the I2C clock line.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>WHEN_THIS_BIT_IS_SET</name>
                                    <description>When this bit is set, the I2C module may exercise
                                        the same control over the clock line that it would in normal
                                        operation. This means that, acting as a slave peripheral,
                                        the I2C module can stretch the clock line (hold it low)
                                        until it has had time to respond to an I2C interrupt.[1]</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MATCH_ALL</name>
                            <description>Select interrupt register match.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>WHEN_THIS_BIT_IS_CLE</name>
                                    <description>When this bit is cleared, an interrupt will only be
                                        generated when a match occurs to one of the (up-to) four
                                        address registers described above. That is, the module will
                                        respond as a normal slave as far as address-recognition is
                                        concerned.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>WHEN_THIS_BIT_IS_SET</name>
                                    <description>When this bit is set to 1 and the I2C is in monitor
                                        mode, an interrupt will be generated on ANY address
                                        received. This will enable the part to monitor all traffic
                                        on the bus.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from reserved bits is not defined.</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>1-3</dimIndex>
                    <name>ADR%s</name>
                    <description>I2C Slave Address Register. Contains the 7-bit slave address for
                        operation of the I2C interface in slave mode, and is not used in master
                        mode. The least significant bit determines whether a slave responds to the
                        General Call address.</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>GC</name>
                            <description>General Call enable bit.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>Address</name>
                            <description>The I2C device address for slave mode.</description>
                            <bitRange>[7:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DATA_BUFFER</name>
                    <description>Data buffer register. The contents of the 8 MSBs of the DAT shift
                        register will be transferred to the DATA_BUFFER automatically after every
                        nine bits (8 bits of data plus ACK or NACK) has been received on the bus.</description>
                    <addressOffset>0x02C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>Data</name>
                            <description>This register holds contents of the 8 MSBs of the DAT shift
                                register.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>4</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-3</dimIndex>
                    <name>MASK[%s]</name>
                    <displayName>MASK[%s]</displayName>
                    <description>I2C Slave address mask register</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. User software should not write ones to reserved
                                bits. This bit reads always back as 0.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>MASK</name>
                            <description>Mask bits.</description>
                            <bitRange>[7:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>SPI</name>
            <description>SPI </description>
            <groupName>SPI</groupName>
            <baseAddress>0x40020000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>SPI</name>
                <value>13</value>
            </interrupt>
            <registers>
                <register>
                    <name>CR</name>
                    <description>SPI Control Register. This register controls the operation of the
                        SPI.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>BITENABLE</name>
                            <description>The SPI controller sends and receives 8 bits of data per
                                transfer.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_SPI_CONTROLLER_S</name>
                                    <description>The SPI controller sends and receives the number of
                                        bits selected by bits 11:8.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CPHA</name>
                            <description>Clock phase control determines the relationship between the
                                data and the clock on SPI transfers, and controls when a slave
                                transfer is defined as starting and ending.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>FIRST_EDGE</name>
                                    <description>Data is sampled on the first clock edge of SCK. A
                                        transfer starts and ends with activation and deactivation of
                                        the SSEL signal.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SECOND_EDGE</name>
                                    <description>Data is sampled on the second clock edge of the
                                        SCK. A transfer starts with the first clock edge, and ends
                                        with the last sampling edge when the SSEL signal is active.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CPOL</name>
                            <description>Clock polarity control.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SCK_IS_ACTIVE_HIGH_</name>
                                    <description>SCK is active high.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SCK_IS_ACTIVE_LOW_</name>
                                    <description>SCK is active low.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MSTR</name>
                            <description>Master mode select.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SLAVE</name>
                                    <description>The SPI operates in Slave mode.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MASTER</name>
                                    <description>The SPI operates in Master mode.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>LSBF</name>
                            <description>LSB First controls which direction each byte is shifted
                                when transferred.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MSB</name>
                                    <description>SPI data is transferred MSB (bit 7) first.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>LSB</name>
                                    <description>SPI data is transferred LSB (bit 0) first.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SPIE</name>
                            <description>Serial peripheral interrupt enable.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTBLOCK</name>
                                    <description>SPI interrupts are inhibited.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>HWINT</name>
                                    <description>A hardware interrupt is generated each time the
                                        SPIF or MODF bits are activated.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>BITS</name>
                            <description>When bit 2 of this register is 1, this field controls the
                                number of bits per transfer:</description>
                            <bitRange>[11:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>8_BITS_PER_TRANSFER</name>
                                    <description>8 bits per transfer</description>
                                    <value>0x8</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>9_BITS_PER_TRANSFER</name>
                                    <description>9 bits per transfer</description>
                                    <value>0x9</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>10_BITS_PER_TRANSFER</name>
                                    <description>10 bits per transfer</description>
                                    <value>0xA</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>11_BITS_PER_TRANSFER</name>
                                    <description>11 bits per transfer</description>
                                    <value>0xB</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>12_BITS_PER_TRANSFER</name>
                                    <description>12 bits per transfer</description>
                                    <value>0xC</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>13_BITS_PER_TRANSFER</name>
                                    <description>13 bits per transfer</description>
                                    <value>0xD</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>14_BITS_PER_TRANSFER</name>
                                    <description>14 bits per transfer</description>
                                    <value>0xE</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>15_BITS_PER_TRANSFER</name>
                                    <description>15 bits per transfer</description>
                                    <value>0xF</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>16_BITS_PER_TRANSFER</name>
                                    <description>16 bits per transfer</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SR</name>
                    <description>SPI Status Register. This register shows the status of the SPI.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[2:0]</bitRange>
                        </field>
                        <field>
                            <name>ABRT</name>
                            <description>Slave abort. When 1, this bit indicates that a slave abort
                                has occurred. This bit is cleared by reading this register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>MODF</name>
                            <description>Mode fault. when 1, this bit indicates that a Mode fault
                                error has occurred. This bit is cleared by reading this register,
                                then writing the SPI0 control register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>ROVR</name>
                            <description>Read overrun. When 1, this bit indicates that a read
                                overrun has occurred. This bit is cleared by reading this register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>WCOL</name>
                            <description>Write collision. When 1, this bit indicates that a write
                                collision has occurred. This bit is cleared by reading this
                                register, then accessing the SPI Data Register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>SPIF</name>
                            <description>SPI transfer complete flag. When 1, this bit indicates when
                                a SPI data transfer is complete. When a master, this bit is set at
                                the end of the last cycle of the transfer. When a slave, this bit is
                                set on the last data sampling edge of the SCK. This bit is cleared
                                by first reading this register, then accessing the SPI Data
                                Register. Note: this is not the SPI interrupt flag. This flag is
                                found in the SPINT register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DR</name>
                    <description>SPI Data Register. This bi-directional register provides the
                        transmit and receive data for the SPI. Transmit data is provided to the SPI0
                        by writing to this register. Data received by the SPI0 can be read from this
                        register.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <readAction>modify</readAction>
                    <fields>
                        <field>
                            <name>DATALOW</name>
                            <description>SPI Bi-directional data port.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>DATAHIGH</name>
                            <description>If bit 2 of the SPCR is 1 and bits 11:8 are other than
                                1000, some or all of these bits contain the additional transmit and
                                receive bits. When less than 16 bits are selected, the more
                                significant among these bits read as zeroes.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CCR</name>
                    <description>SPI Clock Counter Register. This register controls the frequency of
                        a master's SCK0.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>COUNTER</name>
                            <description>SPI0 Clock counter setting.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INT</name>
                    <description>SPI Interrupt Flag. This register contains the interrupt flag for
                        the SPI interface.</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SPIF</name>
                            <description>SPI interrupt flag. Set by the SPI interface to generate an
                                interrupt. Cleared by writing a 1 to this bit. Note: this bit will
                                be set once when SPIE = 1 and at least one of SPIF and WCOL bits is
                                1. However, only when the SPI Interrupt bit is set and SPI0
                                Interrupt is enabled in the NVIC, SPI based interrupt can be
                                processed by interrupt handling software.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[7:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>RTC</name>
            <description> Real Time Clock (RTC) </description>
            <groupName>RTC</groupName>
            <baseAddress>0x40024000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>RTC</name>
                <value>17</value>
            </interrupt>
            <registers>
                <register>
                    <name>ILR</name>
                    <description>Interrupt Location Register</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RTCCIF</name>
                            <description>When one, the Counter Increment Interrupt block generated
                                an interrupt. Writing a one to this bit location clears the counter
                                increment interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RTCALF</name>
                            <description>When one, the alarm registers generated an interrupt.
                                Writing a one to this bit location clears the alarm interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:21]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CCR</name>
                    <description>Clock Control Register</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>CLKEN</name>
                            <description>Clock Enable.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_TIME_COUNTERS_AR</name>
                                    <description>The time counters are enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_TIME_COUNTERS_AR</name>
                                    <description>The time counters are disabled so that they may be
                                        initialized.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CTCRST</name>
                            <description>CTC Reset.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>When one, the elements in the internal oscillator
                                        divider are reset, and remain reset until CCR[1] is changed
                                        to zero. This is the divider that generates the 1 Hz clock
                                        from the 32.768 kHz crystal. The state of the divider is not
                                        visible to software.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NO_EFFECT_</name>
                                    <description>No effect.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Internal test mode controls. These bits must be 0 for
                                normal RTC operation.</description>
                            <bitRange>[3:2]</bitRange>
                        </field>
                        <field>
                            <name>CCALEN</name>
                            <description>Calibration counter enable.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_CALIBRATION_COUN</name>
                                    <description>The calibration counter is disabled and reset to
                                        zero.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_CALIBRATION_COUN</name>
                                    <description>The calibration counter is enabled and counting,
                                        using the 1 Hz clock. When the calibration counter is equal
                                        to the value of the CALIBRATION register, the counter resets
                                        and repeats counting up to the value of the CALIBRATION
                                        register. See Section 30.6.4.2 and Section 30.6.5.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CIIR</name>
                    <description>Counter Increment Interrupt Register</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>IMSEC</name>
                            <description>When 1, an increment of the Second value generates an
                                interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>IMMIN</name>
                            <description>When 1, an increment of the Minute value generates an
                                interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>IMHOUR</name>
                            <description>When 1, an increment of the Hour value generates an
                                interrupt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>IMDOM</name>
                            <description>When 1, an increment of the Day of Month value generates an
                                interrupt.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>IMDOW</name>
                            <description>When 1, an increment of the Day of Week value generates an
                                interrupt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>IMDOY</name>
                            <description>When 1, an increment of the Day of Year value generates an
                                interrupt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>IMMON</name>
                            <description>When 1, an increment of the Month value generates an
                                interrupt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>IMYEAR</name>
                            <description>When 1, an increment of the Year value generates an
                                interrupt.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>AMR</name>
                    <description>Alarm Mask Register</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>AMRSEC</name>
                            <description>When 1, the Second value is not compared for the alarm.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>AMRMIN</name>
                            <description>When 1, the Minutes value is not compared for the alarm.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>AMRHOUR</name>
                            <description>When 1, the Hour value is not compared for the alarm.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>AMRDOM</name>
                            <description>When 1, the Day of Month value is not compared for the
                                alarm.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>AMRDOW</name>
                            <description>When 1, the Day of Week value is not compared for the
                                alarm.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>AMRDOY</name>
                            <description>When 1, the Day of Year value is not compared for the
                                alarm.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>AMRMON</name>
                            <description>When 1, the Month value is not compared for the alarm.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>AMRYEAR</name>
                            <description>When 1, the Year value is not compared for the alarm.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CTIME0</name>
                    <description>Consolidated Time Register 0</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>SECONDS</name>
                            <description>Seconds value in the range of 0 to 59</description>
                            <bitRange>[5:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[7:6]</bitRange>
                        </field>
                        <field>
                            <name>MINUTES</name>
                            <description>Minutes value in the range of 0 to 59</description>
                            <bitRange>[13:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[15:14]</bitRange>
                        </field>
                        <field>
                            <name>HOURS</name>
                            <description>Hours value in the range of 0 to 23</description>
                            <bitRange>[20:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[23:21]</bitRange>
                        </field>
                        <field>
                            <name>DOW</name>
                            <description>Day of week value in the range of 0 to 6</description>
                            <bitRange>[26:24]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:27]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CTIME1</name>
                    <description>Consolidated Time Register 1</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DOM</name>
                            <description>Day of month value in the range of 1 to 28, 29, 30, or 31
                                (depending on the month and whether it is a leap year).</description>
                            <bitRange>[4:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[7:5]</bitRange>
                        </field>
                        <field>
                            <name>MONTH</name>
                            <description>Month value in the range of 1 to 12.</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[15:12]</bitRange>
                        </field>
                        <field>
                            <name>YEAR</name>
                            <description>Year value in the range of 0 to 4095.</description>
                            <bitRange>[27:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:28]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CTIME2</name>
                    <description>Consolidated Time Register 2</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DOY</name>
                            <description>Day of year value in the range of 1 to 365 (366 for leap
                                years).</description>
                            <bitRange>[11:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SEC</name>
                    <description>Seconds Counter</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>SECONDS</name>
                            <description>Seconds value in the range of 0 to 59</description>
                            <bitRange>[5:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MIN</name>
                    <description>Minutes Register</description>
                    <addressOffset>0x024</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>MINUTES</name>
                            <description>Minutes value in the range of 0 to 59</description>
                            <bitRange>[5:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>HRS</name>
                    <description>Hours Register</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>HOURS</name>
                            <description>Hours value in the range of 0 to 23</description>
                            <bitRange>[4:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DOM</name>
                    <description>Day of Month Register</description>
                    <addressOffset>0x02C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DOM</name>
                            <description>Day of month value in the range of 1 to 28, 29, 30, or 31
                                (depending on the month and whether it is a leap year).</description>
                            <bitRange>[4:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DOW</name>
                    <description>Day of Week Register</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DOW</name>
                            <description>Day of week value in the range of 0 to 6.</description>
                            <bitRange>[2:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DOY</name>
                    <description>Day of Year Register</description>
                    <addressOffset>0x034</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DOY</name>
                            <description>Day of year value in the range of 1 to 365 (366 for leap
                                years).</description>
                            <bitRange>[8:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:9]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MONTH</name>
                    <description>Months Register</description>
                    <addressOffset>0x038</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>MONTH</name>
                            <description>Month value in the range of 1 to 12.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>YEAR</name>
                    <description>Years Register</description>
                    <addressOffset>0x03C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>YEAR</name>
                            <description>Year value in the range of 0 to 4095.</description>
                            <bitRange>[11:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CALIBRATION</name>
                    <description>Calibration Value Register</description>
                    <addressOffset>0x040</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>CALVAL</name>
                            <description>If enabled, the calibration counter counts up to this
                                value. The maximum value is 131, 072 corresponding to about 36.4
                                hours. Calibration is disabled if CALVAL = 0.</description>
                            <bitRange>[16:0]</bitRange>
                        </field>
                        <field>
                            <name>CALDIR</name>
                            <description>Calibration direction</description>
                            <bitRange>[17:17]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>BACKWARD_CALIBRATION</name>
                                    <description>Backward calibration. When CALVAL is equal to the
                                        calibration counter, the RTC timers will stop incrementing
                                        for 1 second.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FORWARD_CALIBRATION_</name>
                                    <description>Forward calibration. When CALVAL is equal to the
                                        calibration counter, the RTC timers will jump by 2 seconds.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>5</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-4</dimIndex>
                    <name>GPREG%s</name>
                    <description>General Purpose Register 0</description>
                    <addressOffset>0x044</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>GP</name>
                            <description>General purpose storage.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RTC_AUX</name>
                    <description>RTC Auxiliary control register</description>
                    <addressOffset>0x05C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x10</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>RTC_OSCF</name>
                            <description>RTC Oscillator Fail detect flag. Read: this bit is set if
                                the RTC oscillator stops, and when RTC power is first turned on. An
                                interrupt will occur when this bit is set, the RTC_OSCFEN bit in
                                RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC.
                                Write: writing a 1 to this bit clears the flag.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RTC_PDOUT</name>
                            <description>When 0: the RTC_ALARM pin reflects the RTC alarm status.
                                When 1: the RTC_ALARM pin indicates Deep Power-down mode.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:7]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RTC_AUXEN</name>
                    <description>RTC Auxiliary Enable register</description>
                    <addressOffset>0x058</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>RTC_OSCFEN</name>
                            <description>Oscillator Fail Detect interrupt enable. When 0: the RTC
                                Oscillator Fail detect interrupt is disabled. When 1: the RTC
                                Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ASEC</name>
                    <description>Alarm value for Seconds</description>
                    <addressOffset>0x060</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>SECONDS</name>
                            <description>Seconds value in the range of 0 to 59</description>
                            <bitRange>[5:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>AMIN</name>
                    <description>Alarm value for Minutes</description>
                    <addressOffset>0x64</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>MINUTES</name>
                            <description>Minutes value in the range of 0 to 59</description>
                            <bitRange>[5:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>AHRS</name>
                    <description>Alarm value for Hours</description>
                    <addressOffset>0x068</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>HOURS</name>
                            <description>Hours value in the range of 0 to 23</description>
                            <bitRange>[4:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ADOM</name>
                    <description>Alarm value for Day of Month</description>
                    <addressOffset>0x06C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DOM</name>
                            <description>Day of month value in the range of 1 to 28, 29, 30, or 31
                                (depending on the month and whether it is a leap year).</description>
                            <bitRange>[4:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ADOW</name>
                    <description>Alarm value for Day of Week</description>
                    <addressOffset>0x070</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DOW</name>
                            <description>Day of week value in the range of 0 to 6.</description>
                            <bitRange>[2:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ADOY</name>
                    <description>Alarm value for Day of Year</description>
                    <addressOffset>0x074</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DOY</name>
                            <description>Day of year value in the range of 1 to 365 (366 for leap
                                years).</description>
                            <bitRange>[8:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:9]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>AMON</name>
                    <description>Alarm value for Months</description>
                    <addressOffset>0x078</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>MONTH</name>
                            <description>Month value in the range of 1 to 12.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>AYRS</name>
                    <description>Alarm value for Year</description>
                    <addressOffset>0x07C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>YEAR</name>
                            <description>Year value in the range of 0 to 4095.</description>
                            <bitRange>[11:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>GPIOINT</name>
            <description>GPIO</description>
            <groupName>GPIOINT</groupName>
            <!-- change this to base address 0x40028080 to be backwards compatible  WHY???? -->
            <baseAddress>0x40028080</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <registers>
                <register>
                    <name>STATUS</name>
                    <description>GPIO overall Interrupt Status.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>P0INT</name>
                            <description>Port 0 GPIO interrupt pending.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_PENDING_INTERRUPT</name>
                                    <description>No pending interrupts on Port 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>AT_LEAST_ONE_PENDING</name>
                                    <description>At least one pending interrupt on Port 0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>P2INT</name>
                            <description>Port 2 GPIO interrupt pending.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_PENDING_INTERRUPT</name>
                                    <description>No pending interrupts on Port 2.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>AT_LEAST_ONE_PENDING</name>
                                    <description>At least one pending interrupt on Port 2.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <cluster>
                    <dim>2</dim>
                    <dimIncrement>0x20</dimIncrement>
                    <dimIndex>0-2</dimIndex>
                    <name>PORT[%s]</name>
                    <description>GPIO interrupt registers</description>
                    <headerStructName>int_port</headerStructName>
                    <addressOffset>0x4</addressOffset>
                    <access>read-write</access>
                    <register>
                        <name>STATR</name>
                        <description>GPIO Interrupt Status for Rising edge for Port 0.</description>
                        <addressOffset>0x000</addressOffset>
                        <access>read-only</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>P_0REI</name>
                                <description>Status of Rising Edge Interrupt for P[0]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[0:0]</bitRange>
                            </field>
                            <field>
                                <name>P_1REI</name>
                                <description>Status of Rising Edge Interrupt for P[1]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[1:1]</bitRange>
                            </field>
                            <field>
                                <name>P_2REI</name>
                                <description>Status of Rising Edge Interrupt for P[2]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[2:2]</bitRange>
                            </field>
                            <field>
                                <name>P_3REI</name>
                                <description>Status of Rising Edge Interrupt for P[3]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[3:3]</bitRange>
                            </field>
                            <field>
                                <name>P_4REI</name>
                                <description>Status of Rising Edge Interrupt for P[4]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[4:4]</bitRange>
                            </field>
                            <field>
                                <name>P_5REI</name>
                                <description>Status of Rising Edge Interrupt for P[5]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[5:5]</bitRange>
                            </field>
                            <field>
                                <name>P_6REI</name>
                                <description>Status of Rising Edge Interrupt for P[6]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[6:6]</bitRange>
                            </field>
                            <field>
                                <name>P_7REI</name>
                                <description>Status of Rising Edge Interrupt for P[7]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[7:7]</bitRange>
                            </field>
                            <field>
                                <name>P_8REI</name>
                                <description>Status of Rising Edge Interrupt for P[8]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[8:8]</bitRange>
                            </field>
                            <field>
                                <name>P_9REI</name>
                                <description>Status of Rising Edge Interrupt for P[9]. 0 = No rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[9:9]</bitRange>
                            </field>
                            <field>
                                <name>P_10REI</name>
                                <description>Status of Rising Edge Interrupt for P[10]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[10:10]</bitRange>
                            </field>
                            <field>
                                <name>P_11REI</name>
                                <description>Status of Rising Edge Interrupt for P[11]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[11:11]</bitRange>
                            </field>
                            <field>
                                <name>P_12REI</name>
                                <description>Status of Rising Edge Interrupt for P[12]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[12:12]</bitRange>
                            </field>
                            <field>
                                <name>P_13REI</name>
                                <description>Status of Rising Edge Interrupt for P[13]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[13:13]</bitRange>
                            </field>
                            <field>
                                <name>P_14REI</name>
                                <description>Status of Rising Edge Interrupt for P[14]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[14:14]</bitRange>
                            </field>
                            <field>
                                <name>P_15REI</name>
                                <description>Status of Rising Edge Interrupt for P[15]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[15:15]</bitRange>
                            </field>
                            <field>
                                <name>P_16REI</name>
                                <description>Status of Rising Edge Interrupt for P[16]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[16:16]</bitRange>
                            </field>
                            <field>
                                <name>P_17REI</name>
                                <description>Status of Rising Edge Interrupt for P[17]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[17:17]</bitRange>
                            </field>
                            <field>
                                <name>P_18REI</name>
                                <description>Status of Rising Edge Interrupt for P[18]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[18:18]</bitRange>
                            </field>
                            <field>
                                <name>P_19REI</name>
                                <description>Status of Rising Edge Interrupt for P[19]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[19:19]</bitRange>
                            </field>
                            <field>
                                <name>P_20REI</name>
                                <description>Status of Rising Edge Interrupt for P[20]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[20:20]</bitRange>
                            </field>
                            <field>
                                <name>P_21REI</name>
                                <description>Status of Rising Edge Interrupt for P[21]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[21:21]</bitRange>
                            </field>
                            <field>
                                <name>P_22REI</name>
                                <description>Status of Rising Edge Interrupt for P[22]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[22:22]</bitRange>
                            </field>
                            <field>
                                <name>P_23REI</name>
                                <description>Status of Rising Edge Interrupt for P[23]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[23:23]</bitRange>
                            </field>
                            <field>
                                <name>P_24REI</name>
                                <description>Status of Rising Edge Interrupt for P[24]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[24:24]</bitRange>
                            </field>
                            <field>
                                <name>P_25REI</name>
                                <description>Status of Rising Edge Interrupt for P[25]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[25:25]</bitRange>
                            </field>
                            <field>
                                <name>P_26REI</name>
                                <description>Status of Rising Edge Interrupt for P[26]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[26:26]</bitRange>
                            </field>
                            <field>
                                <name>P_27REI</name>
                                <description>Status of Rising Edge Interrupt for P[27]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[27:27]</bitRange>
                            </field>
                            <field>
                                <name>P_28REI</name>
                                <description>Status of Rising Edge Interrupt for P[28]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[28:28]</bitRange>
                            </field>
                            <field>
                                <name>P_29REI</name>
                                <description>Status of Rising Edge Interrupt for P[29]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[29:29]</bitRange>
                            </field>
                            <field>
                                <name>P_30REI</name>
                                <description>Status of Rising Edge Interrupt for P[30]. 0 = No
                                    rising
                                    edge detected. 1 = Rising edge interrupt generated.</description>
                                <bitRange>[30:30]</bitRange>
                            </field>
                            <field>
                                <name>RESERVED</name>
                                <description>Reserved.</description>
                                <bitRange>[31:31]</bitRange>
                            </field>
                        </fields>
                    </register>
                    <register>
                        <name>STATF</name>
                        <description>GPIO Interrupt Status for Falling edge for Port 0.</description>
                        <addressOffset>0x004</addressOffset>
                        <access>read-only</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>P_0FEI</name>
                                <description>Status of Falling Edge Interrupt for P[0]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[0:0]</bitRange>
                            </field>
                            <field>
                                <name>P_1FEI</name>
                                <description>Status of Falling Edge Interrupt for P[1]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[1:1]</bitRange>
                            </field>
                            <field>
                                <name>P_2FEI</name>
                                <description>Status of Falling Edge Interrupt for P[2]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[2:2]</bitRange>
                            </field>
                            <field>
                                <name>P_3FEI</name>
                                <description>Status of Falling Edge Interrupt for P[3]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[3:3]</bitRange>
                            </field>
                            <field>
                                <name>P_4FEI</name>
                                <description>Status of Falling Edge Interrupt for P[4]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[4:4]</bitRange>
                            </field>
                            <field>
                                <name>P_5FEI</name>
                                <description>Status of Falling Edge Interrupt for P[5]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[5:5]</bitRange>
                            </field>
                            <field>
                                <name>P_6FEI</name>
                                <description>Status of Falling Edge Interrupt for P[6]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[6:6]</bitRange>
                            </field>
                            <field>
                                <name>P_7FEI</name>
                                <description>Status of Falling Edge Interrupt for P[7]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[7:7]</bitRange>
                            </field>
                            <field>
                                <name>P_8FEI</name>
                                <description>Status of Falling Edge Interrupt for P[8]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[8:8]</bitRange>
                            </field>
                            <field>
                                <name>P_9FEI</name>
                                <description>Status of Falling Edge Interrupt for P[9]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[9:9]</bitRange>
                            </field>
                            <field>
                                <name>P_10FEI</name>
                                <description>Status of Falling Edge Interrupt for P[10]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[10:10]</bitRange>
                            </field>
                            <field>
                                <name>P_11FEI</name>
                                <description>Status of Falling Edge Interrupt for P[11]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[11:11]</bitRange>
                            </field>
                            <field>
                                <name>P_12FEI</name>
                                <description>Status of Falling Edge Interrupt for P[12]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[12:12]</bitRange>
                            </field>
                            <field>
                                <name>P_13FEI</name>
                                <description>Status of Falling Edge Interrupt for P[13]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[13:13]</bitRange>
                            </field>
                            <field>
                                <name>P_14FEI</name>
                                <description>Status of Falling Edge Interrupt for P[14]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[14:14]</bitRange>
                            </field>
                            <field>
                                <name>P_15FEI</name>
                                <description>Status of Falling Edge Interrupt for P[15]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[15:15]</bitRange>
                            </field>
                            <field>
                                <name>P_16FEI</name>
                                <description>Status of Falling Edge Interrupt for P[16]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[16:16]</bitRange>
                            </field>
                            <field>
                                <name>P_17FEI</name>
                                <description>Status of Falling Edge Interrupt for P[17]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[17:17]</bitRange>
                            </field>
                            <field>
                                <name>P_18FEI</name>
                                <description>Status of Falling Edge Interrupt for P[18]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[18:18]</bitRange>
                            </field>
                            <field>
                                <name>P_19FEI</name>
                                <description>Status of Falling Edge Interrupt for P[19]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[19:19]</bitRange>
                            </field>
                            <field>
                                <name>P_20FEI</name>
                                <description>Status of Falling Edge Interrupt for P[20]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[20:20]</bitRange>
                            </field>
                            <field>
                                <name>P_21FEI</name>
                                <description>Status of Falling Edge Interrupt for P[21]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[21:21]</bitRange>
                            </field>
                            <field>
                                <name>P_22FEI</name>
                                <description>Status of Falling Edge Interrupt for P[22]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[22:22]</bitRange>
                            </field>
                            <field>
                                <name>P_23FEI</name>
                                <description>Status of Falling Edge Interrupt for P[23]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[23:23]</bitRange>
                            </field>
                            <field>
                                <name>P_24FEI</name>
                                <description>Status of Falling Edge Interrupt for P[24]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[24:24]</bitRange>
                            </field>
                            <field>
                                <name>P_25FEI</name>
                                <description>Status of Falling Edge Interrupt for P[25]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[25:25]</bitRange>
                            </field>
                            <field>
                                <name>P_26FEI</name>
                                <description>Status of Falling Edge Interrupt for P[26]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[26:26]</bitRange>
                            </field>
                            <field>
                                <name>P_27FEI</name>
                                <description>Status of Falling Edge Interrupt for P[27]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[27:27]</bitRange>
                            </field>
                            <field>
                                <name>P_28FEI</name>
                                <description>Status of Falling Edge Interrupt for P[28]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[28:28]</bitRange>
                            </field>
                            <field>
                                <name>P_29FEI</name>
                                <description>Status of Falling Edge Interrupt for P[29]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[29:29]</bitRange>
                            </field>
                            <field>
                                <name>P_30FEI</name>
                                <description>Status of Falling Edge Interrupt for P[30]. 0 = No
                                    falling
                                    edge detected. 1 = Falling edge interrupt generated.</description>
                                <bitRange>[30:30]</bitRange>
                            </field>
                            <field>
                                <name>RESERVED</name>
                                <description>Reserved.</description>
                                <bitRange>[31:31]</bitRange>
                            </field>
                        </fields>
                    </register>
                    <register>
                        <name>CLR</name>
                        <description>GPIO Interrupt Clear.</description>
                        <addressOffset>0x008</addressOffset>
                        <access>write-only</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>P_0CI</name>
                                <description>Clear GPIO port Interrupts for P[0]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[0:0]</bitRange>
                            </field>
                            <field>
                                <name>P_1CI</name>
                                <description>Clear GPIO port Interrupts for P[1]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[1:1]</bitRange>
                            </field>
                            <field>
                                <name>P_2CI</name>
                                <description>Clear GPIO port Interrupts for P[2]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[2:2]</bitRange>
                            </field>
                            <field>
                                <name>P_3CI</name>
                                <description>Clear GPIO port Interrupts for P[3]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[3:3]</bitRange>
                            </field>
                            <field>
                                <name>P_4CI</name>
                                <description>Clear GPIO port Interrupts for P[4]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[4:4]</bitRange>
                            </field>
                            <field>
                                <name>P_5CI</name>
                                <description>Clear GPIO port Interrupts for P[5]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[5:5]</bitRange>
                            </field>
                            <field>
                                <name>P_6CI</name>
                                <description>Clear GPIO port Interrupts for P[6]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[6:6]</bitRange>
                            </field>
                            <field>
                                <name>P_7CI</name>
                                <description>Clear GPIO port Interrupts for P[7]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[7:7]</bitRange>
                            </field>
                            <field>
                                <name>P_8CI</name>
                                <description>Clear GPIO port Interrupts for P[8]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[8:8]</bitRange>
                            </field>
                            <field>
                                <name>P_9CI</name>
                                <description>Clear GPIO port Interrupts for P[9]. 0 = No effect. 1 =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[9:9]</bitRange>
                            </field>
                            <field>
                                <name>P_10CI</name>
                                <description>Clear GPIO port Interrupts for P[10]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[10:10]</bitRange>
                            </field>
                            <field>
                                <name>P_11CI</name>
                                <description>Clear GPIO port Interrupts for P[11]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[11:11]</bitRange>
                            </field>
                            <field>
                                <name>P_12CI</name>
                                <description>Clear GPIO port Interrupts for P[12]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[12:12]</bitRange>
                            </field>
                            <field>
                                <name>P_13CI</name>
                                <description>Clear GPIO port Interrupts for P[13]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[13:13]</bitRange>
                            </field>
                            <field>
                                <name>P_14CI</name>
                                <description>Clear GPIO port Interrupts for P[14]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[14:14]</bitRange>
                            </field>
                            <field>
                                <name>P_15CI</name>
                                <description>Clear GPIO port Interrupts for P[15]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[15:15]</bitRange>
                            </field>
                            <field>
                                <name>P_16CI</name>
                                <description>Clear GPIO port Interrupts for P[16]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[16:16]</bitRange>
                            </field>
                            <field>
                                <name>P_17CI</name>
                                <description>Clear GPIO port Interrupts for P[17]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[17:17]</bitRange>
                            </field>
                            <field>
                                <name>P_18CI</name>
                                <description>Clear GPIO port Interrupts for P[18]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[18:18]</bitRange>
                            </field>
                            <field>
                                <name>P_19CI</name>
                                <description>Clear GPIO port Interrupts for P[19]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[19:19]</bitRange>
                            </field>
                            <field>
                                <name>P_20CI</name>
                                <description>Clear GPIO port Interrupts for P[20]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[20:20]</bitRange>
                            </field>
                            <field>
                                <name>P_21CI</name>
                                <description>Clear GPIO port Interrupts for P[21]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[21:21]</bitRange>
                            </field>
                            <field>
                                <name>P_22CI</name>
                                <description>Clear GPIO port Interrupts for P[22]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[22:22]</bitRange>
                            </field>
                            <field>
                                <name>P_23CI</name>
                                <description>Clear GPIO port Interrupts for P[23]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[23:23]</bitRange>
                            </field>
                            <field>
                                <name>P_24CI</name>
                                <description>Clear GPIO port Interrupts for P[24]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[24:24]</bitRange>
                            </field>
                            <field>
                                <name>P_25CI</name>
                                <description>Clear GPIO port Interrupts for P[25]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[25:25]</bitRange>
                            </field>
                            <field>
                                <name>P_26CI</name>
                                <description>Clear GPIO port Interrupts for P[26]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[26:26]</bitRange>
                            </field>
                            <field>
                                <name>P_27CI</name>
                                <description>Clear GPIO port Interrupts for P[27]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[27:27]</bitRange>
                            </field>
                            <field>
                                <name>P_28CI</name>
                                <description>Clear GPIO port Interrupts for P[28]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[28:28]</bitRange>
                            </field>
                            <field>
                                <name>P_29CI</name>
                                <description>Clear GPIO port Interrupts for P[29]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[29:29]</bitRange>
                            </field>
                            <field>
                                <name>P_30CI</name>
                                <description>Clear GPIO port Interrupts for P[30]. 0 = No effect. 1
                                    =
                                    Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
                                <bitRange>[30:30]</bitRange>
                            </field>
                            <field>
                                <name>RESERVED</name>
                                <description>Reserved.</description>
                                <bitRange>[31:31]</bitRange>
                            </field>
                        </fields>
                    </register>
                    <register>
                        <name>ENR</name>
                        <description>GPIO Interrupt Enable for Rising edge for Port 0.</description>
                        <addressOffset>0x00C</addressOffset>
                        <access>read-write</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>P_0ER</name>
                                <description>Enable rising edge interrupt for P[0]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[0:0]</bitRange>
                            </field>
                            <field>
                                <name>P_1ER</name>
                                <description>Enable rising edge interrupt for P[1]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[1:1]</bitRange>
                            </field>
                            <field>
                                <name>P_2ER</name>
                                <description>Enable rising edge interrupt for P[2]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[2:2]</bitRange>
                            </field>
                            <field>
                                <name>P_3ER</name>
                                <description>Enable rising edge interrupt for P[3]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[3:3]</bitRange>
                            </field>
                            <field>
                                <name>P_4ER</name>
                                <description>Enable rising edge interrupt for P[4]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[4:4]</bitRange>
                            </field>
                            <field>
                                <name>P_5ER</name>
                                <description>Enable rising edge interrupt for P[5]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[5:5]</bitRange>
                            </field>
                            <field>
                                <name>P_6ER</name>
                                <description>Enable rising edge interrupt for P[6]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[6:6]</bitRange>
                            </field>
                            <field>
                                <name>P_7ER</name>
                                <description>Enable rising edge interrupt for P[7]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[7:7]</bitRange>
                            </field>
                            <field>
                                <name>P_8ER</name>
                                <description>Enable rising edge interrupt for P[8]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[8:8]</bitRange>
                            </field>
                            <field>
                                <name>P_9ER</name>
                                <description>Enable rising edge interrupt for P[9]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[9:9]</bitRange>
                            </field>
                            <field>
                                <name>P_10ER</name>
                                <description>Enable rising edge interrupt for P[10]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[10:10]</bitRange>
                            </field>
                            <field>
                                <name>P_11ER</name>
                                <description>Enable rising edge interrupt for P[11]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[11:11]</bitRange>
                            </field>
                            <field>
                                <name>P_12ER</name>
                                <description>Enable rising edge interrupt for P[12]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[12:12]</bitRange>
                            </field>
                            <field>
                                <name>P_13ER</name>
                                <description>Enable rising edge interrupt for P[13]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[13:13]</bitRange>
                            </field>
                            <field>
                                <name>P_14ER</name>
                                <description>Enable rising edge interrupt for P[14]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[14:14]</bitRange>
                            </field>
                            <field>
                                <name>P_15ER</name>
                                <description>Enable rising edge interrupt for P[15]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[15:15]</bitRange>
                            </field>
                            <field>
                                <name>P_16ER</name>
                                <description>Enable rising edge interrupt for P[16]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[16:16]</bitRange>
                            </field>
                            <field>
                                <name>P_17ER</name>
                                <description>Enable rising edge interrupt for P[17]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[17:17]</bitRange>
                            </field>
                            <field>
                                <name>P_18ER</name>
                                <description>Enable rising edge interrupt for P[18]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[18:18]</bitRange>
                            </field>
                            <field>
                                <name>P_19ER</name>
                                <description>Enable rising edge interrupt for P[19]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[19:19]</bitRange>
                            </field>
                            <field>
                                <name>P_20ER</name>
                                <description>Enable rising edge interrupt for P[20]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[20:20]</bitRange>
                            </field>
                            <field>
                                <name>P_21ER</name>
                                <description>Enable rising edge interrupt for P[21]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[21:21]</bitRange>
                            </field>
                            <field>
                                <name>P_22ER</name>
                                <description>Enable rising edge interrupt for P[22]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[22:22]</bitRange>
                            </field>
                            <field>
                                <name>P_23ER</name>
                                <description>Enable rising edge interrupt for P[23]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[23:23]</bitRange>
                            </field>
                            <field>
                                <name>P_24ER</name>
                                <description>Enable rising edge interrupt for P[24]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[24:24]</bitRange>
                            </field>
                            <field>
                                <name>P_25ER</name>
                                <description>Enable rising edge interrupt for P[25]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[25:25]</bitRange>
                            </field>
                            <field>
                                <name>P_26ER</name>
                                <description>Enable rising edge interrupt for P[26]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[26:26]</bitRange>
                            </field>
                            <field>
                                <name>P_27ER</name>
                                <description>Enable rising edge interrupt for P[27]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[27:27]</bitRange>
                            </field>
                            <field>
                                <name>P_28ER</name>
                                <description>Enable rising edge interrupt for P[28]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[28:28]</bitRange>
                            </field>
                            <field>
                                <name>P_29ER</name>
                                <description>Enable rising edge interrupt for P[29]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[29:29]</bitRange>
                            </field>
                            <field>
                                <name>P_30ER</name>
                                <description>Enable rising edge interrupt for P[30]. 0 = Disable
                                    rising
                                    edge interrupt. 1 = Enable rising edge interrupt.</description>
                                <bitRange>[30:30]</bitRange>
                            </field>
                            <field>
                                <name>RESERVED</name>
                                <description>Reserved.</description>
                                <bitRange>[31:31]</bitRange>
                            </field>
                        </fields>
                    </register>
                    <register>
                        <name>ENF</name>
                        <description>GPIO Interrupt Enable for Falling edge for Port 0.</description>
                        <addressOffset>0x010</addressOffset>
                        <access>read-write</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>P_0EF</name>
                                <description>Enable falling edge interrupt for P[0]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[0:0]</bitRange>
                            </field>
                            <field>
                                <name>P_1EF</name>
                                <description>Enable falling edge interrupt for P[1]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[1:1]</bitRange>
                            </field>
                            <field>
                                <name>P_2EF</name>
                                <description>Enable falling edge interrupt for P[2]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[2:2]</bitRange>
                            </field>
                            <field>
                                <name>P_3EF</name>
                                <description>Enable falling edge interrupt for P[3]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[3:3]</bitRange>
                            </field>
                            <field>
                                <name>P_4EF</name>
                                <description>Enable falling edge interrupt for P[4]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[4:4]</bitRange>
                            </field>
                            <field>
                                <name>P_5EF</name>
                                <description>Enable falling edge interrupt for P[5]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[5:5]</bitRange>
                            </field>
                            <field>
                                <name>P_6EF</name>
                                <description>Enable falling edge interrupt for P[6]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[6:6]</bitRange>
                            </field>
                            <field>
                                <name>P_7EF</name>
                                <description>Enable falling edge interrupt for P[7]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[7:7]</bitRange>
                            </field>
                            <field>
                                <name>P_8EF</name>
                                <description>Enable falling edge interrupt for P[8]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[8:8]</bitRange>
                            </field>
                            <field>
                                <name>P_9EF</name>
                                <description>Enable falling edge interrupt for P[9]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[9:9]</bitRange>
                            </field>
                            <field>
                                <name>P_10EF</name>
                                <description>Enable falling edge interrupt for P[10]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[10:10]</bitRange>
                            </field>
                            <field>
                                <name>P_11EF</name>
                                <description>Enable falling edge interrupt for P[11]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[11:11]</bitRange>
                            </field>
                            <field>
                                <name>P_12EF</name>
                                <description>Enable falling edge interrupt for P[12]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[12:12]</bitRange>
                            </field>
                            <field>
                                <name>P_13EF</name>
                                <description>Enable falling edge interrupt for P[13]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[13:13]</bitRange>
                            </field>
                            <field>
                                <name>P_14EF</name>
                                <description>Enable falling edge interrupt for P[14]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[14:14]</bitRange>
                            </field>
                            <field>
                                <name>P_15EF</name>
                                <description>Enable falling edge interrupt for P[15]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[15:15]</bitRange>
                            </field>
                            <field>
                                <name>P_16EF</name>
                                <description>Enable falling edge interrupt for P[16]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[16:16]</bitRange>
                            </field>
                            <field>
                                <name>P_17EF</name>
                                <description>Enable falling edge interrupt for P[17]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[17:17]</bitRange>
                            </field>
                            <field>
                                <name>P_18EF</name>
                                <description>Enable falling edge interrupt for P[18]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[18:18]</bitRange>
                            </field>
                            <field>
                                <name>P_19EF</name>
                                <description>Enable falling edge interrupt for P[19]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[19:19]</bitRange>
                            </field>
                            <field>
                                <name>P_20EF</name>
                                <description>Enable falling edge interrupt for P[20]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[20:20]</bitRange>
                            </field>
                            <field>
                                <name>P_21EF</name>
                                <description>Enable falling edge interrupt for P[21]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[21:21]</bitRange>
                            </field>
                            <field>
                                <name>P_22EF</name>
                                <description>Enable falling edge interrupt for P[22]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[22:22]</bitRange>
                            </field>
                            <field>
                                <name>P_23EF</name>
                                <description>Enable falling edge interrupt for P[23]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[23:23]</bitRange>
                            </field>
                            <field>
                                <name>P_24EF</name>
                                <description>Enable falling edge interrupt for P[24]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[24:24]</bitRange>
                            </field>
                            <field>
                                <name>P_25EF</name>
                                <description>Enable falling edge interrupt for P[25]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[25:25]</bitRange>
                            </field>
                            <field>
                                <name>P_26EF</name>
                                <description>Enable falling edge interrupt for P[26]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[26:26]</bitRange>
                            </field>
                            <field>
                                <name>P_27EF</name>
                                <description>Enable falling edge interrupt for P[27]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[27:27]</bitRange>
                            </field>
                            <field>
                                <name>P_28EF</name>
                                <description>Enable falling edge interrupt for P[28]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[28:28]</bitRange>
                            </field>
                            <field>
                                <name>P_29EF</name>
                                <description>Enable falling edge interrupt for P[29]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[29:29]</bitRange>
                            </field>
                            <field>
                                <name>P_30EF</name>
                                <description>Enable falling edge interrupt for P[30]. 0 = Disable
                                    falling edge interrupt. 1 = Enable falling edge interrupt.</description>
                                <bitRange>[30:30]</bitRange>
                            </field>
                            <field>
                                <name>RESERVED</name>
                                <description>Reserved.</description>
                                <bitRange>[31:31]</bitRange>
                            </field>
                        </fields>
                    </register>
                </cluster>
            </registers>
        </peripheral>
        <peripheral>
            <name>PINCONNECT</name>
            <description>Pin connect block</description>
            <baseAddress>0x4002C000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <registers>
                <register>
                    <dim>11</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-11</dimIndex>
                    <name>PINSEL[%s]</name>
                    <displayName>PINSEL[%s]</displayName>
                    <description>Pin function select register %s.</description>
                    <addressOffset>0x0</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields></fields>
                </register>
                <register>
                    <dim>10</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-10</dimIndex>
                    <name>PINMODE[%s]</name>
                    <displayName>PINMODE[%s]</displayName>
                    <description>Pin mode select register %s.</description>
                    <addressOffset>0x040</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields></fields>
                </register>
                <register>
                    <dim>5</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-5</dimIndex>
                    <name>PINMODE_OD[%s]</name>
                    <displayName>PINMODE_OD[%s]</displayName>
                    <description>Open drain mode control register %s.</description>
                    <addressOffset>0x068</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields></fields>
                </register>
                <register>
                    <name>I2CPADCFG</name>
                    <description>I2C Pin Configuration register</description>
                    <addressOffset>0x07C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SDADRV0</name>
                            <description>Drive mode control for the SDA0 pin, P0.27.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>STANDARD</name>
                                    <description>Standard. The SDA0 pin is in the standard drive
                                        mode.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FAST_MODE_PLUS</name>
                                    <description>Fast-mode plus. The SDA0 pin is in Fast Mode Plus
                                        drive mode.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SDAI2C0</name>
                            <description>I 2C filter mode control for the SDA0 pin, P0.27.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLED</name>
                                    <description>Enabled. The SDA0 pin has I2C glitch filtering and
                                        slew rate control enabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled. The SDA0 pin has I2C glitch filtering and
                                        slew rate control disabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SCLDRV0</name>
                            <description>Drive mode control for the SCL0 pin, P0.28.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>STANDARD</name>
                                    <description>Standard. The SCL0 pin is in the standard drive
                                        mode.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FAST_MODE_PLUS</name>
                                    <description>Fast-mode plus. The SCL0 pin is in Fast Mode Plus
                                        drive mode.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SCLI2C0</name>
                            <description>I 2C filter mode control for the SCL0 pin, P0.28.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ENABLED</name>
                                    <description>Enabled. The SCL0 pin has I2C glitch filtering and
                                        slew rate control enabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled. The SCL0 pin has I2C glitch filtering and
                                        slew rate control disabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>SSP0</name>
            <description>SSP0 controller</description>
            <baseAddress>0x40088000</baseAddress>
            <addressBlock>
                <offset>0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>SSP0</name>
                <value>14</value>
            </interrupt>
            <registers>
                <register>
                    <name>CR0</name>
                    <description>Control Register 0. Selects the serial clock rate, bus type, and
                        data size.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DSS</name>
                            <description>Data Size Select. This field controls the number of bits
                                transferred in each frame. Values 0000-0010 are not supported and
                                should not be used.</description>
                            <bitRange>[3:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>4_BIT_TRANSFER</name>
                                    <description>4-bit transfer</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>5_BIT_TRANSFER</name>
                                    <description>5-bit transfer</description>
                                    <value>0x4</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>6_BIT_TRANSFER</name>
                                    <description>6-bit transfer</description>
                                    <value>0x5</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>7_BIT_TRANSFER</name>
                                    <description>7-bit transfer</description>
                                    <value>0x6</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>8_BIT_TRANSFER</name>
                                    <description>8-bit transfer</description>
                                    <value>0x7</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>9_BIT_TRANSFER</name>
                                    <description>9-bit transfer</description>
                                    <value>0x8</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>10_BIT_TRANSFER</name>
                                    <description>10-bit transfer</description>
                                    <value>0x9</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>11_BIT_TRANSFER</name>
                                    <description>11-bit transfer</description>
                                    <value>0xA</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>12_BIT_TRANSFER</name>
                                    <description>12-bit transfer</description>
                                    <value>0xB</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>13_BIT_TRANSFER</name>
                                    <description>13-bit transfer</description>
                                    <value>0xC</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>14_BIT_TRANSFER</name>
                                    <description>14-bit transfer</description>
                                    <value>0xD</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>15_BIT_TRANSFER</name>
                                    <description>15-bit transfer</description>
                                    <value>0xE</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>16_BIT_TRANSFER</name>
                                    <description>16-bit transfer</description>
                                    <value>0xF</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>FRF</name>
                            <description>Frame Format.</description>
                            <bitRange>[5:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SPI</name>
                                    <description>SPI</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TI</name>
                                    <description>TI</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MICROWIRE</name>
                                    <description>Microwire</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THIS_COMBINATION_IS_</name>
                                    <description>This combination is not supported and should not be
                                        used.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CPOL</name>
                            <description>Clock Out Polarity. This bit is only used in SPI mode.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>BUS_LOW</name>
                                    <description>SSP controller maintains the bus clock low between
                                        frames.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>BUS_HIGH</name>
                                    <description>SSP controller maintains the bus clock high between
                                        frames.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CPHA</name>
                            <description>Clock Out Phase. This bit is only used in SPI mode.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>FIRST_CLOCK</name>
                                    <description>SSP controller captures serial data on the first
                                        clock transition of the frame, that is, the transition away
                                        from the inter-frame state of the clock line.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SECOND_CLOCK</name>
                                    <description>SSP controller captures serial data on the second
                                        clock transition of the frame, that is, the transition back
                                        to the inter-frame state of the clock line.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SCR</name>
                            <description>Serial Clock Rate. The number of prescaler-output clocks
                                per bit on the bus, minus one. Given that CPSDVSR is the prescale
                                divider, and the APB clock PCLK clocks the prescaler, the bit
                                frequency is PCLK / (CPSDVSR X [SCR+1]).</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CR1</name>
                    <description>Control Register 1. Selects master/slave and other modes.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>LBM</name>
                            <description>Loop Back Mode.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NORMAL</name>
                                    <description>During normal operation.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>OUPTU</name>
                                    <description>Serial input is taken from the serial output (MOSI
                                        or MISO) rather than the serial input pin (MISO or MOSI
                                        respectively).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SSE</name>
                            <description>SSP Enable.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>The SSP controller is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED</name>
                                    <description>The SSP controller will interact with other devices
                                        on the serial bus. Software should write the appropriate
                                        control information to the other SSP registers and interrupt
                                        controller registers, before setting this bit.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MS</name>
                            <description>Master/Slave Mode.This bit can only be written when the SSE
                                bit is 0.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MASTER</name>
                                    <description>The SSP controller acts as a master on the bus,
                                        driving the SCLK, MOSI, and SSEL lines and receiving the
                                        MISO line.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SLAVE</name>
                                    <description>The SSP controller acts as a slave on the bus,
                                        driving MISO line and receiving SCLK, MOSI, and SSEL lines.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SOD</name>
                            <description>Slave Output Disable. This bit is relevant only in slave
                                mode (MS = 1). If it is 1, this blocks this SSP controller from
                                driving the transmit data line (MISO).</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DR</name>
                    <description>Data Register. Writes fill the transmit FIFO, and reads empty the
                        receive FIFO.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <readAction>modify</readAction>
                    <fields>
                        <field>
                            <name>DATA</name>
                            <description>Write: software can write data to be sent in a future frame
                                to this register whenever the TNF bit in the Status register is 1,
                                indicating that the Tx FIFO is not full. If the Tx FIFO was
                                previously empty and the SSP controller is not busy on the bus,
                                transmission of the data will begin immediately. Otherwise the data
                                written to this register will be sent as soon as all previous data
                                has been sent (and received). If the data length is less than 16
                                bits, software must right-justify the data written to this register.
                                Read: software can read data from this register whenever the RNE bit
                                in the Status register is 1, indicating that the Rx FIFO is not
                                empty. When software reads this register, the SSP controller returns
                                data from the least recent frame in the Rx FIFO. If the data length
                                is less than 16 bits, the data is right-justified in this field with
                                higher order bits filled with 0s.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SR</name>
                    <description>Status Register</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x00000003</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TFE</name>
                            <description>Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is
                                empty, 0 if not.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TNF</name>
                            <description>Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is
                                full, 1 if not.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RNE</name>
                            <description>Receive FIFO Not Empty. This bit is 0 if the Receive FIFO
                                is empty, 1 if not.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RFF</name>
                            <description>Receive FIFO Full. This bit is 1 if the Receive FIFO is
                                full, 0 if not.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>BSY</name>
                            <description>Busy. This bit is 0 if the SSPn controller is idle, or 1 if
                                it is currently sending/receiving a frame and/or the Tx FIFO is not
                                empty.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CPSR</name>
                    <description>Clock Prescale Register</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CPSDVSR</name>
                            <description>This even value between 2 and 254, by which PCLK is divided
                                to yield the prescaler output clock. Bit 0 always reads as 0.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IMSC</name>
                    <description>Interrupt Mask Set and Clear Register</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RORIM</name>
                            <description>Software should set this bit to enable interrupt when a
                                Receive Overrun occurs, that is, when the Rx FIFO is full and
                                another frame is completely received. The ARM spec implies that the
                                preceding frame data is overwritten by the new frame data when this
                                occurs.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RTIM</name>
                            <description>Software should set this bit to enable interrupt when a
                                Receive Time-out condition occurs. A Receive Time-out occurs when
                                the Rx FIFO is not empty, and no has not been read for a time-out
                                period. The time-out period is the same for master and slave modes
                                and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X
                                [SCR+1]).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RXIM</name>
                            <description>Software should set this bit to enable interrupt when the
                                Rx FIFO is at least half full.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>TXIM</name>
                            <description>Software should set this bit to enable interrupt when the
                                Tx FIFO is at least half empty.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RIS</name>
                    <description>Raw Interrupt Status Register</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x00000008</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RORRIS</name>
                            <description>This bit is 1 if another frame was completely received
                                while the RxFIFO was full. The ARM spec implies that the preceding
                                frame data is overwritten by the new frame data when this occurs.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RTRIS</name>
                            <description>This bit is 1 if the Rx FIFO is not empty, and has not been
                                read for a time-out period. The time-out period is the same for
                                master and slave modes and is determined by the SSP bit rate: 32
                                bits at PCLK / (CPSDVSR X [SCR+1]).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RXRIS</name>
                            <description>This bit is 1 if the Rx FIFO is at least half full.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>TXRIS</name>
                            <description>This bit is 1 if the Tx FIFO is at least half empty.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MIS</name>
                    <description>Masked Interrupt Status Register</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RORMIS</name>
                            <description>This bit is 1 if another frame was completely received
                                while the RxFIFO was full, and this interrupt is enabled.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RTMIS</name>
                            <description>This bit is 1 if the Rx FIFO is not empty, has not been
                                read for a time-out period, and this interrupt is enabled. The
                                time-out period is the same for master and slave modes and is
                                determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X
                                [SCR+1]).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RXMIS</name>
                            <description>This bit is 1 if the Rx FIFO is at least half full, and
                                this interrupt is enabled.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>TXMIS</name>
                            <description>This bit is 1 if the Tx FIFO is at least half empty, and
                                this interrupt is enabled.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ICR</name>
                    <description>SSPICR Interrupt Clear Register</description>
                    <addressOffset>0x020</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>RORIC</name>
                            <description>Writing a 1 to this bit clears the frame was received when
                                RxFIFO was full interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RTIC</name>
                            <description>Writing a 1 to this bit clears the Rx FIFO was not empty
                                and has not been read for a time-out period interrupt. The time-out
                                period is the same for master and slave modes and is determined by
                                the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DMACR</name>
                    <description>SSP0 DMA control register</description>
                    <addressOffset>0x024</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXDMAE</name>
                            <description>Receive DMA Enable. When this bit is set to one 1, DMA for
                                the receive FIFO is enabled, otherwise receive DMA is disabled.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TXDMAE</name>
                            <description>Transmit DMA Enable. When this bit is set to one 1, DMA for
                                the transmit FIFO is enabled, otherwise transmit DMA is disabled</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>ADC</name>
            <description>Analog-to-Digital Converter (ADC) </description>
            <groupName>ADC</groupName>
            <baseAddress>0x40034000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>ADC</name>
                <value>22</value>
            </interrupt>
            <registers>
                <register>
                    <name>CR</name>
                    <description>A/D Control Register. The ADCR register must be written to select
                        the operating mode before A/D conversion can occur.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>SEL</name>
                            <description>Selects which of the AD0[7:0] pins is (are) to be sampled
                                and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects
                                pin AD0[7]. In software-controlled mode, only one of these bits
                                should be 1. In hardware scan mode, any value containing 1 to 8 ones
                                is allowed. All zeroes is equivalent to 0x01.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>CLKDIV</name>
                            <description>The APB clock (PCLK) is divided by (this value plus one) to
                                produce the clock for the A/D converter, which should be less than
                                or equal to 12.4 MHz. Typically, software should program the
                                smallest value in this field that yields a clock of 12.4 MHz or
                                slightly less, but in certain cases (such as a high-impedance analog
                                source) a slower clock may be desirable.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>BURST</name>
                            <description>Burst mode</description>
                            <bitRange>[16:16]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>BURST</name>
                                    <description>The AD converter does repeated conversions at up to
                                        400 kHz, scanning (if necessary) through the pins selected
                                        by bits set to ones in the SEL field. The first conversion
                                        after the start corresponds to the least-significant 1 in
                                        the SEL field, then higher numbered 1-bits (pins) if
                                        applicable. Repeated conversions can be terminated by
                                        clearing this bit, but the conversion that's in progress
                                        when this bit is cleared will be completed. START bits must
                                        be 000 when BURST = 1 or conversions will not start.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SW</name>
                                    <description>Conversions are software controlled and require 31
                                        clocks.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[20:17]</bitRange>
                        </field>
                        <field>
                            <name>PDN</name>
                            <description>Power down mode</description>
                            <bitRange>[21:21]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>POWERED</name>
                                    <description>The A/D converter is operational.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>POWERDOWN</name>
                                    <description>The A/D converter is in power-down mode.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[23:22]</bitRange>
                        </field>
                        <field>
                            <name>START</name>
                            <description>When the BURST bit is 0, these bits control whether and
                                when an A/D conversion is started:</description>
                            <bitRange>[26:24]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_START_THIS_VALUE</name>
                                    <description>No start (this value should be used when clearing
                                        PDN to 0).</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>START_CONVERSION_NOW</name>
                                    <description>Start conversion now.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>P2_10</name>
                                    <description>Start conversion when the edge selected by bit 27
                                        occurs on the P2[10] pin.</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>P1_27</name>
                                    <description>Start conversion when the edge selected by bit 27
                                        occurs on the P1[27] pin.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MAT0_1</name>
                                    <description>Start conversion when the edge selected by bit 27
                                        occurs on MAT0.1. Note that this does not require that the
                                        MAT0.1 function appear on a device pin.</description>
                                    <value>0x4</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MAT0_3</name>
                                    <description>Start conversion when the edge selected by bit 27
                                        occurs on MAT0.3. Note that it is not possible to cause the
                                        MAT0.3 function to appear on a device pin.</description>
                                    <value>0x5</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MAT1_0</name>
                                    <description>Start conversion when the edge selected by bit 27
                                        occurs on MAT1.0. Note that this does not require that the
                                        MAT1.0 function appear on a device pin.</description>
                                    <value>0x6</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MAT1_1</name>
                                    <description>Start conversion when the edge selected by bit 27
                                        occurs on MAT1.1. Note that this does not require that the
                                        MAT1.1 function appear on a device pin.</description>
                                    <value>0x7</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EDGE</name>
                            <description>This bit is significant only when the START field contains
                                010-111. In these cases:</description>
                            <bitRange>[27:27]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>FALLLING</name>
                                    <description>Start conversion on a falling edge on the selected
                                        CAP/MAT signal.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>Start conversion on a rising edge on the selected
                                        CAP/MAT signal.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:28]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>GDR</name>
                    <description>A/D Global Data Register. This register contains the ADC's DONE bit
                        and the result of the most recent A/D conversion.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>RESULT</name>
                            <description>When DONE is 1, this field contains a binary fraction
                                representing the voltage on the AD0[n] pin selected by the SEL
                                field, as it falls within the range of VREFP to VSS. Zero in the
                                field indicates that the voltage on the input pin was less than,
                                equal to, or close to that on VSS, while 0xFFF indicates that the
                                voltage on the input was close to, equal to, or greater than that on
                                VREFP.</description>
                            <bitRange>[15:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[23:16]</bitRange>
                        </field>
                        <field>
                            <name>CHN</name>
                            <description>These bits contain the channel from which the RESULT bits
                                were converted (e.g. 000 identifies channel 0, 001 channel 1...).</description>
                            <bitRange>[26:24]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[29:27]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN</name>
                            <description>This bit is 1 in burst mode if the results of one or more
                                conversions was (were) lost and overwritten before the conversion
                                that produced the result in the RESULT bits. This bit is cleared by
                                reading this register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>DONE</name>
                            <description>This bit is set to 1 when an A/D conversion completes. It
                                is cleared when this register is read and when the ADCR is written.
                                If the ADCR is written while a conversion is still in progress, this
                                bit is set and a new conversion is started.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTEN</name>
                    <description>A/D Interrupt Enable Register. This register contains enable bits
                        that allow the DONE flag of each A/D channel to be included or excluded from
                        contributing to the generation of an A/D interrupt.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x100</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ADINTEN0</name>
                            <description>Interrupt enable</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Completion of a conversion on ADC channel 0 will
                                        not generate an interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>Completion of a conversion on ADC channel 0 will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ADINTEN1</name>
                            <description>Interrupt enable</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Completion of a conversion on ADC channel 1 will
                                        not generate an interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>Completion of a conversion on ADC channel 1 will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ADINTEN2</name>
                            <description>Interrupt enable</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Completion of a conversion on ADC channel 2 will
                                        not generate an interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>Completion of a conversion on ADC channel 2 will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ADINTEN3</name>
                            <description>Interrupt enable</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Completion of a conversion on ADC channel 3 will
                                        not generate an interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>Completion of a conversion on ADC channel 3 will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ADINTEN4</name>
                            <description>Interrupt enable</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Completion of a conversion on ADC channel 4 will
                                        not generate an interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>Completion of a conversion on ADC channel 4 will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ADINTEN5</name>
                            <description>Interrupt enable</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Completion of a conversion on ADC channel 5 will
                                        not generate an interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>Completion of a conversion on ADC channel 5 will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ADINTEN6</name>
                            <description>Interrupt enable</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Completion of a conversion on ADC channel 6 will
                                        not generate an interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>Completion of a conversion on ADC channel 6 will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ADINTEN7</name>
                            <description>Interrupt enable</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Completion of a conversion on ADC channel 7 will
                                        not generate an interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>Completion of a conversion on ADC channel 7 will
                                        generate an interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ADGINTEN</name>
                            <description>Interrupt enable</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CHANNELS</name>
                                    <description>Only the individual ADC channels enabled by
                                        ADINTEN7:0 will generate interrupts.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>GLOBAL</name>
                                    <description>The global DONE flag in ADDR is enabled to generate
                                        an interrupt in addition to any individual ADC channels that
                                        are enabled to generate interrupts.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:9]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>8</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-7</dimIndex>
                    <name>DR[%s]</name>
                    <displayName>DR[%s]</displayName>
                    <description>A/D Channel 0 Data Register. This register contains the result of
                        the most recent conversion completed on channel 0.</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>RESULT</name>
                            <description>When DONE is 1, this field contains a binary fraction
                                representing the voltage on the AD0[n] pin, as it falls within the
                                range of VREFP to V SS. Zero in the field indicates that the voltage
                                on the input pin was less than, equal to, or close to that on VSS,
                                while 0xFFF indicates that the voltage on the input was close to,
                                equal to, or greater than that on VREFP.</description>
                            <bitRange>[15:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[29:16]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN</name>
                            <description>This bit is 1 in burst mode if the results of one or more
                                conversions was (were) lost and overwritten before the conversion
                                that produced the result in the RESULT bits.This bit is cleared by
                                reading this register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>DONE</name>
                            <description>This bit is set to 1 when an A/D conversion completes. It
                                is cleared when this register is read.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>STAT</name>
                    <description>A/D Status Register. This register contains DONE and OVERRUN flags
                        for all of the A/D channels, as well as the A/D interrupt/DMA flag.</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DONE0</name>
                            <description>This bit mirrors the DONE status flag from the result
                                register for A/D channel 0.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>DONE1</name>
                            <description>This bit mirrors the DONE status flag from the result
                                register for A/D channel 1.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>DONE2</name>
                            <description>This bit mirrors the DONE status flag from the result
                                register for A/D channel 2.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DONE3</name>
                            <description>This bit mirrors the DONE status flag from the result
                                register for A/D channel 3.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>DONE4</name>
                            <description>This bit mirrors the DONE status flag from the result
                                register for A/D channel 4.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>DONE5</name>
                            <description>This bit mirrors the DONE status flag from the result
                                register for A/D channel 5.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>DONE6</name>
                            <description>This bit mirrors the DONE status flag from the result
                                register for A/D channel 6.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>DONE7</name>
                            <description>This bit mirrors the DONE status flag from the result
                                register for A/D channel 7.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN0</name>
                            <description>This bit mirrors the OVERRRUN status flag from the result
                                register for A/D channel 0.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN1</name>
                            <description>This bit mirrors the OVERRRUN status flag from the result
                                register for A/D channel 1.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN2</name>
                            <description>This bit mirrors the OVERRRUN status flag from the result
                                register for A/D channel 2.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN3</name>
                            <description>This bit mirrors the OVERRRUN status flag from the result
                                register for A/D channel 3.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN4</name>
                            <description>This bit mirrors the OVERRRUN status flag from the result
                                register for A/D channel 4.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN5</name>
                            <description>This bit mirrors the OVERRRUN status flag from the result
                                register for A/D channel 5.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN6</name>
                            <description>This bit mirrors the OVERRRUN status flag from the result
                                register for A/D channel 6.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>OVERRUN7</name>
                            <description>This bit mirrors the OVERRRUN status flag from the result
                                register for A/D channel 7.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>ADINT</name>
                            <description>This bit is the A/D interrupt flag. It is one when any of
                                the individual A/D channel Done flags is asserted and enabled to
                                contribute to the A/D interrupt via the ADINTEN register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:17]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TRM</name>
                    <description>ADC trim register.</description>
                    <addressOffset>0x034</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>ADCOFFS</name>
                            <description>Offset trim bits for ADC operation. Initialized by the boot
                                code. Can be overwritten by the user.</description>
                            <bitRange>[7:4]</bitRange>
                        </field>
                        <field>
                            <name>TRIM</name>
                            <description>written-to by boot code. Can not be overwritten by the
                                user. These bits are locked after boot code write.</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>CANAFRAM</name>
            <description>CAN acceptance filter RAM</description>
            <baseAddress>0x40038000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <registers>
                <register>
                    <dim>512</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-511</dimIndex>
                    <name>MASK[%s]</name>
                    <displayName>MASK[%s]</displayName>
                    <description>CAN AF ram access register</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>MASK</name>
                            <description>CAN AF RAM mask</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>CANAF</name>
            <description> CAN controller acceptance filter </description>
            <groupName>CANAF</groupName>
            <baseAddress>0x4003C000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <registers>
                <register>
                    <name>AFMR</name>
                    <description>Acceptance Filter Register</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>ACCOFF</name>
                            <description>if AccBP is 0, the Acceptance Filter is not operational.
                                All Rx messages on all CAN buses are ignored.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>ACCBP</name>
                            <description>All Rx messages are accepted on enabled CAN controllers.
                                Software must set this bit before modifying the contents of any of
                                the registers described below, and before modifying the contents of
                                Lookup Table RAM in any way other than setting or clearing Disable
                                bits in Standard Identifier entries. When both this bit and AccOff
                                are 0, the Acceptance filter operates to screen received CAN
                                Identifiers.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EFCAN</name>
                            <description>FullCAN mode</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SOFTWARE_MUST_READ_A</name>
                                    <description>Software must read all messages for all enabled IDs
                                        on all enabled CAN buses, from the receiving CAN
                                        controllers.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_ACCEPTANCE_FILTE</name>
                                    <description>The Acceptance Filter itself will take care of
                                        receiving and storing messages for selected Standard ID
                                        values on selected CAN buses. See Section 21.16 FullCAN mode
                                        on page 576.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SFF_SA</name>
                    <description>Standard Frame Individual Start Address Register</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>SFF_SA</name>
                            <description>The start address of the table of individual Standard
                                Identifiers in AF Lookup RAM. If the table is empty, write the same
                                value in this register and the SFF_GRP_sa register described below.
                                For compatibility with possible future devices, write zeroes in bits
                                31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1,
                                this value also indicates the size of the table of Standard IDs
                                which the Acceptance Filter will search and (if found) automatically
                                store received messages in Acceptance Filter RAM.</description>
                            <bitRange>[10:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:11]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SFF_GRP_SA</name>
                    <description>Standard Frame Group Start Address Register</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>SFF_GRP_SA</name>
                            <description>The start address of the table of grouped Standard
                                Identifiers in AF Lookup RAM. If the table is empty, write the same
                                value in this register and the EFF_sa register described below. The
                                largest value that should be written to this register is 0x800, when
                                only the Standard Individual table is used, and the last word
                                (address 0x7FC) in AF Lookup Table RAM is used. For compatibility
                                with possible future devices, please write zeroes in bits 31:12 and
                                1:0 of this register.</description>
                            <bitRange>[11:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EFF_SA</name>
                    <description>Extended Frame Start Address Register</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>EFF_SA</name>
                            <description>The start address of the table of individual Extended
                                Identifiers in AF Lookup RAM. If the table is empty, write the same
                                value in this register and the EFF_GRP_sa register described below.
                                The largest value that should be written to this register is 0x800,
                                when both Extended Tables are empty and the last word (address
                                0x7FC) in AF Lookup Table RAM is used. For compatibility with
                                possible future devices, please write zeroes in bits 31:11 and 1:0
                                of this register.</description>
                            <bitRange>[10:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:11]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EFF_GRP_SA</name>
                    <description>Extended Frame Group Start Address Register</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>EFF_GRP_SA</name>
                            <description>The start address of the table of grouped Extended
                                Identifiers in AF Lookup RAM. If the table is empty, write the same
                                value in this register and the ENDofTable register described below.
                                The largest value that should be written to this register is 0x800,
                                when this table is empty and the last word (address 0x7FC) in AF
                                Lookup Table RAM is used. For compatibility with possible future
                                devices, please write zeroes in bits 31:12 and 1:0 of this register.</description>
                            <bitRange>[11:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ENDOFTABLE</name>
                    <description>End of AF Tables register</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>ENDOFTABLE</name>
                            <description>The address above the last active address in the last
                                active AF table. For compatibility with possible future devices,
                                please write zeroes in bits 31:12 and 1:0 of this register. If the
                                eFCAN bit in the AFMR is 0, the largest value that should be written
                                to this register is 0x800, which allows the last word (address
                                0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the
                                AFMR is 1, this value marks the start of the area of Acceptance
                                Filter RAM, into which the Acceptance Filter will automatically
                                receive messages for selected IDs on selected CAN buses. In this
                                case, the maximum value that should be written to this register is
                                0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of
                                message storage between this address and the end of Acceptance
                                Filter RAM, for each Standard ID that is specified between the start
                                of Acceptance Filter RAM, and the next active AF table.</description>
                            <bitRange>[11:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>LUTERRAD</name>
                    <description>LUT Error Address register</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>LUTERRAD</name>
                            <description>It the LUT Error bit (below) is 1, this read-only field
                                contains the address in AF Lookup Table RAM, at which the Acceptance
                                Filter encountered an error in the content of the tables.</description>
                            <bitRange>[10:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:11]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>LUTERR</name>
                    <description>LUT Error Register</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>LUTERR</name>
                            <description>This read-only bit is set to 1 if the Acceptance Filter
                                encounters an error in the content of the tables in AF RAM. It is
                                cleared when software reads the LUTerrAd register. This condition is
                                ORed with the other CAN interrupts from the CAN controllers, to
                                produce the request that is connected to the NVIC.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:1]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FCANIE</name>
                    <description>FullCAN interrupt enable register</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FCANIE</name>
                            <description>Global FullCAN Interrupt Enable. When 1, this interrupt is
                                enabled.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:1]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FCANIC0</name>
                    <description>FullCAN interrupt and capture register0</description>
                    <addressOffset>0x024</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>INTPND</name>
                            <description>FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit
                                0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt
                                Pending bit 31.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FCANIC1</name>
                    <description>FullCAN interrupt and capture register1</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>IntPnd32</name>
                            <description>FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt
                                Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 =
                                FullCan Interrupt Pending bit 63.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>CCAN</name>
            <description>Central CAN controller </description>
            <groupName>CCAN</groupName>
            <baseAddress>0x40040000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>CANActivity</name>
                <value>34</value>
            </interrupt>
            <registers>
                <register>
                    <name>TXSR</name>
                    <description>CAN Central Transmit Status Register</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x00030300</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TS1</name>
                            <description>When 1, the CAN controller 1 is sending a message (same as
                                TS in the CAN1GSR).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TS2</name>
                            <description>When 1, the CAN controller 2 is sending a message (same as
                                TS in the CAN2GSR)</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[7:2]</bitRange>
                        </field>
                        <field>
                            <name>TBS1</name>
                            <description>When 1, all 3 Tx Buffers of the CAN1 controller are
                                available to the CPU (same as TBS in CAN1GSR).</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>TBS2</name>
                            <description>When 1, all 3 Tx Buffers of the CAN2 controller are
                                available to the CPU (same as TBS in CAN2GSR).</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[15:10]</bitRange>
                        </field>
                        <field>
                            <name>TCS1</name>
                            <description>When 1, all requested transmissions have been completed
                                successfully by the CAN1 controller (same as TCS in CAN1GSR).</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>TCS2</name>
                            <description>When 1, all requested transmissions have been completed
                                successfully by the CAN2 controller (same as TCS in CAN2GSR).</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:18]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXSR</name>
                    <description>CAN Central Receive Status Register</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RS1</name>
                            <description>When 1, CAN1 is receiving a message (same as RS in
                                CAN1GSR).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RS2</name>
                            <description>When 1, CAN2 is receiving a message (same as RS in
                                CAN2GSR).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[7:2]</bitRange>
                        </field>
                        <field>
                            <name>RB1</name>
                            <description>When 1, a received message is available in the CAN1
                                controller (same as RBS in CAN1GSR).</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>RB2</name>
                            <description>When 1, a received message is available in the CAN2
                                controller (same as RBS in CAN2GSR).</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[15:10]</bitRange>
                        </field>
                        <field>
                            <name>DOS1</name>
                            <description>When 1, a message was lost because the preceding message to
                                CAN1 controller was not read out quickly enough (same as DOS in
                                CAN1GSR).</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>DOS2</name>
                            <description>When 1, a message was lost because the preceding message to
                                CAN2 controller was not read out quickly enough (same as DOS in
                                CAN2GSR).</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:18]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MSR</name>
                    <description>CAN Central Miscellaneous Register</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>E1</name>
                            <description>When 1, one or both of the CAN1 Tx and Rx Error Counters
                                has reached the limit set in the CAN1EWL register (same as ES in
                                CAN1GSR)</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>E2</name>
                            <description>When 1, one or both of the CAN2 Tx and Rx Error Counters
                                has reached the limit set in the CAN2EWL register (same as ES in
                                CAN2GSR)</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[7:2]</bitRange>
                        </field>
                        <field>
                            <name>BS1</name>
                            <description>When 1, the CAN1 controller is currently involved in bus
                                activities (same as BS in CAN1GSR).</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>BS2</name>
                            <description>When 1, the CAN2 controller is currently involved in bus
                                activities (same as BS in CAN2GSR).</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>CAN1</name>
            <description>CAN1 controller </description>
            <groupName>CAN</groupName>
            <baseAddress>0x40044000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>CAN</name>
                <value>25</value>
            </interrupt>
            <registers>
                <register>
                    <name>MOD</name>
                    <description>Controls the operating mode of the CAN Controller.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>RM</name>
                            <description>Reset Mode.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NORMAL_THE_CAN_CONTR</name>
                                    <description>Normal.The CAN Controller is in the Operating Mode,
                                        and certain registers can not be written.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET_CAN_OPERATION</name>
                                    <description>Reset. CAN operation is disabled, writable
                                        registers can be written and the current
                                        transmission/reception of a message is aborted.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>LOM</name>
                            <description>Listen Only Mode.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NORMAL_THE_CAN_CONT</name>
                                    <description>Normal. The CAN controller acknowledges a
                                        successfully received message on the CAN bus. The error
                                        counters are stopped at the current value.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>LISTEN_ONLY_THE_CON</name>
                                    <description>Listen only. The controller gives no
                                        acknowledgment, even if a message is successfully received.
                                        Messages cannot be sent, and the controller operates in
                                        error passive mode. This mode is intended for software bit
                                        rate detection and hot plugging.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>STM</name>
                            <description>Self Test Mode.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NORMAL_A_TRANSMITTE</name>
                                    <description>Normal. A transmitted message must be acknowledged
                                        to be considered successful.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELF_TEST_THE_CONTR</name>
                                    <description>Self test. The controller will consider a Tx
                                        message successful even if there is no acknowledgment
                                        received. In this mode a full node test is possible without
                                        any other active node on the bus using the SRR bit in
                                        CANxCMR.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TPM</name>
                            <description>Transmit Priority Mode.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CAN_ID_THE_TRANSMIT</name>
                                    <description>CAN ID. The transmit priority for 3 Transmit
                                        Buffers depends on the CAN Identifier.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>LOCAL_PRIORITY_THE_</name>
                                    <description>Local priority. The transmit priority for 3
                                        Transmit Buffers depends on the contents of the Tx Priority
                                        register within the Transmit Buffer.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SM</name>
                            <description>Sleep Mode.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>WAKE_UP_NORMAL_OPER</name>
                                    <description>Wake-up. Normal operation.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SLEEP_THE_CAN_CONTR</name>
                                    <description>Sleep. The CAN controller enters Sleep Mode if no
                                        CAN interrupt is pending and there is no bus activity. See
                                        the Sleep Mode description Section 21.8.2 on page 565.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RPM</name>
                            <description>Receive Polarity Mode.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LOW_ACTIVE_RD_INPUT</name>
                                    <description>Low active. RD input is active Low (dominant bit =
                                        0).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>HIGH_ACTIVE_RD_INPU</name>
                                    <description>High active. RD input is active High (dominant bit
                                        = 1) -- reverse polarity.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TM</name>
                            <description>Test Mode.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_NORMAL_OPE</name>
                                    <description>Disabled. Normal operation.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED_THE_TD_PIN_</name>
                                    <description>Enabled. The TD pin will reflect the bit, detected
                                        on RD pin, with the next positive edge of the system clock.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CMR</name>
                    <description>Command bits that affect the state of the CAN Controller</description>
                    <addressOffset>0x004</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TR</name>
                            <description>Transmission Request.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ABSENT_NO_TRANSMISSI</name>
                                    <description>Absent.No transmission request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>PRESENT_THE_MESSAGE</name>
                                    <description>Present. The message, previously written to the
                                        CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB
                                        registers, is queued for transmission from the selected
                                        Transmit Buffer. If at two or all three of STB1, STB2 and
                                        STB3 bits are selected when TR=1 is written, Transmit Buffer
                                        will be selected based on the chosen priority scheme (for
                                        details see Section 21.5.3 Transmit Buffers (TXB))</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>AT</name>
                            <description>Abort Transmission.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_ACTION_DO_NOT_AB</name>
                                    <description>No action. Do not abort the transmission.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>PRESENT_IF_NOT_ALRE</name>
                                    <description>Present. if not already in progress, a pending
                                        Transmission Request for the selected Transmit Buffer is
                                        cancelled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RRB</name>
                            <description>Release Receive Buffer.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_ACTION_DO_NOT_RE</name>
                                    <description>No action. Do not release the receive buffer.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RELEASED_THE_INFORM</name>
                                    <description>Released. The information in the Receive Buffer
                                        (consisting of CANxRFS, CANxRID, and if applicable the
                                        CANxRDA and CANxRDB registers) is released, and becomes
                                        eligible for replacement by the next received frame. If the
                                        next received frame is not available, writing this command
                                        clears the RBS bit in the Status Register(s).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CDO</name>
                            <description>Clear Data Overrun.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_ACTION_DO_NOT_CL</name>
                                    <description>No action. Do not clear the data overrun bit.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CLEAR_THE_DATA_OVER</name>
                                    <description>Clear. The Data Overrun bit in Status Register(s)
                                        is cleared.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SRR</name>
                            <description>Self Reception Request.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ABSENT_NO_SELF_RECE</name>
                                    <description>Absent. No self reception request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>PRESENT_THE_MESSAGE</name>
                                    <description>Present. The message, previously written to the
                                        CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB
                                        registers, is queued for transmission from the selected
                                        Transmit Buffer and received simultaneously. This differs
                                        from the TR bit above in that the receiver is not disabled
                                        during the transmission, so that it receives the message if
                                        its Identifier is recognized by the Acceptance Filter.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>STB1</name>
                            <description>Select Tx Buffer 1.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NOT_SELECTED_TX_BUF</name>
                                    <description>Not selected. Tx Buffer 1 is not selected for
                                        transmission.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECTED_TX_BUFFER_</name>
                                    <description>Selected. Tx Buffer 1 is selected for transmission.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>STB2</name>
                            <description>Select Tx Buffer 2.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NOT_SELECTED_TX_BUF</name>
                                    <description>Not selected. Tx Buffer 2 is not selected for
                                        transmission.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECTED_TX_BUFFER_</name>
                                    <description>Selected. Tx Buffer 2 is selected for transmission.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>STB3</name>
                            <description>Select Tx Buffer 3.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NOT_SELECTED_TX_BUF</name>
                                    <description>Not selected. Tx Buffer 3 is not selected for
                                        transmission.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECTED_TX_BUFFER_</name>
                                    <description>Selected. Tx Buffer 3 is selected for transmission.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>GSR</name>
                    <description>Global Controller Status and Error Counters. The error counters can
                        only be written when RM in CANMOD is 1.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x3C</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RBS</name>
                            <description>Receive Buffer Status. After reading all messages and
                                releasing their memory space with the command 'Release Receive
                                Buffer,' this bit is cleared.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>EMPTY_NO_MESSAGE_IS</name>
                                    <description>Empty. No message is available.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FULL_AT_LEAST_ONE_C</name>
                                    <description>Full. At least one complete message is received by
                                        the Double Receive Buffer and available in the CANxRFS,
                                        CANxRID, and if applicable the CANxRDA and CANxRDB
                                        registers. This bit is cleared by the Release Receive Buffer
                                        command in CANxCMR, if no subsequent received message is
                                        available.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DOS</name>
                            <description>Data Overrun Status. If there is not enough space to store
                                the message within the Receive Buffer, that message is dropped and
                                the Data Overrun condition is signalled to the CPU in the moment
                                this message becomes valid. If this message is not completed
                                successfully (e.g. because of an error), no overrun condition is
                                signalled.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ABSENT_NO_DATA_OVER</name>
                                    <description>Absent. No data overrun has occurred since the last
                                        Clear Data Overrun command was given/written to CANxCMR (or
                                        since Reset).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>OVERRUN_A_MESSAGE_W</name>
                                    <description>Overrun. A message was lost because the preceding
                                        message to this CAN controller was not read and released
                                        quickly enough (there was not enough space for a new message
                                        in the Double Receive Buffer).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TBS</name>
                            <description>Transmit Buffer Status.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LOCKED_AT_LEAST_ONE</name>
                                    <description>Locked. At least one of the Transmit Buffers is not
                                        available for the CPU, i.e. at least one previously queued
                                        message for this CAN controller has not yet been sent, and
                                        therefore software should not write to the CANxTFI, CANxTID,
                                        CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RELEASED_ALL_THREE_</name>
                                    <description>Released. All three Transmit Buffers are available
                                        for the CPU. No transmit message is pending for this CAN
                                        controller (in any of the 3 Tx buffers), and software may
                                        write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB
                                        registers.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TCS</name>
                            <description>Transmit Complete Status. The Transmission Complete Status
                                bit is set '0' (incomplete) whenever the Transmission Request bit or
                                the Self Reception Request bit is set '1' at least for one of the
                                three Transmit Buffers. The Transmission Complete Status bit will
                                remain '0' until all messages are transmitted successfully.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INCOMPLETE_AT_LEAST</name>
                                    <description>Incomplete. At least one requested transmission has
                                        not been successfully completed yet.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>COMPLETE_ALL_REQUES</name>
                                    <description>Complete. All requested transmission(s) has (have)
                                        been successfully completed.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RS</name>
                            <description>Receive Status. If both the Receive Status and the Transmit
                                Status bits are '0' (idle), the CAN-Bus is idle. If both bits are
                                set, the controller is waiting to become idle again. After hardware
                                reset 11 consecutive recessive bits have to be detected until idle
                                status is reached. After Bus-off this will take 128 times of 11
                                consecutive recessive bits.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>IDLE_THE_CAN_CONTRO</name>
                                    <description>Idle. The CAN controller is idle.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RECEIVE_THE_CAN_CON</name>
                                    <description>Receive. The CAN controller is receiving a message.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TS</name>
                            <description>Transmit Status. If both the Receive Status and the
                                Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both
                                bits are set, the controller is waiting to become idle again. After
                                hardware reset 11 consecutive recessive bits have to be detected
                                until idle status is reached. After Bus-off this will take 128 times
                                of 11 consecutive recessive bits.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>IDLE_THE_CAN_CONTRO</name>
                                    <description>Idle. The CAN controller is idle.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRANSMIT_THE_CAN_CO</name>
                                    <description>Transmit. The CAN controller is sending a message.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ES</name>
                            <description>Error Status. Errors detected during reception or
                                transmission will effect the error counters according to the CAN
                                specification. The Error Status bit is set when at least one of the
                                error counters has reached or exceeded the Error Warning Limit. An
                                Error Warning Interrupt is generated, if enabled. The default value
                                of the Error Warning Limit after hardware reset is 96 decimal, see
                                also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL -
                                0x4004 4018, CAN2EWL - 0x4004 8018).</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>OK_BOTH_ERROR_COUNT</name>
                                    <description>OK. Both error counters are below the Error Warning
                                        Limit.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ERROR_ONE_OR_BOTH_O</name>
                                    <description>Error. One or both of the Transmit and Receive
                                        Error Counters has reached the limit set in the Error
                                        Warning Limit register.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>BS</name>
                            <description>Bus Status. Mode bit '1' (present) and an Error Warning
                                Interrupt is generated, if enabled. Afterwards the Transmit Error
                                Counter is set to '127', and the Receive Error Counter is cleared.
                                It will stay in this mode until the CPU clears the Reset Mode bit.
                                Once this is completed the CAN Controller will wait the minimum
                                protocol-defined time (128 occurrences of the Bus-Free signal)
                                counting down the Transmit Error Counter. After that, the Bus Status
                                bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the
                                Error Counters are reset, and an Error Warning Interrupt is
                                generated, if enabled. Reading the TX Error Counter during this time
                                gives information about the status of the Bus-Off recovery.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>BUS_ON_THE_CAN_CONT</name>
                                    <description>Bus-on. The CAN Controller is involved in bus
                                        activities</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>BUS_OFF_THE_CAN_CON</name>
                                    <description>Bus-off. The CAN controller is currently not
                                        involved/prohibited from bus activity because the Transmit
                                        Error Counter reached its limiting value of 255.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>RXERR</name>
                            <description>The current value of the Rx Error Counter (an 8-bit value).</description>
                            <bitRange>[23:16]</bitRange>
                        </field>
                        <field>
                            <name>TXERR</name>
                            <description>The current value of the Tx Error Counter (an 8-bit value).</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ICR</name>
                    <description>Interrupt status, Arbitration Lost Capture, Error Code Capture</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RI</name>
                            <description>Receive Interrupt. This bit is set whenever the RBS bit in
                                CANxSR and the RIE bit in CANxIER are both 1, indicating that a new
                                message was received and stored in the Receive Buffer. The Receive
                                Interrupt Bit is not cleared upon a read access to the Interrupt
                                Register. Giving the Command Release Receive Buffer will clear RI
                                temporarily. If there is another message available within the
                                Receive Buffer after the release command, RI is set again. Otherwise
                                RI remains cleared.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TI1</name>
                            <description>Transmit Interrupt 1. This bit is set when the TBS1 bit in
                                CANxSR goes from 0 to 1 (whenever a message out of TXB1 was
                                successfully transmitted or aborted), indicating that Transmit
                                buffer 1 is available, and the TIE1 bit in CANxIER is 1.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EI</name>
                            <description>Error Warning Interrupt. This bit is set on every change
                                (set or clear) of either the Error Status or Bus Status bit in
                                CANxSR and the EIE bit bit is set within the Interrupt Enable
                                Register at the time of the change.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DOI</name>
                            <description>Data Overrun Interrupt. This bit is set when the DOS bit in
                                CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>WUI</name>
                            <description>Wake-Up Interrupt. This bit is set if the CAN controller is
                                sleeping and bus activity is detected and the WUIE bit in CANxIER is
                                1. A Wake-Up Interrupt is also generated if the CPU tries to set the
                                Sleep bit while the CAN controller is involved in bus activities or
                                a CAN Interrupt is pending. The WUI flag can also get asserted when
                                the according enable bit WUIE is not set. In this case a Wake-Up
                                Interrupt does not get asserted.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EPI</name>
                            <description>Error Passive Interrupt. This bit is set if the EPIE bit in
                                CANxIER is 1, and the CAN controller switches between Error Passive
                                and Error Active mode in either direction. This is the case when the
                                CAN Controller has reached the Error Passive Status (at least one
                                error counter exceeds the CAN protocol defined level of 127) or if
                                the CAN Controller is in Error Passive Status and enters the Error
                                Active Status again.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ALI</name>
                            <description>Arbitration Lost Interrupt. This bit is set if the ALIE bit
                                in CANxIER is 1, and the CAN controller loses arbitration while
                                attempting to transmit. In this case the CAN node becomes a
                                receiver.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>BEI</name>
                            <description>Bus Error Interrupt -- this bit is set if the BEIE bit in
                                CANxIER is 1, and the CAN controller detects an error on the bus.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>IDI</name>
                            <description>ID Ready Interrupt -- this bit is set if the IDIE bit in
                                CANxIER is 1, and a CAN Identifier has been received (a message was
                                successfully transmitted or aborted). This bit is set whenever a
                                message was successfully transmitted or aborted and the IDIE bit is
                                set in the IER register.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TI2</name>
                            <description>Transmit Interrupt 2. This bit is set when the TBS2 bit in
                                CANxSR goes from 0 to 1 (whenever a message out of TXB2 was
                                successfully transmitted or aborted), indicating that Transmit
                                buffer 2 is available, and the TIE2 bit in CANxIER is 1.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TI3</name>
                            <description>Transmit Interrupt 3. This bit is set when the TBS3 bit in
                                CANxSR goes from 0 to 1 (whenever a message out of TXB3 was
                                successfully transmitted or aborted), indicating that Transmit
                                buffer 3 is available, and the TIE3 bit in CANxIER is 1.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET</name>
                                    <description>Set</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[15:11]</bitRange>
                        </field>
                        <field>
                            <name>ERRBIT4_0</name>
                            <description>Error Code Capture: when the CAN controller detects a bus
                                error, the location of the error within the frame is captured in
                                this field. The value reflects an internal state variable, and as a
                                result is not very linear: 00011 = Start of Frame 00010 = ID28 ...
                                ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 =
                                ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit
                                01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length
                                Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter
                                11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End
                                of Frame 10010 = Intermission Whenever a bus error occurs, the
                                corresponding bus error interrupt is forced, if enabled. At the same
                                time, the current position of the Bit Stream Processor is captured
                                into the Error Code Capture Register. The content within this
                                register is fixed until the user software has read out its content
                                once. From now on, the capture mechanism is activated again, i.e.
                                reading the CANxICR enables another Bus Error Interrupt.</description>
                            <bitRange>[20:16]</bitRange>
                        </field>
                        <field>
                            <name>ERRDIR</name>
                            <description>When the CAN controller detects a bus error, the direction
                                of the current bit is captured in this bit.</description>
                            <bitRange>[21:21]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ERROR_OCCURRED_DURIN</name>
                                    <description>Error occurred during transmitting.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ERROR_OCCURRED_DURIN</name>
                                    <description>Error occurred during receiving.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ERRC1_0</name>
                            <description>When the CAN controller detects a bus error, the type of
                                error is captured in this field:</description>
                            <bitRange>[23:22]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>BIT_ERROR</name>
                                    <description>Bit error</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FORM_ERROR</name>
                                    <description>Form error</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>STUFF_ERROR</name>
                                    <description>Stuff error</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>OTHER_ERROR</name>
                                    <description>Other error</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ALCBIT</name>
                            <description>Each time arbitration is lost while trying to send on the
                                CAN, the bit number within the frame is captured into this field.
                                After the content of ALCBIT is read, the ALI bit is cleared and a
                                new Arbitration Lost interrupt can occur. 00 = arbitration lost in
                                the first bit (MS) of identifier ... 11 = arbitration lost in SRTS
                                bit (RTR bit for standard frame messages) 12 = arbitration lost in
                                IDE bit 13 = arbitration lost in 12th bit of identifier (extended
                                frame only) ... 30 = arbitration lost in last bit of identifier
                                (extended frame only) 31 = arbitration lost in RTR bit (extended
                                frame only) On arbitration lost, the corresponding arbitration lost
                                interrupt is forced, if enabled. At that time, the current bit
                                position of the Bit Stream Processor is captured into the
                                Arbitration Lost Capture Register. The content within this register
                                is fixed until the user application has read out its contents once.
                                From now on, the capture mechanism is activated again.</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IER</name>
                    <description>Interrupt Enable</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RIE</name>
                            <description>Receiver Interrupt Enable. When the Receive Buffer Status
                                is 'full', the CAN Controller requests the respective interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TIE1</name>
                            <description>Transmit Interrupt Enable for Buffer1. When a message has
                                been successfully transmitted out of TXB1 or Transmit Buffer 1 is
                                accessible again (e.g. after an Abort Transmission command), the CAN
                                Controller requests the respective interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EIE</name>
                            <description>Error Warning Interrupt Enable. If the Error or Bus Status
                                change (see Status Register), the CAN Controller requests the
                                respective interrupt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DOIE</name>
                            <description>Data Overrun Interrupt Enable. If the Data Overrun Status
                                bit is set (see Status Register), the CAN Controller requests the
                                respective interrupt.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>WUIE</name>
                            <description>Wake-Up Interrupt Enable. If the sleeping CAN controller
                                wakes up, the respective interrupt is requested.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPIE</name>
                            <description>Error Passive Interrupt Enable. If the error status of the
                                CAN Controller changes from error active to error passive or vice
                                versa, the respective interrupt is requested.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>ALIE</name>
                            <description>Arbitration Lost Interrupt Enable. If the CAN Controller
                                has lost arbitration, the respective interrupt is requested.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>BEIE</name>
                            <description>Bus Error Interrupt Enable. If a bus error has been
                                detected, the CAN Controller requests the respective interrupt.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>IDIE</name>
                            <description>ID Ready Interrupt Enable. When a CAN identifier has been
                                received, the CAN Controller requests the respective interrupt.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>TIE2</name>
                            <description>Transmit Interrupt Enable for Buffer2. When a message has
                                been successfully transmitted out of TXB2 or Transmit Buffer 2 is
                                accessible again (e.g. after an Abort Transmission command), the CAN
                                Controller requests the respective interrupt.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>TIE3</name>
                            <description>Transmit Interrupt Enable for Buffer3. When a message has
                                been successfully transmitted out of TXB3 or Transmit Buffer 3 is
                                accessible again (e.g. after an Abort Transmission command), the CAN
                                Controller requests the respective interrupt.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:11]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>BTR</name>
                    <description>Bus Timing. Can only be written when RM in CANMOD is 1.</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x1C0000</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>BRP</name>
                            <description>Baud Rate Prescaler. The APB clock is divided by (this
                                value plus one) to produce the CAN clock.</description>
                            <bitRange>[9:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[13:10]</bitRange>
                        </field>
                        <field>
                            <name>SJW</name>
                            <description>The Synchronization Jump Width is (this value plus one) CAN
                                clocks.</description>
                            <bitRange>[15:14]</bitRange>
                        </field>
                        <field>
                            <name>TESG1</name>
                            <description>The delay from the nominal Sync point to the sample point
                                is (this value plus one) CAN clocks.</description>
                            <bitRange>[19:16]</bitRange>
                        </field>
                        <field>
                            <name>TESG2</name>
                            <description>The delay from the sample point to the next nominal sync
                                point is (this value plus one) CAN clocks. The nominal CAN bit time
                                is (this value plus the value in TSEG1 plus 3) CAN clocks.</description>
                            <bitRange>[22:20]</bitRange>
                        </field>
                        <field>
                            <name>SAM</name>
                            <description>Sampling</description>
                            <bitRange>[23:23]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_BUS_IS_SAMPLED_O</name>
                                    <description>The bus is sampled once (recommended for high speed
                                        buses)</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_BUS_IS_SAMPLED_3</name>
                                    <description>The bus is sampled 3 times (recommended for low to
                                        medium speed buses to filter spikes on the bus-line)</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EWL</name>
                    <description>Error Warning Limit. Can only be written when RM in CANMOD is 1.</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x60</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EWL</name>
                            <description>During CAN operation, this value is compared to both the Tx
                                and Rx Error Counters. If either of these counter matches this
                                value, the Error Status (ES) bit in CANSR is set.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SR</name>
                    <description>Status Register</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x3C3C3C</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RBS_1</name>
                            <description>Receive Buffer Status. This bit is identical to the RBS bit
                                in the CANxGSR.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>DOS_1</name>
                            <description>Data Overrun Status. This bit is identical to the DOS bit
                                in the CANxGSR.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>TBS1_1</name>
                            <description>Transmit Buffer Status 1.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LOCKED_SOFTWARE_CAN</name>
                                    <description>Locked. Software cannot access the Tx Buffer 1 nor
                                        write to the corresponding CANxTFI, CANxTID, CANxTDA, and
                                        CANxTDB registers because a message is either waiting for
                                        transmission or is in transmitting process.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RELEASED_SOFTWARE_M</name>
                                    <description>Released. Software may write a message into the
                                        Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and
                                        CANxTDB registers.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TCS1_1</name>
                            <description>Transmission Complete Status.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INCOMPLETE_THE_PREV</name>
                                    <description>Incomplete. The previously requested transmission
                                        for Tx Buffer 1 is not complete.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>COMPLETE_THE_PREVIO</name>
                                    <description>Complete. The previously requested transmission for
                                        Tx Buffer 1 has been successfully completed.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RS_1</name>
                            <description>Receive Status. This bit is identical to the RS bit in the
                                GSR.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>TS1_1</name>
                            <description>Transmit Status 1.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>IDLE_THERE_IS_NO_TR</name>
                                    <description>Idle. There is no transmission from Tx Buffer 1.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRANSMIT_THE_CAN_CO</name>
                                    <description>Transmit. The CAN Controller is transmitting a
                                        message from Tx Buffer 1.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ES_1</name>
                            <description>Error Status. This bit is identical to the ES bit in the
                                CANxGSR.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>BS_1</name>
                            <description>Bus Status. This bit is identical to the BS bit in the
                                CANxGSR.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RBS_2</name>
                            <description>Receive Buffer Status. This bit is identical to the RBS bit
                                in the CANxGSR.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>DOS_2</name>
                            <description>Data Overrun Status. This bit is identical to the DOS bit
                                in the CANxGSR.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>TBS2_2</name>
                            <description>Transmit Buffer Status 2.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LOCKED_SOFTWARE_CAN</name>
                                    <description>Locked. Software cannot access the Tx Buffer 2 nor
                                        write to the corresponding CANxTFI, CANxTID, CANxTDA, and
                                        CANxTDB registers because a message is either waiting for
                                        transmission or is in transmitting process.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RELEASED_SOFTWARE_M</name>
                                    <description>Released. Software may write a message into the
                                        Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and
                                        CANxTDB registers.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TCS2_2</name>
                            <description>Transmission Complete Status.</description>
                            <bitRange>[11:11]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INCOMPLETE_THE_PREV</name>
                                    <description>Incomplete. The previously requested transmission
                                        for Tx Buffer 2 is not complete.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>COMPLETE_THE_PREVIO</name>
                                    <description>Complete. The previously requested transmission for
                                        Tx Buffer 2 has been successfully completed.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RS_2</name>
                            <description>Receive Status. This bit is identical to the RS bit in the
                                GSR.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>TS2_2</name>
                            <description>Transmit Status 2.</description>
                            <bitRange>[13:13]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>IDLE_THERE_IS_NO_TR</name>
                                    <description>Idle. There is no transmission from Tx Buffer 2.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRANSMIT_THE_CAN_CO</name>
                                    <description>Transmit. The CAN Controller is transmitting a
                                        message from Tx Buffer 2.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ES_2</name>
                            <description>Error Status. This bit is identical to the ES bit in the
                                CANxGSR.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>BS_2</name>
                            <description>Bus Status. This bit is identical to the BS bit in the
                                CANxGSR.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RBS_3</name>
                            <description>Receive Buffer Status. This bit is identical to the RBS bit
                                in the CANxGSR.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>DOS_3</name>
                            <description>Data Overrun Status. This bit is identical to the DOS bit
                                in the CANxGSR.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>TBS3_3</name>
                            <description>Transmit Buffer Status 3.</description>
                            <bitRange>[18:18]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LOCKED_SOFTWARE_CAN</name>
                                    <description>Locked. Software cannot access the Tx Buffer 3 nor
                                        write to the corresponding CANxTFI, CANxTID, CANxTDA, and
                                        CANxTDB registers because a message is either waiting for
                                        transmission or is in transmitting process.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RELEASED_SOFTWARE_M</name>
                                    <description>Released. Software may write a message into the
                                        Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and
                                        CANxTDB registers.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TCS3_3</name>
                            <description>Transmission Complete Status.</description>
                            <bitRange>[19:19]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INCOMPLETE_THE_PREV</name>
                                    <description>Incomplete. The previously requested transmission
                                        for Tx Buffer 3 is not complete.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>COMPLETE_THE_PREVIO</name>
                                    <description>Complete. The previously requested transmission for
                                        Tx Buffer 3 has been successfully completed.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RS_3</name>
                            <description>Receive Status. This bit is identical to the RS bit in the
                                GSR.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>TS3_3</name>
                            <description>Transmit Status 3.</description>
                            <bitRange>[21:21]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>IDLE_THERE_IS_NO_TR</name>
                                    <description>Idle. There is no transmission from Tx Buffer 3.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TRANSMIT_THE_CAN_CO</name>
                                    <description>Transmit. The CAN Controller is transmitting a
                                        message from Tx Buffer 3.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ES_3</name>
                            <description>Error Status. This bit is identical to the ES bit in the
                                CANxGSR.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>BS_3</name>
                            <description>Bus Status. This bit is identical to the BS bit in the
                                CANxGSR.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, the value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RFS</name>
                    <description>Receive frame status. Can only be written when RM in CANMOD is 1.</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>IDINDEX</name>
                            <description>ID Index. If the BP bit (below) is 0, this value is the
                                zero-based number of the Lookup Table RAM entry at which the
                                Acceptance Filter matched the received Identifier. Disabled entries
                                in the Standard tables are included in this numbering, but will not
                                be matched. See Section 21.17 Examples of acceptance filter tables
                                and ID index values on page 587 for examples of ID Index values.</description>
                            <bitRange>[9:0]</bitRange>
                        </field>
                        <field>
                            <name>BP</name>
                            <description>If this bit is 1, the current message was received in AF
                                Bypass mode, and the ID Index field (above) is meaningless.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[15:11]</bitRange>
                        </field>
                        <field>
                            <name>DLC</name>
                            <description>The field contains the Data Length Code (DLC) field of the
                                current received message. When RTR = 0, this is related to the
                                number of data bytes available in the CANRDA and CANRDB registers as
                                follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1,
                                this value indicates the number of data bytes requested to be sent
                                back, with the same encoding.</description>
                            <bitRange>[19:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[29:20]</bitRange>
                        </field>
                        <field>
                            <name>RTR</name>
                            <description>This bit contains the Remote Transmission Request bit of
                                the current received message. 0 indicates a Data Frame, in which (if
                                DLC is non-zero) data can be read from the CANRDA and possibly the
                                CANRDB registers. 1 indicates a Remote frame, in which case the DLC
                                value identifies the number of data bytes requested to be sent using
                                the same Identifier.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>FF</name>
                            <description>A 0 in this bit indicates that the current received message
                                included an 11-bit Identifier, while a 1 indicates a 29-bit
                                Identifier. This affects the contents of the CANid register
                                described below.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RID</name>
                    <description>Received Identifier. Can only be written when RM in CANMOD is 1.</description>
                    <addressOffset>0x024</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ID</name>
                            <description>The 11-bit Identifier field of the current received
                                message. In CAN 2.0A, these bits are called ID10-0, while in CAN
                                2.0B they're called ID29-18.</description>
                            <bitRange>[10:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:11]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RDA</name>
                    <description>Received data bytes 1-4. Can only be written when RM in CANMOD is
                        1.</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DATA1</name>
                            <description>Data 1. If the DLC field in CANRFS >= 0001, this contains
                                the first Data byte of the current received message.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>DATA2</name>
                            <description>Data 2. If the DLC field in CANRFS >= 0010, this contains
                                the first Data byte of the current received message.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>DATA3</name>
                            <description>Data 3. If the DLC field in CANRFS >= 0011, this contains
                                the first Data byte of the current received message.</description>
                            <bitRange>[23:16]</bitRange>
                        </field>
                        <field>
                            <name>DATA4</name>
                            <description>Data 4. If the DLC field in CANRFS >= 0100, this contains
                                the first Data byte of the current received message.</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RDB</name>
                    <description>Received data bytes 5-8. Can only be written when RM in CANMOD is
                        1.</description>
                    <addressOffset>0x02C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DATA5</name>
                            <description>Data 5. If the DLC field in CANRFS >= 0101, this contains
                                the first Data byte of the current received message.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>DATA6</name>
                            <description>Data 6. If the DLC field in CANRFS >= 0110, this contains
                                the first Data byte of the current received message.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>DATA7</name>
                            <description>Data 7. If the DLC field in CANRFS >= 0111, this contains
                                the first Data byte of the current received message.</description>
                            <bitRange>[23:16]</bitRange>
                        </field>
                        <field>
                            <name>DATA8</name>
                            <description>Data 8. If the DLC field in CANRFS >= 1000, this contains
                                the first Data byte of the current received message.</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x10</dimIncrement>
                    <dimIndex>1-3</dimIndex>
                    <name>TFI%s</name>
                    <description>Transmit frame info (Tx Buffer )</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PRIO</name>
                            <description>If the TPM (Transmit Priority Mode) bit in the CANxMOD
                                register is set to 1, enabled Tx Buffers contend for the right to
                                send their messages based on this field. The buffer with the lowest
                                TX Priority value wins the prioritization and is sent first.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>DLC</name>
                            <description>Data Length Code. This value is sent in the DLC field of
                                the next transmit message. In addition, if RTR = 0, this value
                                controls the number of Data bytes sent in the next transmit message,
                                from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx =
                                8 bytes</description>
                            <bitRange>[19:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[29:20]</bitRange>
                        </field>
                        <field>
                            <name>RTR</name>
                            <description>This value is sent in the RTR bit of the next transmit
                                message. If this bit is 0, the number of data bytes called out by
                                the DLC field are sent from the CANxTDA and CANxTDB registers. If
                                this bit is 1, a Remote Frame is sent, containing a request for that
                                number of bytes.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>FF</name>
                            <description>If this bit is 0, the next transmit message will be sent
                                with an 11-bit Identifier (standard frame format), while if it's 1,
                                the message will be sent with a 29-bit Identifier (extended frame
                                format).</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x10</dimIncrement>
                    <dimIndex>1-3</dimIndex>
                    <name>TID%s</name>
                    <description>Transmit Identifier (Tx Buffer)</description>
                    <addressOffset>0x034</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ID</name>
                            <description>The 11-bit Identifier to be sent in the next transmit
                                message.</description>
                            <bitRange>[10:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:11]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x10</dimIncrement>
                    <dimIndex>1-3</dimIndex>
                    <name>TDA%s</name>
                    <description>Transmit data bytes 1-4 (Tx Buffer)</description>
                    <addressOffset>0x038</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DATA1</name>
                            <description>Data 1. If RTR = 0 and DLC >= 0001 in the corresponding
                                CANxTFI, this byte is sent as the first Data byte of the next
                                transmit message.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>DATA2</name>
                            <description>Data 2. If RTR = 0 and DLC >= 0010 in the corresponding
                                CANxTFI, this byte is sent as the 2nd Data byte of the next transmit
                                message.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>DATA3</name>
                            <description>Data 3. If RTR = 0 and DLC >= 0011 in the corresponding
                                CANxTFI, this byte is sent as the 3rd Data byte of the next transmit
                                message.</description>
                            <bitRange>[23:16]</bitRange>
                        </field>
                        <field>
                            <name>DATA4</name>
                            <description>Data 4. If RTR = 0 and DLC >= 0100 in the corresponding
                                CANxTFI, this byte is sent as the 4th Data byte of the next transmit
                                message.</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x10</dimIncrement>
                    <dimIndex>1-3</dimIndex>
                    <name>TDB%s</name>
                    <description>Transmit data bytes 5-8 (Tx Buffer )</description>
                    <addressOffset>0x03C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>DATA5</name>
                            <description>Data 5. If RTR = 0 and DLC >= 0101 in the corresponding
                                CANTFI, this byte is sent as the 5th Data byte of the next transmit
                                message.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>DATA6</name>
                            <description>Data 6. If RTR = 0 and DLC >= 0110 in the corresponding
                                CANTFI, this byte is sent as the 6th Data byte of the next transmit
                                message.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>DATA7</name>
                            <description>Data 7. If RTR = 0 and DLC >= 0111 in the corresponding
                                CANTFI, this byte is sent as the 7th Data byte of the next transmit
                                message.</description>
                            <bitRange>[23:16]</bitRange>
                        </field>
                        <field>
                            <name>DATA8</name>
                            <description>Data 8. If RTR = 0 and DLC >= 1000 in the corresponding
                                CANTFI, this byte is sent as the 8th Data byte of the next transmit
                                message.</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral derivedFrom="CAN1">
            <name>CAN2</name>
            <baseAddress>0x40048000</baseAddress>
        </peripheral>
        <peripheral derivedFrom="I2C0">
            <name>I2C1</name>
            <baseAddress>0x4005C000</baseAddress>
            <interrupt>
                <name>I2C1</name>
                <value>11</value>
            </interrupt>
        </peripheral>
        <peripheral derivedFrom="SSP0">
            <name>SSP1</name>
            <description>SSP controller</description>
            <groupName>SSP</groupName>
            <baseAddress>0x40030000</baseAddress>
            <interrupt>
                <name>SSP1</name>
                <value>15</value>
            </interrupt>
        </peripheral>
        <peripheral>
            <name>DAC</name>
            <description> Digital-to-Analog Converter (DAC) </description>
            <groupName>DAC</groupName>
            <baseAddress>0x4008C000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <registers>
                <register>
                    <name>CR</name>
                    <description>D/A Converter Register. This register contains the digital value to
                        be converted to analog and a power control bit.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[5:0]</bitRange>
                        </field>
                        <field>
                            <name>VALUE</name>
                            <description>After the selected settling time after this field is
                                written with a new VALUE, the voltage on the DAC_OUT pin (with
                                respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN.</description>
                            <bitRange>[15:6]</bitRange>
                        </field>
                        <field>
                            <name>BIAS</name>
                            <description>Settling time The settling times noted in the description
                                of the BIAS bit are valid for a capacitance load on the DAC_OUT pin
                                not exceeding 100 pF. A load impedance value greater than that value
                                will cause settling time longer than the specified time. One or more
                                graphs of load impedance vs. settling time will be included in the
                                final data sheet.</description>
                            <bitRange>[16:16]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>FAST</name>
                                    <description>The settling time of the DAC is 1 us max, and the
                                        maximum current is 700 uA. This allows a maximum update rate
                                        of 1 MHz.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SLOW</name>
                                    <description>The settling time of the DAC is 2.5 us and the
                                        maximum current is 350 uA. This allows a maximum update rate
                                        of 400 kHz.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:17]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CTRL</name>
                    <description>DAC Control register. This register controls DMA and timer
                        operation.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>INT_DMA_REQ</name>
                            <description>DMA interrupt request</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CLEAR_ON_ANY_WRITE_T</name>
                                    <description>Clear on any write to the DACR register.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SET_BY_HARDWARE_WHEN</name>
                                    <description>Set by hardware when the timer times out.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DBLBUF_ENA</name>
                            <description>Double buffering</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Disable</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_WHEN_THIS_BI</name>
                                    <description>Enable. When this bit and the CNT_ENA bit are both
                                        set, the double-buffering feature in the DACR register will
                                        be enabled. Writes to the DACR register are written to a
                                        pre-buffer and then transferred to the DACR on the next
                                        time-out of the counter.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CNT_ENA</name>
                            <description>Time-out counter operation</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Disable</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE</name>
                                    <description>Enable</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DMA_ENA</name>
                            <description>DMA access</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE</name>
                                    <description>Disable</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_DMA_BURST_RE</name>
                                    <description>Enable. DMA Burst Request Input 7 is enabled for
                                        the DAC (see Table 672).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CNTVAL</name>
                    <description>DAC Counter Value register. This register contains the reload value
                        for the DAC DMA/Interrupt timer.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>VALUE</name>
                            <description>16-bit reload value for the DAC interrupt/DMA timer.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral derivedFrom="TIMER0">
            <name>TIMER2</name>
            <baseAddress>0x40090000</baseAddress>
            <interrupt>
                <name>TIMER2</name>
                <value>3</value>
            </interrupt>
        </peripheral>
        <peripheral derivedFrom="TIMER0">
            <name>TIMER3</name>
            <baseAddress>0x40094000</baseAddress>
            <interrupt>
                <name>TIMER3</name>
                <value>4</value>
            </interrupt>
        </peripheral>
        <peripheral derivedFrom="UART0">
            <name>UART2</name>
            <baseAddress>0x40098000</baseAddress>
            <interrupt>
                <name>UART2</name>
                <value>7</value>
            </interrupt>
        </peripheral>
        <peripheral derivedFrom="UART0">
            <name>UART3</name>
            <baseAddress>0x4009C000</baseAddress>
            <interrupt>
                <name>UART3</name>
                <value>8</value>
            </interrupt>
        </peripheral>
        <peripheral derivedFrom="I2C0">
            <name>I2C2</name>
            <baseAddress>0x400A0000</baseAddress>
            <interrupt>
                <name>I2C2</name>
                <value>12</value>
            </interrupt>
        </peripheral>
        <peripheral>
            <name>I2S</name>
            <description>I2S interface</description>
            <groupName>I2S</groupName>
            <baseAddress>0x400A8000</baseAddress>
            <addressBlock>
                <offset>0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>I2S</name>
                <value>27</value>
            </interrupt>
            <registers>
                <register>
                    <name>DAO</name>
                    <description>I2S Digital Audio Output Register. Contains control bits for the
                        I2S transmit channel.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x87E1</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>WORDWIDTH</name>
                            <description>Selects the number of bytes in data as follows:</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>8_BIT_DATA</name>
                                    <description>8-bit data</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>16_BIT_DATA</name>
                                    <description>16-bit data</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>32_BIT_DATA</name>
                                    <description>32-bit data</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MONO</name>
                            <description>When 1, data is of monaural format. When 0, the data is in
                                stereo format.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>STOP</name>
                            <description>When 1, disables accesses on FIFOs, places the transmit
                                channel in mute mode.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESET</name>
                            <description>When 1, asynchronously resets the transmit channel and
                                FIFO.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>WS_SEL</name>
                            <description>When 0, the interface is in master mode. When 1, the
                                interface is in slave mode. See Section 34.7.2 for a summary of
                                useful combinations for this bit with TXMODE.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>WS_HALFPERIOD</name>
                            <description>Word select half period minus 1, i.e. WS 64clk period ->
                                ws_halfperiod = 31.</description>
                            <bitRange>[14:6]</bitRange>
                        </field>
                        <field>
                            <name>MUTE</name>
                            <description>When 1, the transmit channel sends only zeroes.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DAI</name>
                    <description>I2S Digital Audio Input Register. Contains control bits for the I2S
                        receive channel.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x07E1</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>WORDWIDTH</name>
                            <description>Selects the number of bytes in data as follows:</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>8_BIT_DATA</name>
                                    <description>8-bit data</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>16_BIT_DATA</name>
                                    <description>16-bit data</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>32_BIT_DATA</name>
                                    <description>32-bit data</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>MONO</name>
                            <description>When 1, data is of monaural format. When 0, the data is in
                                stereo format.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>STOP</name>
                            <description>When 1, disables accesses on FIFOs, places the transmit
                                channel in mute mode.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESET</name>
                            <description>When 1, asynchronously reset the transmit channel and FIFO.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>WS_SEL</name>
                            <description>When 0, the interface is in master mode. When 1, the
                                interface is in slave mode. See Section 34.7.2 for a summary of
                                useful combinations for this bit with RXMODE.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>WS_HALFPERIOD</name>
                            <description>Word select half period minus 1, i.e. WS 64clk period ->
                                ws_halfperiod = 31.</description>
                            <bitRange>[14:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:15]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXFIFO</name>
                    <description>I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter
                        FIFO.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>I2STXFIFO</name>
                            <description>8 x 32-bit transmit FIFO.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXFIFO</name>
                    <description>I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <readAction>modify</readAction>
                    <fields>
                        <field>
                            <name>I2SRXFIFO</name>
                            <description>8 x 32-bit transmit FIFO.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>STATE</name>
                    <description>I2S Status Feedback Register. Contains status information about the
                        I2S interface.</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x7</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>IRQ</name>
                            <description>This bit reflects the presence of Receive Interrupt or
                                Transmit Interrupt. This is determined by comparing the current FIFO
                                levels to the rx_depth_irq and tx_depth_irq fields in the IRQ
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>DMAREQ1</name>
                            <description>This bit reflects the presence of Receive or Transmit DMA
                                Request 1. This is determined by comparing the current FIFO levels
                                to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>DMAREQ2</name>
                            <description>This bit reflects the presence of Receive or Transmit DMA
                                Request 2. This is determined by comparing the current FIFO levels
                                to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:3]</bitRange>
                        </field>
                        <field>
                            <name>RX_LEVEL</name>
                            <description>Reflects the current level of the Receive FIFO.</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[15:12]</bitRange>
                        </field>
                        <field>
                            <name>TX_LEVEL</name>
                            <description>Reflects the current level of the Transmit FIFO.</description>
                            <bitRange>[19:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:20]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DMA1</name>
                    <description>I2S DMA Configuration Register 1. Contains control information for
                        DMA request 1.</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RX_DMA1_ENABLE</name>
                            <description>When 1, enables DMA1 for I2S receive.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TX_DMA1_ENABLE</name>
                            <description>When 1, enables DMA1 for I2S transmit.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[7:2]</bitRange>
                        </field>
                        <field>
                            <name>RX_DEPTH_DMA1</name>
                            <description>Set the FIFO level that triggers a receive DMA request on
                                DMA1.</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[15:12]</bitRange>
                        </field>
                        <field>
                            <name>TX_DEPTH_DMA1</name>
                            <description>Set the FIFO level that triggers a transmit DMA request on
                                DMA1.</description>
                            <bitRange>[19:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:20]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DMA2</name>
                    <description>I2S DMA Configuration Register 2. Contains control information for
                        DMA request 2.</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RX_DMA2_ENABLE</name>
                            <description>When 1, enables DMA1 for I2S receive.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TX_DMA2_ENABLE</name>
                            <description>When 1, enables DMA1 for I2S transmit.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:2]</bitRange>
                        </field>
                        <field>
                            <name>RX_DEPTH_DMA2</name>
                            <description>Set the FIFO level that triggers a receive DMA request on
                                DMA2.</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[15:12]</bitRange>
                        </field>
                        <field>
                            <name>TX_DEPTH_DMA2</name>
                            <description>Set the FIFO level that triggers a transmit DMA request on
                                DMA2.</description>
                            <bitRange>[19:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:20]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IRQ</name>
                    <description>I2S Interrupt Request Control Register. Contains bits that control
                        how the I2S interrupt request is generated.</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RX_IRQ_ENABLE</name>
                            <description>When 1, enables I2S receive interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TX_IRQ_ENABLE</name>
                            <description>When 1, enables I2S transmit interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:2]</bitRange>
                        </field>
                        <field>
                            <name>RX_DEPTH_IRQ</name>
                            <description>Set the FIFO level on which to create an irq request.</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[15:12]</bitRange>
                        </field>
                        <field>
                            <name>TX_DEPTH_IRQ</name>
                            <description>Set the FIFO level on which to create an irq request.</description>
                            <bitRange>[19:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:20]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXRATE</name>
                    <description>I2S Transmit MCLK divider. This register determines the I2S TX MCLK
                        rate by specifying the value to divide PCLK by in order to produce MCLK.</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>Y_DIVIDER</name>
                            <description>I2S transmit MCLK rate denominator. This value is used to
                                divide PCLK to produce the transmit MCLK. Eight bits of fractional
                                divide supports a wide range of possibilities. A value of 0 stops
                                the clock.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>X_DIVIDER</name>
                            <description>I2S transmit MCLK rate numerator. This value is used to
                                multiply PCLK by to produce the transmit MCLK. A value of 0 stops
                                the clock. Eight bits of fractional divide supports a wide range of
                                possibilities. Note: the resulting ratio X/Y is divided by 2.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXRATE</name>
                    <description>I2S Receive MCLK divider. This register determines the I2S RX MCLK
                        rate by specifying the value to divide PCLK by in order to produce MCLK.</description>
                    <addressOffset>0x024</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>Y_DIVIDER</name>
                            <description>I2S receive MCLK rate denominator. This value is used to
                                divide PCLK to produce the receive MCLK. Eight bits of fractional
                                divide supports a wide range of possibilities. A value of 0 stops
                                the clock.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>X_DIVIDER</name>
                            <description>I2S receive MCLK rate numerator. This value is used to
                                multiply PCLK by to produce the receive MCLK. A value of 0 stops the
                                clock. Eight bits of fractional divide supports a wide range of
                                possibilities. Note: the resulting ratio X/Y is divided by 2.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXBITRATE</name>
                    <description>I2S Transmit bit rate divider. This register determines the I2S
                        transmit bit rate by specifying the value to divide TX_MCLK by in order to
                        produce the transmit bit clock.</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TX_BITRATE</name>
                            <description>I2S transmit bit rate. This value plus one is used to
                                divide TX_MCLK to produce the transmit bit clock.</description>
                            <bitRange>[5:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXBITRATE</name>
                    <description>I2S Receive bit rate divider. This register determines the I2S
                        receive bit rate by specifying the value to divide RX_MCLK by in order to
                        produce the receive bit clock.</description>
                    <addressOffset>0x02C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RX_BITRATE</name>
                            <description>I2S receive bit rate. This value plus one is used to divide
                                RX_MCLK to produce the receive bit clock.</description>
                            <bitRange>[5:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXMODE</name>
                    <description>I2S Transmit mode control.</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TXCLKSEL</name>
                            <description>Clock source selection for the transmit bit clock divider.</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SELECT_THE_TX_FRACTI</name>
                                    <description>Select the TX fractional rate divider clock output
                                        as the source</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECT_THE_RX_MCLK_S</name>
                                    <description>Select the RX_MCLK signal as the TX_MCLK clock
                                        source</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TX4PIN</name>
                            <description>Transmit 4-pin mode selection. When 1, enables 4-pin mode.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>TXMCENA</name>
                            <description>Enable for the TX_MCLK output. When 0, output of TX_MCLK is
                                not enabled. When 1, output of TX_MCLK is enabled.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXMODE</name>
                    <description>I2S Receive mode control.</description>
                    <addressOffset>0x034</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXCLKSEL</name>
                            <description>Clock source selection for the receive bit clock divider.</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SELECT_THE_RX_FRACTI</name>
                                    <description>Select the RX fractional rate divider clock output
                                        as the source</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECT_THE_TX_MCLK_S</name>
                                    <description>Select the TX_MCLK signal as the RX_MCLK clock
                                        source</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RX4PIN</name>
                            <description>Receive 4-pin mode selection. When 1, enables 4-pin mode.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RXMCENA</name>
                            <description>Enable for the RX_MCLK output. When 0, output of RX_MCLK is
                                not enabled. When 1, output of RX_MCLK is enabled.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>RITIMER</name>
            <description>Repetitive Interrupt Timer (RIT) </description>
            <groupName>RIT</groupName>
            <baseAddress>0x400B0000</baseAddress>
            <addressBlock>
                <offset>0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>RIT</name>
                <value>29</value>
            </interrupt>
            <registers>
                <register>
                    <name>COMPVAL</name>
                    <description>Compare register</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0xFFFFFFFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RICOMP</name>
                            <description>Compare register. Holds the compare value which is compared
                                to the counter.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MASK</name>
                    <description>Mask register. This register holds the 32-bit mask value. A 1
                        written to any bit will force a compare on the corresponding bit of the
                        counter and compare register.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RIMASK</name>
                            <description>Mask register. This register holds the 32-bit mask value. A
                                one written to any bit overrides the result of the comparison for
                                the corresponding bit of the counter and compare register (causes
                                the comparison of the register bits to be always true).</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CTRL</name>
                    <description>Control register.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0xC</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RITINT</name>
                            <description>Interrupt flag</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_BIT_IS_SET_TO_1</name>
                                    <description>This bit is set to 1 by hardware whenever the
                                        counter value equals the masked compare value specified by
                                        the contents of RICOMPVAL and RIMASK registers. Writing a 1
                                        to this bit will clear it to 0. Writing a 0 has no effect.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_COUNTER_VALUE_DO</name>
                                    <description>The counter value does not equal the masked compare
                                        value.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RITENCLR</name>
                            <description>Timer enable clear</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_TIMER_WILL_BE_CL</name>
                                    <description>The timer will be cleared to 0 whenever the counter
                                        value equals the masked compare value specified by the
                                        contents of RICOMPVAL and RIMASK registers. This will occur
                                        on the same clock that sets the interrupt flag.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>THE_TIMER_WILL_NOT_B</name>
                                    <description>The timer will not be cleared to 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RITENBR</name>
                            <description>Timer enable for debug</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THE_TIMER_IS_HALTED_</name>
                                    <description>The timer is halted when the processor is halted
                                        for debugging.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DEBUG_HAS_NO_EFFECT_</name>
                                    <description>Debug has no effect on the timer operation.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RITEN</name>
                            <description>Timer enable.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TIMER_ENABLED_THIS_</name>
                                    <description>Timer enabled. This can be overruled by a debug
                                        halt if enabled in bit 2.</description>
                                    <value>1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TIMER_DISABLED_</name>
                                    <description>Timer disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>COUNTER</name>
                    <description>32-bit counter</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RICOUNTER</name>
                            <description>32-bit up counter. Counts continuously unless RITEN bit in
                                RICTRL register is cleared or debug mode is entered (if enabled by
                                the RITNEBR bit in RICTRL). Can be loaded to any value in software.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>MCPWM</name>
            <description>Motor Control PWM</description>
            <groupName>MCPWM</groupName>
            <baseAddress>0x400B8000</baseAddress>
            <addressBlock>
                <offset>0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>MCPWM</name>
                <value>30</value>
            </interrupt>
            <registers>
                <register>
                    <name>CON</name>
                    <description>PWM Control read address</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RUN0</name>
                            <description>Stops/starts timer channel 0.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>STOP_</name>
                                    <description>Stop.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RUN_</name>
                                    <description>Run.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CENTER0</name>
                            <description>Edge/center aligned operation for channel 0.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>EDGE_ALIGNED_</name>
                                    <description>Edge-aligned.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CENTER_ALIGNED_</name>
                                    <description>Center-aligned.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>POLA0</name>
                            <description>Selects polarity of the MCOA0 and MCOB0 pins.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>PASSIVE_STATE_IS_LOW</name>
                                    <description>Passive state is LOW, active state is HIGH.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>PASSIVE_STATE_IS_HIG</name>
                                    <description>Passive state is HIGH, active state is LOW.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DTE0</name>
                            <description>Controls the dead-time feature for channel 0.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DEAD_TIME_DISABLED_</name>
                                    <description>Dead-time disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DEAD_TIME_ENABLED_</name>
                                    <description>Dead-time enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DISUP0</name>
                            <description>Enable/disable updates of functional registers for channel
                                0 (see Section 24.8.2).</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>UPDATE</name>
                                    <description>Functional registers are updated from the write
                                        registers at the end of each PWM cycle.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NOUPDATE</name>
                                    <description>Functional registers remain the same as long as the
                                        timer is running.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:5]</bitRange>
                        </field>
                        <field>
                            <name>RUN1</name>
                            <description>Stops/starts timer channel 1.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>STOP_</name>
                                    <description>Stop.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RUN_</name>
                                    <description>Run.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CENTER1</name>
                            <description>Edge/center aligned operation for channel 1.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>EDGE_ALIGNED_</name>
                                    <description>Edge-aligned.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CENTER_ALIGNED_</name>
                                    <description>Center-aligned.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>POLA1</name>
                            <description>Selects polarity of the MCOA1 and MCOB1 pins.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>PASSIVE_STATE_IS_LOW</name>
                                    <description>Passive state is LOW, active state is HIGH.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>PASSIVE_STATE_IS_HIG</name>
                                    <description>Passive state is HIGH, active state is LOW.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DTE1</name>
                            <description>Controls the dead-time feature for channel 1.</description>
                            <bitRange>[11:11]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DEAD_TIME_DISABLED_</name>
                                    <description>Dead-time disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DEAD_TIME_ENABLED_</name>
                                    <description>Dead-time enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DISUP1</name>
                            <description>Enable/disable updates of functional registers for channel
                                1 (see Section 24.8.2).</description>
                            <bitRange>[12:12]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>UPDATE</name>
                                    <description>Functional registers are updated from the write
                                        registers at the end of each PWM cycle.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NOUPDATE</name>
                                    <description>Functional registers remain the same as long as the
                                        timer is running.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[15:13]</bitRange>
                        </field>
                        <field>
                            <name>RUN2</name>
                            <description>Stops/starts timer channel 2.</description>
                            <bitRange>[16:16]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>STOP_</name>
                                    <description>Stop.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RUN_</name>
                                    <description>Run.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CENTER2</name>
                            <description>Edge/center aligned operation for channel 2.</description>
                            <bitRange>[17:17]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>EDGE_ALIGNED_</name>
                                    <description>Edge-aligned.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CENTER_ALIGNED_</name>
                                    <description>Center-aligned.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>POLA2</name>
                            <description>Selects polarity of the MCOA2 and MCOB2 pins.</description>
                            <bitRange>[18:18]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>PASSIVE_STATE_IS_LOW</name>
                                    <description>Passive state is LOW, active state is HIGH.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>PASSIVE_STATE_IS_HIG</name>
                                    <description>Passive state is HIGH, active state is LOW.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DTE2</name>
                            <description>Controls the dead-time feature for channel 1.</description>
                            <bitRange>[19:19]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DEAD_TIME_DISABLED_</name>
                                    <description>Dead-time disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DEAD_TIME_ENABLED_</name>
                                    <description>Dead-time enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DISUP2</name>
                            <description>Enable/disable updates of functional registers for channel
                                2 (see Section 24.8.2).</description>
                            <bitRange>[20:20]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>UPDATE</name>
                                    <description>Functional registers are updated from the write
                                        registers at the end of each PWM cycle.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NOUPDATE</name>
                                    <description>Functional registers remain the same as long as the
                                        timer is running.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[28:21]</bitRange>
                        </field>
                        <field>
                            <name>INVBDC</name>
                            <description>Controls the polarity of the MCOB outputs for all 3
                                channels. This bit is typically set to 1 only in 3-phase DC mode.</description>
                            <bitRange>[29:29]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>OPPOSITE</name>
                                    <description>The MCOB outputs have opposite polarity from the
                                        MCOA outputs (aside from dead time).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SAME</name>
                                    <description>The MCOB outputs have the same basic polarity as
                                        the MCOA outputs. (see Section 24.8.6)</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ACMODE</name>
                            <description>3-phase AC mode select (see Section 24.8.7).</description>
                            <bitRange>[30:30]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>3_PHASE_AC_MODE_OFF</name>
                                    <description>3-phase AC-mode off: Each PWM channel uses its own
                                        timer-counter and period register.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>3_PHASE_AC_MODE_ON_</name>
                                    <description>3-phase AC-mode on: All PWM channels use the
                                        timer-counter and period register of channel 0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DCMODE</name>
                            <description>3-phase DC mode select (see Section 24.8.6).</description>
                            <bitRange>[31:31]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>3_PHASE_DC_MODE_OFF</name>
                                    <description>3-phase DC mode off: PWM channels are independent
                                        (unless bit ACMODE = 1)</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>3_PHASE_DC_MODE_ON_</name>
                                    <description>3-phase DC mode on: The internal MCOA0 output is
                                        routed through the CP register (i.e. a mask) register to all
                                        six PWM outputs.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CON_SET</name>
                    <description>PWM Control set address</description>
                    <addressOffset>0x004</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>RUN0_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>CENTER0_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>POLA0_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DTE0_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>DISUP0_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[7:5]</bitRange>
                        </field>
                        <field>
                            <name>RUN1_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>CENTER1_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>POLA1_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>DTE1_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>DISUP1_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[15:13]</bitRange>
                        </field>
                        <field>
                            <name>RUN2_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>CENTER2_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>POLA2_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>DTE2_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>DISUP2_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[28:21]</bitRange>
                        </field>
                        <field>
                            <name>INVBDC_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>ACMODE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>DCMODE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CON
                                register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CON_CLR</name>
                    <description>PWM Control clear address</description>
                    <addressOffset>0x008</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>RUN0_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>CENTER0_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>POLA0_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DTE0_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>DISUP0_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[7:5]</bitRange>
                        </field>
                        <field>
                            <name>RUN1_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>CENTER1_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>POLA1_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>DTE1_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>DISUP1_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[15:13]</bitRange>
                        </field>
                        <field>
                            <name>RUN2_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>CENTER2_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>POLA2_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>DTE2_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>DISUP2_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[28:21]</bitRange>
                        </field>
                        <field>
                            <name>INVBDC_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>ACMOD_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>DCMODE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CON
                                register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CAPCON</name>
                    <description>Capture Control read address</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CAP0MCI0_RE</name>
                            <description>A 1 in this bit enables a channel 0 capture event on a
                                rising edge on MCI0.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI0_FE</name>
                            <description>A 1 in this bit enables a channel 0 capture event on a
                                falling edge on MCI0.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI1_RE</name>
                            <description>A 1 in this bit enables a channel 0 capture event on a
                                rising edge on MCI1.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI1_FE</name>
                            <description>A 1 in this bit enables a channel 0 capture event on a
                                falling edge on MCI1.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI2_RE</name>
                            <description>A 1 in this bit enables a channel 0 capture event on a
                                rising edge on MCI2.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI2_FE</name>
                            <description>A 1 in this bit enables a channel 0 capture event on a
                                falling edge on MCI2.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI0_RE</name>
                            <description>A 1 in this bit enables a channel 1 capture event on a
                                rising edge on MCI0.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI0_FE</name>
                            <description>A 1 in this bit enables a channel 1 capture event on a
                                falling edge on MCI0.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI1_RE</name>
                            <description>A 1 in this bit enables a channel 1 capture event on a
                                rising edge on MCI1.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI1_FE</name>
                            <description>A 1 in this bit enables a channel 1 capture event on a
                                falling edge on MCI1.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI2_RE</name>
                            <description>A 1 in this bit enables a channel 1 capture event on a
                                rising edge on MCI2.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI2_FE</name>
                            <description>A 1 in this bit enables a channel 1 capture event on a
                                falling edge on MCI2.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI0_RE</name>
                            <description>A 1 in this bit enables a channel 2 capture event on a
                                rising edge on MCI0.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI0_FE</name>
                            <description>A 1 in this bit enables a channel 2 capture event on a
                                falling edge on MCI0.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI1_RE</name>
                            <description>A 1 in this bit enables a channel 2 capture event on a
                                rising edge on MCI1.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI1_FE</name>
                            <description>A 1 in this bit enables a channel 2 capture event on a
                                falling edge on MCI1.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI2_RE</name>
                            <description>A 1 in this bit enables a channel 2 capture event on a
                                rising edge on MCI2.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI2_FE</name>
                            <description>A 1 in this bit enables a channel 2 capture event on a
                                falling edge on MCI2.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>RT0</name>
                            <description>If this bit is 1, TC0 is reset by a channel 0 capture
                                event.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>RT1</name>
                            <description>If this bit is 1, TC1 is reset by a channel 1 capture
                                event.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>RT2</name>
                            <description>If this bit is 1, TC2 is reset by a channel 2 capture
                                event.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:21]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CAPCON_SET</name>
                    <description>Capture Control set address</description>
                    <addressOffset>0x010</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>CAP0MCI0_RE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI0_FE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI1_RE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI1_FE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI2_RE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI2_FE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI0_RE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI0_FE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI1_RE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI1_FE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI2_RE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI2_FE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI0_RE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI0_FE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI1_RE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI1_FE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI2_RE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI2_FE_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>RT0_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>RT1_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>RT2_SET</name>
                            <description>Writing a one sets the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:21]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CAPCON_CLR</name>
                    <description>Event Control clear address</description>
                    <addressOffset>0x014</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>CAP0MCI0_RE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI0_FE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI1_RE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI1_FE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI2_RE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>CAP0MCI2_FE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI0_RE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI0_FE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI1_RE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI1_FE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI2_RE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>CAP1MCI2_FE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI0_RE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI0_FE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI1_RE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI1_FE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI2_RE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>CAP2MCI2_FE_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>RT0_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>RT1_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>RT2_CLR</name>
                            <description>Writing a one clears the corresponding bits in the CAPCON
                                register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:21]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-2</dimIndex>
                    <name>TC[%s]</name>
                    <displayName>TC[%s]</displayName>
                    <description>Timer Counter register</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MCTC</name>
                            <description>Timer/Counter value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-2</dimIndex>
                    <name>LIM[%s]</name>
                    <displayName>LIM[%s]</displayName>
                    <description>Limit register</description>
                    <addressOffset>0x024</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MCLIM</name>
                            <description>Limit value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-2</dimIndex>
                    <name>MAT[%s]</name>
                    <displayName>MAT[%s]</displayName>
                    <description>Match register</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MCMAT</name>
                            <description>Match value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DT</name>
                    <description>Dead time register</description>
                    <addressOffset>0x03C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x3FFFFFFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DT0</name>
                            <description>Dead time for channel 0.[1]</description>
                            <bitRange>[9:0]</bitRange>
                        </field>
                        <field>
                            <name>DT1</name>
                            <description>Dead time for channel 1.[2]</description>
                            <bitRange>[19:10]</bitRange>
                        </field>
                        <field>
                            <name>DT2</name>
                            <description>Dead time for channel 2.[2]</description>
                            <bitRange>[29:20]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>reserved</description>
                            <bitRange>[31:30]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CP</name>
                    <description>Communication Pattern register</description>
                    <addressOffset>0x040</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CCPA0</name>
                            <description>Communication pattern output A, channel 0.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MCOA0_PASSIVE_</name>
                                    <description>MCOA0 passive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERNAL_MCOA0_</name>
                                    <description>internal MCOA0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CCPB0</name>
                            <description>Communication pattern output B, channel 0.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MCOB0_PASSIVE_</name>
                                    <description>MCOB0 passive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MCOB0_TRACKS_INTERNA</name>
                                    <description>MCOB0 tracks internal MCOA0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CCPA1</name>
                            <description>Communication pattern output A, channel 1.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MCOA1_PASSIVE_</name>
                                    <description>MCOA1 passive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MCOA1_TRACKS_INTERNA</name>
                                    <description>MCOA1 tracks internal MCOA0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CCPB1</name>
                            <description>Communication pattern output B, channel 1.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MCOB1_PASSIVE_</name>
                                    <description>MCOB1 passive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MCOB1_TRACKS_INTERNA</name>
                                    <description>MCOB1 tracks internal MCOA0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CCPA2</name>
                            <description>Communication pattern output A, channel 2.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MCOA2_PASSIVE_</name>
                                    <description>MCOA2 passive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MCOA2_TRACKS_INTERNA</name>
                                    <description>MCOA2 tracks internal MCOA0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CCPB2</name>
                            <description>Communication pattern output B, channel 2.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>MCOB2_PASSIVE_</name>
                                    <description>MCOB2 passive.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>MCOB2_TRACKS_INTERNA</name>
                                    <description>MCOB2 tracks internal MCOA0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <dim>3</dim>
                    <dimIncrement>0x4</dimIncrement>
                    <dimIndex>0-2</dimIndex>
                    <name>CAP[%s]</name>
                    <displayName>CAP[%s]</displayName>
                    <description>Capture register</description>
                    <addressOffset>0x044</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CAP</name>
                            <description>Current TC value at a capture event.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTEN</name>
                    <description>Interrupt Enable read address</description>
                    <addressOffset>0x050</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ILIM0</name>
                            <description>Limit interrupt for channel 0.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>IMAT0</name>
                            <description>Match interrupt for channel 0.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ICAP0</name>
                            <description>Capture interrupt for channel 0.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ILIM1</name>
                            <description>Limit interrupt for channel 1.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>IMAT1</name>
                            <description>Match interrupt for channel 1.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ICAP1</name>
                            <description>Capture interrupt for channel 1.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>ILIM2</name>
                            <description>Limit interrupt for channel 2.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>IMAT2</name>
                            <description>Match interrupt for channel 2.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ICAP2</name>
                            <description>Capture interrupt for channel 2.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[14:11]</bitRange>
                        </field>
                        <field>
                            <name>ABORT</name>
                            <description>Fast abort interrupt.</description>
                            <bitRange>[15:15]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>INTERRUPT_DISABLED_</name>
                                    <description>Interrupt disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>INTERRUPT_ENABLED_</name>
                                    <description>Interrupt enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTEN_SET</name>
                    <description>Interrupt Enable set address</description>
                    <addressOffset>0x054</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>ILIM0_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>IMAT0_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>ICAP0_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ILIM1_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>IMAT1_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>ICAP1_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>ILIM2_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>IMAT2_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>ICAP2_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[14:12]</bitRange>
                        </field>
                        <field>
                            <name>ABORT_SET</name>
                            <description>Writing a one sets the corresponding bit in INTEN, thus
                                enabling the interrupt.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTEN_CLR</name>
                    <description>Interrupt Enable clear address</description>
                    <addressOffset>0x058</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>ILIM0_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>IMAT0_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>ICAP0_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ILIM1_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>IMAT1_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>ICAP1_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>ILIM2_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>IMAT2_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>ICAP2_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[14:11]</bitRange>
                        </field>
                        <field>
                            <name>ABORT_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTF</name>
                    <description>Interrupt flags read address</description>
                    <addressOffset>0x068</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ILIM0_F</name>
                            <description>Limit interrupt flag for channel 0.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>IMAT0_F</name>
                            <description>Match interrupt flag for channel 0.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ICAP0_F</name>
                            <description>Capture interrupt flag for channel 0.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ILIM1_F</name>
                            <description>Limit interrupt flag for channel 1.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>IMAT1_F</name>
                            <description>Match interrupt flag for channel 1.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ICAP1_F</name>
                            <description>Capture interrupt flag for channel 1.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>ILIM2_F</name>
                            <description>Limit interrupt flag for channel 2.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>IMAT2_F</name>
                            <description>Match interrupt flag for channel 2.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ICAP2_F</name>
                            <description>Capture interrupt flag for channel 2.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[14:11]</bitRange>
                        </field>
                        <field>
                            <name>ABORT_F</name>
                            <description>Fast abort interrupt flag.</description>
                            <bitRange>[15:15]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>THIS_INTERRUPT_SOURC</name>
                                    <description>This interrupt source is not contributing to the
                                        MCPWM interrupt request.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>IF_THE_CORRESPONDING</name>
                                    <description>If the corresponding bit in INTEN is 1, the MCPWM
                                        module is asserting its interrupt request to the Interrupt
                                        Controller.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTF_SET</name>
                    <description>Interrupt flags set address</description>
                    <addressOffset>0x06C</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>ILIM0_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>IMAT0_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>ICAP0_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ILIM1_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>IMAT1_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>ICAP1_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>ILIM2_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>IMAT2_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>ICAP2_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[14:11]</bitRange>
                        </field>
                        <field>
                            <name>ABORT_F_SET</name>
                            <description>Writing a one sets the corresponding bit in the INTF
                                register, thus possibly simulating hardware interrupt.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTF_CLR</name>
                    <description>Interrupt flags clear address</description>
                    <addressOffset>0x070</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>ILIM0_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in the INTF
                                register, thus clearing the corresponding interrupt request.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>IMAT0_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>ICAP0_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ILIM1_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>IMAT1_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>ICAP1_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>ILIM2_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>IMAT2_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>ICAP2_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[14:11]</bitRange>
                        </field>
                        <field>
                            <name>ABORT_F_CLR</name>
                            <description>Writing a one clears the corresponding bit in INTEN, thus
                                disabling the interrupt.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CNTCON</name>
                    <description>Count Control read address</description>
                    <addressOffset>0x05C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TC0MCI0_RE</name>
                            <description>Counter 0 rising edge mode, channel 0.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_RISING_EDGE_ON_MCI</name>
                                    <description>A rising edge on MCI0 does not affect counter 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>If MODE0 is 1, counter 0 advances on a rising edge
                                        on MCI0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC0MCI0_FE</name>
                            <description>Counter 0 falling edge mode, channel 0.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_FALLING_EDGE_ON_MC</name>
                                    <description>A falling edge on MCI0 does not affect counter 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING</name>
                                    <description>If MODE0 is 1, counter 0 advances on a falling edge
                                        on MCI0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC0MCI1_RE</name>
                            <description>Counter 0 rising edge mode, channel 1.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_RISING_EDGE_ON_MCI</name>
                                    <description>A rising edge on MCI1 does not affect counter 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>If MODE0 is 1, counter 0 advances on a rising edge
                                        on MCI1.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC0MCI1_FE</name>
                            <description>Counter 0 falling edge mode, channel 1.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_FALLING_EDGE_ON_MC</name>
                                    <description>A falling edge on MCI1 does not affect counter 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING</name>
                                    <description>If MODE0 is 1, counter 0 advances on a falling edge
                                        on MCI1.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC0MCI2_RE</name>
                            <description>Counter 0 rising edge mode, channel 2.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_RISING_EDGE_ON_MCI</name>
                                    <description>A rising edge on MCI0 does not affect counter 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>If MODE0 is 1, counter 0 advances on a rising edge
                                        on MCI2.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC0MCI2_FE</name>
                            <description>Counter 0 falling edge mode, channel 2.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_FALLING_EDGE_ON_MC</name>
                                    <description>A falling edge on MCI0 does not affect counter 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLLING</name>
                                    <description>If MODE0 is 1, counter 0 advances on a falling edge
                                        on MCI2.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC1MCI0_RE</name>
                            <description>Counter 1 rising edge mode, channel 0.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_RISING_EDGE_ON_MCI</name>
                                    <description>A rising edge on MCI0 does not affect counter 1.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>If MODE1 is 1, counter 1 advances on a rising edge
                                        on MCI0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC1MCI0_FE</name>
                            <description>Counter 1 falling edge mode, channel 0.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_FALLING_EDGE_ON_MC</name>
                                    <description>A falling edge on MCI0 does not affect counter 1.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING</name>
                                    <description>If MODE1 is 1, counter 1 advances on a falling edge
                                        on MCI0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC1MCI1_RE</name>
                            <description>Counter 1 rising edge mode, channel 1.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_RISING_EDGE_ON_MCI</name>
                                    <description>A rising edge on MCI1 does not affect counter 1.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>If MODE1 is 1, counter 1 advances on a rising edge
                                        on MCI1.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC1MCI1_FE</name>
                            <description>Counter 1 falling edge mode, channel 1.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_FALLING_EDGE_ON_MC</name>
                                    <description>A falling edge on MCI0 does not affect counter 1.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING</name>
                                    <description>If MODE1 is 1, counter 1 advances on a falling edge
                                        on MCI1.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC1MCI2_RE</name>
                            <description>Counter 1 rising edge mode, channel 2.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_RISING_EDGE_ON_MCI</name>
                                    <description>A rising edge on MCI2 does not affect counter 1.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>If MODE1 is 1, counter 1 advances on a rising edge
                                        on MCI2.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC1MCI2_FE</name>
                            <description>Counter 1 falling edge mode, channel 2.</description>
                            <bitRange>[11:11]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_FALLING_EDGE_ON_MC</name>
                                    <description>A falling edge on MCI2 does not affect counter 1.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING</name>
                                    <description>If MODE1 is 1, counter 1 advances on a falling edge
                                        on MCI2.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC2MCI0_RE</name>
                            <description>Counter 2 rising edge mode, channel 0.</description>
                            <bitRange>[12:12]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_RISING_EDGE_ON_MCI</name>
                                    <description>A rising edge on MCI0 does not affect counter 2.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>If MODE2 is 1, counter 2 advances on a rising edge
                                        on MCI0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC2MCI0_FE</name>
                            <description>Counter 2 falling edge mode, channel 0.</description>
                            <bitRange>[13:13]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_FALLING_EDGE_ON_MC</name>
                                    <description>A falling edge on MCI0 does not affect counter 2.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING</name>
                                    <description>If MODE2 is 1, counter 2 advances on a falling edge
                                        on MCI0.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC2MCI1_RE</name>
                            <description>Counter 2 rising edge mode, channel 1.</description>
                            <bitRange>[14:14]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_RISING_EDGE_ON_MCI</name>
                                    <description>A rising edge on MCI1 does not affect counter 2.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING</name>
                                    <description>If MODE2 is 1, counter 2 advances on a rising edge
                                        on MCI1.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC2MCI1_FE</name>
                            <description>Counter 2 falling edge mode, channel 1.</description>
                            <bitRange>[15:15]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_FALLING_EDGE_ON_MC</name>
                                    <description>A falling edge on MCI1 does not affect counter 2.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING</name>
                                    <description>If MODE2 is 1, counter 2 advances on a falling edge
                                        on MCI1.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC2MCI2_RE</name>
                            <description>Counter 2 rising edge mode, channel 2.</description>
                            <bitRange>[16:16]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_RISING_EDGE_ON_MCI</name>
                                    <description>A rising edge on MCI2 does not affect counter 2.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISIING</name>
                                    <description>If MODE2 is 1, counter 2 advances on a rising edge
                                        on MCI2.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TC2MCI2_FE</name>
                            <description>Counter 2 falling edge mode, channel 2.</description>
                            <bitRange>[17:17]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>A_FALLING_EDGE_ON_MC</name>
                                    <description>A falling edge on MCI2 does not affect counter 2.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>FALLING</name>
                                    <description>If MODE2 is 1, counter 2 advances on a falling edge
                                        on MCI2.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[28:18]</bitRange>
                        </field>
                        <field>
                            <name>CNTR0</name>
                            <description>Channel 0 counter/timer mode.</description>
                            <bitRange>[29:29]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CHANNEL_0_IS_IN_TIME</name>
                                    <description>Channel 0 is in timer mode.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CHANNEL_0_IS_IN_COUN</name>
                                    <description>Channel 0 is in counter mode.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CNTR1</name>
                            <description>Channel 1 counter/timer mode.</description>
                            <bitRange>[30:30]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CHANNEL_1_IS_IN_TIME</name>
                                    <description>Channel 1 is in timer mode.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CHANNEL_1_IS_IN_COUN</name>
                                    <description>Channel 1 is in counter mode.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CNTR2</name>
                            <description>Channel 2 counter/timer mode.</description>
                            <bitRange>[31:31]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CHANNEL_2_IS_IN_TIME</name>
                                    <description>Channel 2 is in timer mode.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CHANNEL_2_IS_IN_COUN</name>
                                    <description>Channel 2 is in counter mode.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CNTCON_SET</name>
                    <description>Count Control set address</description>
                    <addressOffset>0x060</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>TC0MCI0_RE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI0_FE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI1_RE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI1_FE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI2_RE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI2_FE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI0_RE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI0_FE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI1_RE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI1_FE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI2_RE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI2_FE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI0_RE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI0_FE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI1_RE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI1_FE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI2_RE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI2_FE_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[28:18]</bitRange>
                        </field>
                        <field>
                            <name>CNTR0_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>CNTR1_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>CNTR2_SET</name>
                            <description>Writing a one sets the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CNTCON_CLR</name>
                    <description>Count Control clear address</description>
                    <addressOffset>0x064</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>TC0MCI0_RE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI0_FE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI1_RE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI1_FE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI2_RE</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>TC0MCI2_FE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI0_RE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI0_FE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI1_RE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI1_FE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI2_RE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>TC1MCI2_FE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI0_RE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI0_FE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI1_RE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI1_FE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI2_RE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>TC2MCI2_FE_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[28:18]</bitRange>
                        </field>
                        <field>
                            <name>CNTR0_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>CNTR1_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>CNTR2_CLR</name>
                            <description>Writing a one clears the corresponding bit in the CNTCON
                                register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CAP_CLR</name>
                    <description>Capture clear address</description>
                    <addressOffset>0x074</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>CAP_CLR0</name>
                            <description>Writing a 1 to this bit clears the CAP0 register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>CAP_CLR1</name>
                            <description>Writing a 1 to this bit clears the CAP1 register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>CAP_CLR2</name>
                            <description>Writing a 1 to this bit clears the CAP2 register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>QEI</name>
            <description>Quadrature Encoder Interface (QEI) </description>
            <groupName>QEI</groupName>
            <baseAddress>0x400BC000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>QEI</name>
                <value>31</value>
            </interrupt>
            <registers>
                <register>
                    <name>CON</name>
                    <description>Control register</description>
                    <addressOffset>0x000</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>RESP</name>
                            <description>Reset position counter. When set = 1, resets the position
                                counter to all zeros. Autoclears when the position counter is
                                cleared.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RESPI</name>
                            <description>Reset position counter on index. When set = 1, resets the
                                position counter to all zeros once only the first time an index
                                pulse occurs. Autoclears when the position counter is cleared.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESV</name>
                            <description>Reset velocity. When set = 1, resets the velocity counter
                                to all zeros, reloads the velocity timer, and presets the velocity
                                compare register. Autoclears when the velocity counter is cleared.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESI</name>
                            <description>Reset index counter. When set = 1, resets the index counter
                                to all zeros. Autoclears when the index counter is cleared.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CONF</name>
                    <description>Configuration register</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DIRINV</name>
                            <description>Direction invert. When 1, complements the DIR bit.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>SIGMODE</name>
                            <description>Signal Mode. When 0, PhA and PhB function as quadrature
                                encoder inputs. When 1, PhA functions as the direction signal and
                                PhB functions as the clock signal.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>CAPMODE</name>
                            <description>Capture Mode. When 0, only PhA edges are counted (2X). When
                                1, BOTH PhA and PhB edges are counted (4X), increasing resolution
                                but decreasing range.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>INVINX</name>
                            <description>Invert Index. When 1, inverts the sense of the index input.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CRESPI</name>
                            <description>Continuously reset the position counter on index. When 1,
                                resets the position counter to all zeros whenever an index pulse
                                occurs after the next position increase (recalibration).</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[15:5]</bitRange>
                        </field>
                        <field>
                            <name>INXGATE</name>
                            <description>Index gating configuration: When INXGATE[16] = 1, pass the
                                index when PHA = 1 and PHB = 0, otherwise block index. When
                                INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise
                                block index. When INXGATE[18] = 1, pass the index when PHA = 0 and
                                PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index
                                when PHA = 0 and PHB = 0, otherwise block index.</description>
                            <bitRange>[19:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:20]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>STAT</name>
                    <description>Status register</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DIR</name>
                            <description>Direction bit. In combination with DIRINV bit indicates
                                forward or reverse direction. See Table 597.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:1]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>POS</name>
                    <description>Position register</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>POS</name>
                            <description>Current position value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MAXPOS</name>
                    <description>Maximum position register</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MAXPOS</name>
                            <description>Current maximum position value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CMPOS0</name>
                    <description>Position compare register 0</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0xFFFFFFFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PCMP0</name>
                            <description>Position compare value 0.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CMPOS1</name>
                    <description>Position compare register 1</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-write</access>
                    <resetValue>0xFFFFFFFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PCMP1</name>
                            <description>Position compare value 1.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CMPOS2</name>
                    <description>Position compare register 2</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0xFFFFFFFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PCMP2</name>
                            <description>Position compare value 2.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INXCNT</name>
                    <description>Index count register 0</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ENCPOS</name>
                            <description>Current index counter value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INXCMP0</name>
                    <description>Index compare register 0</description>
                    <addressOffset>0x024</addressOffset>
                    <access>read-write</access>
                    <resetValue>0xFFFFFFFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ICMP0</name>
                            <description>Index compare value 0.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>LOAD</name>
                    <description>Velocity timer reload register</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>VELLOAD</name>
                            <description>Current velocity timer load value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TIME</name>
                    <description>Velocity timer register</description>
                    <addressOffset>0x02C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>VELVAL</name>
                            <description>Current velocity timer value.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>VEL</name>
                    <description>Velocity counter register</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>VELPC</name>
                            <description>Current velocity pulse count.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CAP</name>
                    <description>Velocity capture register</description>
                    <addressOffset>0x034</addressOffset>
                    <access>read-only</access>
                    <resetValue>0xFFFFFFFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>VELCAP</name>
                            <description>Last velocity capture.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>VELCOMP</name>
                    <description>Velocity compare register</description>
                    <addressOffset>0x038</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>VELPC</name>
                            <description>Compare velocity pulse count.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FILTER</name>
                    <description>Digital filter register</description>
                    <addressOffset>0x03C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FILTA</name>
                            <description>Digital filter sampling delay.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTSTAT</name>
                    <description>Interrupt status register</description>
                    <addressOffset>0xFE0</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>INX_INT</name>
                            <description>Indicates that an index pulse was detected.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TIM_INT</name>
                            <description>Indicates that a velocity timer overflow occurred</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>VELC_INT</name>
                            <description>Indicates that captured velocity is less than compare
                                velocity.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DIR_INT</name>
                            <description>Indicates that a change of direction was detected.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INT</name>
                            <description>Indicates that an encoder phase error was detected.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>ENCLK_INT</name>
                            <description>Indicates that and encoder clock pulse was detected.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>POS0_INT</name>
                            <description>Indicates that the position 0 compare value is equal to the
                                current position.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>POS1_INT</name>
                            <description>Indicates that the position 1compare value is equal to the
                                current position.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>POS2_INT</name>
                            <description>Indicates that the position 2 compare value is equal to the
                                current position.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>REV0_INT</name>
                            <description>Indicates that the index compare 0 value is equal to the
                                current index count.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>POS0REV_INT</name>
                            <description>Combined position 0 and revolution count interrupt. Set
                                when both the POS0_Int bit is set and the REV0_Int is set.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>POS1REV_INT</name>
                            <description>Combined position 1 and revolution count interrupt. Set
                                when both the POS1_Int bit is set and the REV1_Int is set.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>POS2REV_INT</name>
                            <description>Combined position 2 and revolution count interrupt. Set
                                when both the POS2_Int bit is set and the REV2_Int is set.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>REV1_INT</name>
                            <description>Indicates that the index compare 1value is equal to the
                                current index count.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>REV2_INT</name>
                            <description>Indicates that the index compare 2 value is equal to the
                                current index count.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>MAXPOS_INT</name>
                            <description>Indicates that the current position count goes through the
                                MAXPOS value to zero in the forward direction, or through zero to
                                MAXPOS in the reverse direction.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SET</name>
                    <description>Interrupt status set register</description>
                    <addressOffset>0xFEC</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>INX_INT</name>
                            <description>Writing a 1 sets the INX_Int bit in QEIINTSTAT.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TIM_INT</name>
                            <description>Writing a 1 sets the TIN_Int bit in QEIINTSTAT.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>VELC_INT</name>
                            <description>Writing a 1 sets the VELC_Int bit in QEIINTSTAT.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DIR_INT</name>
                            <description>Writing a 1 sets the DIR_Int bit in QEIINTSTAT.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INT</name>
                            <description>Writing a 1 sets the ERR_Int bit in QEIINTSTAT.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>ENCLK_INT</name>
                            <description>Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>POS0_INT</name>
                            <description>Writing a 1 sets the POS0_Int bit in QEIINTSTAT.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>POS1_INT</name>
                            <description>Writing a 1 sets the POS1_Int bit in QEIINTSTAT.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>POS2_INT</name>
                            <description>Writing a 1 sets the POS2_Int bit in QEIINTSTAT.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>REV0_INT</name>
                            <description>Writing a 1 sets the REV0_Int bit in QEIINTSTAT.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>POS0REV_INT</name>
                            <description>Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>POS1REV_INT</name>
                            <description>Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>POS2REV_INT</name>
                            <description>Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>REV1_INT</name>
                            <description>Writing a 1 sets the REV1_Int bit in QEIINTSTAT.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>REV2_INT</name>
                            <description>Writing a 1 sets the REV2_Int bit in QEIINTSTAT.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>MAXPOS_INT</name>
                            <description>Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CLR</name>
                    <description>Interrupt status clear register</description>
                    <addressOffset>0xFE8</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>INX_INT</name>
                            <description>Writing a 1 clears the INX_Int bit in QEIINTSTAT.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TIM_INT</name>
                            <description>Writing a 1 clears the TIN_Int bit in QEIINTSTAT.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>VELC_INT</name>
                            <description>Writing a 1 clears the VELC_Int bit in QEIINTSTAT.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DIR_INT</name>
                            <description>Writing a 1 clears the DIR_Int bit in QEIINTSTAT.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INT</name>
                            <description>Writing a 1 clears the ERR_Int bit in QEIINTSTAT.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>ENCLK_INT</name>
                            <description>Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>POS0_INT</name>
                            <description>Writing a 1 clears the POS0_Int bit in QEIINTSTAT.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>POS1_INT</name>
                            <description>Writing a 1 clears the POS1_Int bit in QEIINTSTAT.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>POS2_INT</name>
                            <description>Writing a 1 clears the POS2_Int bit in QEIINTSTAT.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>REV0_INT</name>
                            <description>Writing a 1 clears the REV0_Int bit in QEIINTSTAT.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>POS0REV_INT</name>
                            <description>Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>POS1REV_INT</name>
                            <description>Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>POS2REV_INT</name>
                            <description>Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>REV1_INT</name>
                            <description>Writing a 1 clears the REV1_Int bit in QEIINTSTAT.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>REV2_INT</name>
                            <description>Writing a 1 clears the REV2_Int bit in QEIINTSTAT.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>MAXPOS_INT</name>
                            <description>Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IE</name>
                    <description>Interrupt enable register</description>
                    <addressOffset>0xFE4</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>INX_INT</name>
                            <description>When 1, the INX_Int interrupt is enabled.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TIM_INT</name>
                            <description>When 1, the TIN_Int interrupt is enabled.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>VELC_INT</name>
                            <description>When 1, the VELC_Int interrupt is enabled.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DIR_INT</name>
                            <description>When 1, the DIR_Int interrupt is enabled.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INT</name>
                            <description>When 1, the ERR_Int interrupt is enabled.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>ENCLK_INT</name>
                            <description>When 1, the ENCLK_Int interrupt is enabled.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>POS0_INT</name>
                            <description>When 1, the POS0_Int interrupt is enabled.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>POS1_INT</name>
                            <description>When 1, the POS1_Int interrupt is enabled.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>POS2_INT</name>
                            <description>When 1, the POS2_Int interrupt is enabled.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>REV0_INT</name>
                            <description>When 1, the REV0_Int interrupt is enabled.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>POS0REV_INT</name>
                            <description>When 1, the POS0REV_Int interrupt is enabled.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>POS1REV_INT</name>
                            <description>When 1, the POS1REV_Int interrupt is enabled.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>POS2REV_INT</name>
                            <description>When 1, the POS2REV_Int interrupt is enabled.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>REV1_INT</name>
                            <description>When 1, the REV1_Int interrupt is enabled.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>REV2_INT</name>
                            <description>When 1, the REV2_Int interrupt is enabled.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>MAXPOS_INT</name>
                            <description>When 1, the MAXPOS_Int interrupt is enabled.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IES</name>
                    <description>Interrupt enable set register</description>
                    <addressOffset>0xFDC</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>INX_INT</name>
                            <description>Writing a 1 enables the INX_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TIM_INT</name>
                            <description>Writing a 1 enables the TIN_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>VELC_INT</name>
                            <description>Writing a 1 enables the VELC_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DIR_INT</name>
                            <description>Writing a 1 enables the DIR_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INT</name>
                            <description>Writing a 1 enables the ERR_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>ENCLK_INT</name>
                            <description>Writing a 1 enables the ENCLK_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>POS0_INT</name>
                            <description>Writing a 1 enables the POS0_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>POS1_INT</name>
                            <description>Writing a 1 enables the POS1_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>POS2_INT</name>
                            <description>Writing a 1 enables the POS2_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>REV0_INT</name>
                            <description>Writing a 1 enables the REV0_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>POS0REV_INT</name>
                            <description>Writing a 1 enables the POS0REV_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>POS1REV_INT</name>
                            <description>Writing a 1 enables the POS1REV_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>POS2REV_INT</name>
                            <description>Writing a 1 enables the POS2REV_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>REV1_INT</name>
                            <description>Writing a 1 enables the REV1_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>REV2_INT</name>
                            <description>Writing a 1 enables the REV2_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>MAXPOS_INT</name>
                            <description>Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IEC</name>
                    <description>Interrupt enable clear register</description>
                    <addressOffset>0xFD8</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>INX_INT</name>
                            <description>Writing a 1 disables the INX_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TIM_INT</name>
                            <description>Writing a 1 disables the TIN_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>VELC_INT</name>
                            <description>Writing a 1 disables the VELC_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DIR_INT</name>
                            <description>Writing a 1 disables the DIR_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INT</name>
                            <description>Writing a 1 disables the ERR_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>ENCLK_INT</name>
                            <description>Writing a 1 disables the ENCLK_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>POS0_INT</name>
                            <description>Writing a 1 disables the POS0_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>POS1_INT</name>
                            <description>Writing a 1 disables the POS1_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>POS2_INT</name>
                            <description>Writing a 1 disables the POS2_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>REV0_INT</name>
                            <description>Writing a 1 disables the REV0_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>POS0REV_INT</name>
                            <description>Writing a 1 disables the POS0REV_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>POS1REV_INT</name>
                            <description>Writing a 1 disables the POS1REV_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>POS2REV_INT</name>
                            <description>Writing a 1 disables the POS2REV_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>REV1_INT</name>
                            <description>Writing a 1 disables the REV1_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>REV2_INT</name>
                            <description>Writing a 1 disables the REV2_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>MAXPOS_INT</name>
                            <description>Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE
                                register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>SYSCON</name>
            <description>System and clock control</description>
            <groupName>SYSCON</groupName>
            <baseAddress>0x400FC000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>EINT0</name>
                <value>18</value>
            </interrupt>
            <interrupt>
                <name>EINT1</name>
                <value>19</value>
            </interrupt>
            <interrupt>
                <name>EINT2</name>
                <value>20</value>
            </interrupt>
            <interrupt>
                <name>EINT3</name>
                <value>21</value>
            </interrupt>
            <interrupt>
                <name>BOD</name>
                <value>23</value>
            </interrupt>
            <interrupt>
                <name>PLL0</name>
                <value>16</value>
            </interrupt>
            <interrupt>
                <name>PLL1</name>
                <value>32</value>
            </interrupt>
            <registers>
                <register>
                    <name>FLASHCFG</name>
                    <description>Flash Accelerator Configuration Register. Controls flash access
                        timing.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x303A</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not change these bits from
                                the reset value.</description>
                            <bitRange>[11:0]</bitRange>
                        </field>
                        <field>
                            <name>FLASHTIM</name>
                            <description>Flash access time. The value of this field plus 1 gives the
                                number of CPU clocks used for a flash access. Warning: improper
                                setting of this value may result in incorrect operation of the
                                device. Other values are reserved.</description>
                            <bitRange>[15:12]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>1CLK</name>
                                    <description>Flash accesses use 1 CPU clock. Use for up to 20
                                        MHz CPU clock.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>2CLK</name>
                                    <description>Flash accesses use 2 CPU clocks. Use for up to 40
                                        MHz CPU clock.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>3CLK</name>
                                    <description>Flash accesses use 3 CPU clocks. Use for up to 60
                                        MHz CPU clock.</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>4CLK</name>
                                    <description>Flash accesses use 4 CPU clocks. Use for up to 80
                                        MHz CPU clock.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>5CLK</name>
                                    <description>Flash accesses use 5 CPU clocks. Use for up to 100
                                        MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769
                                        only.</description>
                                    <value>0x4</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>6CLK</name>
                                    <description>Flash accesses use 6 CPU clocks. This safe setting
                                        will work under any conditions.</description>
                                    <value>0x5</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PLL0CON</name>
                    <description>PLL0 Control Register</description>
                    <addressOffset>0x080</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PLLE0</name>
                            <description>PLL0 Enable. When one, and after a valid PLL0 feed, this
                                bit will activate PLL0 and allow it to lock to the requested
                                frequency. See PLL0STAT register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PLLC0</name>
                            <description>PLL0 Connect. Setting PLLC0 to one after PLL0 has been
                                enabled and locked, then followed by a valid PLL0 feed sequence
                                causes PLL0 to become the clock source for the CPU, AHB peripherals,
                                and used to derive the clocks for APB peripherals. The PLL0 output
                                may potentially be used to clock the USB subsystem if the frequency
                                is 48 MHz. See PLL0STAT register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PLL0CFG</name>
                    <description>PLL0 Configuration Register</description>
                    <addressOffset>0x084</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MSEL0</name>
                            <description>PLL0 Multiplier value. Supplies the value M in PLL0
                                frequency calculations. The value stored here is M - 1. Note: Not
                                all values of M are needed, and therefore some are not supported by
                                hardware.</description>
                            <bitRange>[14:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>NSEL0</name>
                            <description>PLL0 Pre-Divider value. Supplies the value N in PLL0
                                frequency calculations. The value stored here is N - 1. Supported
                                values for N are 1 through 32.</description>
                            <bitRange>[23:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PLL0STAT</name>
                    <description>PLL0 Status Register</description>
                    <addressOffset>0x088</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MSEL0</name>
                            <description>Read-back for the PLL0 Multiplier value. This is the value
                                currently used by PLL0, and is one less than the actual multiplier.</description>
                            <bitRange>[14:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>NSEL0</name>
                            <description>Read-back for the PLL0 Pre-Divider value. This is the value
                                currently used by PLL0, and is one less than the actual divider.</description>
                            <bitRange>[23:16]</bitRange>
                        </field>
                        <field>
                            <name>PLLE0_STAT</name>
                            <description>Read-back for the PLL0 Enable bit. This bit reflects the
                                state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one,
                                PLL0 is currently enabled. When zero, PLL0 is turned off. This bit
                                is automatically cleared when Power-down mode is entered.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>PLLC0_STAT</name>
                            <description>Read-back for the PLL0 Connect bit. This bit reflects the
                                state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When
                                PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source
                                for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed.
                                This bit is automatically cleared when Power-down mode is entered.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>PLOCK0</name>
                            <description>Reflects the PLL0 Lock status. When zero, PLL0 is not
                                locked. When one, PLL0 is locked onto the requested frequency. See
                                text for details.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:27]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PLL0FEED</name>
                    <description>PLL0 Feed Register</description>
                    <addressOffset>0x08C</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>PLL0FEED</name>
                            <description>The PLL0 feed sequence must be written to this register in
                                order for PLL0 configuration and control register changes to take
                                effect.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PLL1CON</name>
                    <description>PLL1 Control Register</description>
                    <addressOffset>0x0A0</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PLLE1</name>
                            <description>PLL1 Enable. When one, and after a valid PLL1 feed, this
                                bit will activate PLL1 and allow it to lock to the requested
                                frequency.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PLLC1</name>
                            <description>PLL1 Connect. Setting PLLC to one after PLL1 has been
                                enabled and locked, then followed by a valid PLL1 feed sequence
                                causes PLL1 to become the clock source for the USB subsystem via the
                                USB clock divider. See PLL1STAT register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PLL1CFG</name>
                    <description>PLL1 Configuration Register</description>
                    <addressOffset>0x0A4</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MSEL1</name>
                            <description>PLL1 Multiplier value. Supplies the value M in the PLL1
                                frequency calculations.</description>
                            <bitRange>[4:0]</bitRange>
                        </field>
                        <field>
                            <name>PSEL1</name>
                            <description>PLL1 Divider value. Supplies the value P in the PLL1
                                frequency calculations.</description>
                            <bitRange>[6:5]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:7]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PLL1STAT</name>
                    <description>PLL1 Status Register</description>
                    <addressOffset>0x0A8</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MSEL1</name>
                            <description>Read-back for the PLL1 Multiplier value. This is the value
                                currently used by PLL1.</description>
                            <bitRange>[4:0]</bitRange>
                        </field>
                        <field>
                            <name>PSEL1</name>
                            <description>Read-back for the PLL1 Divider value. This is the value
                                currently used by PLL1.</description>
                            <bitRange>[6:5]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>PLLE1_STAT</name>
                            <description>Read-back for the PLL1 Enable bit. When one, PLL1 is
                                currently activated. When zero, PLL1 is turned off. This bit is
                                automatically cleared when Power-down mode is activated.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>PLLC1_STAT</name>
                            <description>Read-back for the PLL1 Connect bit. When PLLC and PLLE are
                                both one, PLL1 is connected as the clock source for the
                                microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed
                                and the oscillator clock is used directly by the microcontroller.
                                This bit is automatically cleared when Power-down mode is activated.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PLOCK1</name>
                            <description>Reflects the PLL1 Lock status. When zero, PLL1 is not
                                locked. When one, PLL1 is locked onto the requested frequency.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:11]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PLL1FEED</name>
                    <description>PLL1 Feed Register</description>
                    <addressOffset>0x0AC</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>PLL1FEED</name>
                            <description>The PLL1 feed sequence must be written to this register in
                                order for PLL1 configuration and control register changes to take
                                effect.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PCON</name>
                    <description>Power Control Register</description>
                    <addressOffset>0x0C0</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PM0</name>
                            <description>Power mode control bit 0. This bit controls entry to the
                                Power-down mode.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PM1</name>
                            <description>Power mode control bit 1. This bit controls entry to the
                                Deep Power-down mode.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>BODRPM</name>
                            <description>Brown-Out Reduced Power Mode. When BODRPM is 1, the
                                Brown-Out Detect circuitry will be turned off when chip Power-down
                                mode or Deep Sleep mode is entered, resulting in a further reduction
                                in power usage. However, the possibility of using Brown-Out Detect
                                as a wake-up source from the reduced power mode will be lost. When
                                0, the Brown-Out Detect function remains active during Power-down
                                and Deep Sleep modes. See the System Control Block chapter for
                                details of Brown-Out detection.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>BOGD</name>
                            <description>Brown-Out Global Disable. When BOGD is 1, the Brown-Out
                                Detect circuitry is fully disabled at all times, and does not
                                consume power. When 0, the Brown-Out Detect circuitry is enabled.
                                See the System Control Block chapter for details of Brown-Out
                                detection. Note: the Brown-Out Reset Disable (BORD, in this
                                register) and the Brown-Out Interrupt (xx) must be disabled when
                                software changes the value of this bit.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>BORD</name>
                            <description>Brown-Out Reset Disable. When BORD is 1, the BOD will not
                                reset the device when the VDD(REG)(3V3) voltage dips goes below the
                                BOD reset trip level. The Brown-Out interrupt is not affected. When
                                BORD is 0, the BOD reset is enabled.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[7:3]</bitRange>
                        </field>
                        <field>
                            <name>SMFLAG</name>
                            <description>Sleep Mode entry flag. Set when the Sleep mode is
                                successfully entered. Cleared by software writing a one to this bit.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>DSFLAG</name>
                            <description>Deep Sleep entry flag. Set when the Deep Sleep mode is
                                successfully entered. Cleared by software writing a one to this bit.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PDFLAG</name>
                            <description>Power-down entry flag. Set when the Power-down mode is
                                successfully entered. Cleared by software writing a one to this bit.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>DPDFLAG</name>
                            <description>Deep Power-down entry flag. Set when the Deep Power-down
                                mode is successfully entered. Cleared by software writing a one to
                                this bit.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PCONP</name>
                    <description>Power Control for Peripherals Register</description>
                    <addressOffset>0x0C4</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x03BE</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PCTIM0</name>
                            <description>Timer/Counter 0 power/clock control bit.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>PCTIM1</name>
                            <description>Timer/Counter 1 power/clock control bit.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PCUART0</name>
                            <description>UART0 power/clock control bit.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>PCUART1</name>
                            <description>UART1 power/clock control bit.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>PCPWM1</name>
                            <description>PWM1 power/clock control bit.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>PCI2C0</name>
                            <description>The I2C0 interface power/clock control bit.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>PCSPI</name>
                            <description>The SPI interface power/clock control bit.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>PCRTC</name>
                            <description>The RTC power/clock control bit.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PCSSP1</name>
                            <description>The SSP 1 interface power/clock control bit.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>PCADC</name>
                            <description>A/D converter (ADC) power/clock control bit. Note: Clear
                                the PDN bit in the AD0CR before clearing this bit, and set this bit
                                before setting PDN.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>PCCAN1</name>
                            <description>CAN Controller 1 power/clock control bit.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>PCCAN2</name>
                            <description>CAN Controller 2 power/clock control bit.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>PCGPIO</name>
                            <description>Power/clock control bit for IOCON, GPIO, and GPIO
                                interrupts.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>PCRIT</name>
                            <description>Repetitive Interrupt Timer power/clock control bit.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>PCMCPWM</name>
                            <description>Motor Control PWM</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>PCQEI</name>
                            <description>Quadrature Encoder Interface power/clock control bit.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>PCI2C1</name>
                            <description>The I2C1 interface power/clock control bit.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>PCSSP0</name>
                            <description>The SSP0 interface power/clock control bit.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>PCTIM2</name>
                            <description>Timer 2 power/clock control bit.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>PCTIM3</name>
                            <description>Timer 3 power/clock control bit.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>PCUART2</name>
                            <description>UART 2 power/clock control bit.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>PCUART3</name>
                            <description>UART 3 power/clock control bit.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>PCI2C2</name>
                            <description>I2C interface 2 power/clock control bit.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>PCI2S</name>
                            <description>I2S interface power/clock control bit.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>PCGPDMA</name>
                            <description>GPDMA function power/clock control bit.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>PCENET</name>
                            <description>Ethernet block power/clock control bit.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>PCUSB</name>
                            <description>USB interface power/clock control bit.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CCLKCFG</name>
                    <description>CPU Clock Configuration Register</description>
                    <addressOffset>0x104</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CCLKSEL</name>
                            <description>Selects the divide value for creating the CPU clock (CCLK)
                                from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU
                                clock. This setting is not allowed when the PLL0 is connected,
                                because the rate would always be greater than the maximum allowed
                                CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This
                                setting is not allowed when the PLL0 is connected, because the rate
                                would always be greater than the maximum allowed CPU clock. 2 =
                                pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is
                                divided by 4 to produce the CPU clock. ... 255 = pllclk is divided
                                by 256 to produce the CPU clock.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>USBCLKCFG</name>
                    <description>USB Clock Configuration Register</description>
                    <addressOffset>0x108</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>USBSEL</name>
                            <description>Selects the divide value for creating the USB clock from
                                the PLL0 output. Only the values shown below can produce even number
                                multiples of 48 MHz from the PLL0 output. Warning: Improper setting
                                of this value will result in incorrect operation of the USB
                                interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288
                                MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9
                                = PLL0 output is divided by 10. PLL0 output must be 480 MHz.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CLKSRCSEL</name>
                    <description>Clock Source Select Register</description>
                    <addressOffset>0x10C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CLKSRC</name>
                            <description>Selects the clock source for PLL0 as follows. Warning:
                                Improper setting of this value, or an incorrect sequence of changing
                                this value may result in incorrect operation of the device.</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SELECTS_THE_INTERNAL</name>
                                    <description>Selects the Internal RC oscillator as the PLL0
                                        clock source (default).</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECTS_THE_MAIN_OSC</name>
                                    <description>Selects the main oscillator as the PLL0 clock
                                        source. Select the main oscillator as PLL0 clock source if
                                        the PLL0 clock output is used for USB or for CAN with
                                        baudrates > 100 kBit/s.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECTS_THE_RTC_OSCI</name>
                                    <description>Selects the RTC oscillator as the PLL0 clock
                                        source.</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESERVED</name>
                                    <description>Reserved, do not use this setting.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CANSLEEPCLR</name>
                    <description>Allows clearing the current CAN channel sleep state as well as
                        reading that state.</description>
                    <addressOffset>0x110</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>CAN1SLEEP</name>
                            <description>Sleep status and control for CAN channel 1. Read: when 1,
                                indicates that CAN channel 1 is in the sleep mode. Write: writing a
                                1 causes clocks to be restored to CAN channel 1.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>CAN2SLEEP</name>
                            <description>Sleep status and control for CAN channel 2. Read: when 1,
                                indicates that CAN channel 2 is in the sleep mode. Write: writing a
                                1 causes clocks to be restored to CAN channel 2.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CANWAKEFLAGS</name>
                    <description>Allows reading the wake-up state of the CAN channels.</description>
                    <addressOffset>0x114</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>CAN1WAKE</name>
                            <description>Wake-up status for CAN channel 1. Read: when 1, indicates
                                that a falling edge has occurred on the receive data line of CAN
                                channel 1. Write: writing a 1 clears this bit.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>CAN2WAKE</name>
                            <description>Wake-up status for CAN channel 2. Read: when 1, indicates
                                that a falling edge has occurred on the receive data line of CAN
                                channel 2. Write: writing a 1 clears this bit.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EXTINT</name>
                    <description>External Interrupt Flag Register</description>
                    <addressOffset>0x140</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EINT0</name>
                            <description>In level-sensitive mode, this bit is set if the EINT0
                                function is selected for its pin, and the pin is in its active
                                state. In edge-sensitive mode, this bit is set if the EINT0 function
                                is selected for its pin, and the selected edge occurs on the pin.
                                This bit is cleared by writing a one to it, except in level
                                sensitive mode when the pin is in its active state.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EINT1</name>
                            <description>In level-sensitive mode, this bit is set if the EINT1
                                function is selected for its pin, and the pin is in its active
                                state. In edge-sensitive mode, this bit is set if the EINT1 function
                                is selected for its pin, and the selected edge occurs on the pin.
                                This bit is cleared by writing a one to it, except in level
                                sensitive mode when the pin is in its active state.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EINT2</name>
                            <description>In level-sensitive mode, this bit is set if the EINT2
                                function is selected for its pin, and the pin is in its active
                                state. In edge-sensitive mode, this bit is set if the EINT2 function
                                is selected for its pin, and the selected edge occurs on the pin.
                                This bit is cleared by writing a one to it, except in level
                                sensitive mode when the pin is in its active state.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EINT3</name>
                            <description>In level-sensitive mode, this bit is set if the EINT3
                                function is selected for its pin, and the pin is in its active
                                state. In edge-sensitive mode, this bit is set if the EINT3 function
                                is selected for its pin, and the selected edge occurs on the pin.
                                This bit is cleared by writing a one to it, except in level
                                sensitive mode when the pin is in its active state.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EXTMODE</name>
                    <description>External Interrupt Mode register</description>
                    <addressOffset>0x148</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EXTMODE0</name>
                            <description>External interrupt 0 EINT0 mode.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LEVEL_SENSITIVE</name>
                                    <description>Level-sensitive. Level-sensitivity is selected for
                                        EINT0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EDGE_SENSITIVE</name>
                                    <description>Edge-sensitive. EINT0 is edge sensitive.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EXTMODE1</name>
                            <description>External interrupt 1 EINT1 mode.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LEVEL_SENSITIVE</name>
                                    <description>Level-sensitive. Level-sensitivity is selected for
                                        EINT1.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EDGE_SENSITIVE</name>
                                    <description>Edge-sensitive. EINT1 is edge sensitive.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EXTMODE2</name>
                            <description>External interrupt 2 EINT2 mode.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LEVEL_SENSITIVE</name>
                                    <description>Level-sensitive. Level-sensitivity is selected for
                                        EINT2.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EDGE_SENSITIVE</name>
                                    <description>Edge-sensitive. EINT2 is edge sensitive.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EXTMODE3</name>
                            <description>External interrupt 3 EINT3 mode.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LEVEL_SENSITIVE</name>
                                    <description>Level-sensitive. Level-sensitivity is selected for
                                        EINT3.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EDGE_SENSITIVE</name>
                                    <description>Edge-sensitive. EINT3 is edge sensitive.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EXTPOLAR</name>
                    <description>External Interrupt Polarity Register</description>
                    <addressOffset>0x14C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EXTPOLAR0</name>
                            <description>External interrupt 0 EINT0 polarity.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>FALLING_EDGE</name>
                                    <description>Falling edge. EINT0 is low-active or falling-edge
                                        sensitive (depending on EXTMODE0).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING_EDGE</name>
                                    <description>Rising edge. EINT0 is high-active or rising-edge
                                        sensitive (depending on EXTMODE0).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EXTPOLAR1</name>
                            <description>External interrupt 1 EINT1 polarity.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>FALLING_EDGE</name>
                                    <description>Falling edge. EINT1 is low-active or falling-edge
                                        sensitive (depending on EXTMODE1).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING_EDGE</name>
                                    <description>Rising edge. EINT1 is high-active or rising-edge
                                        sensitive (depending on EXTMODE1).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EXTPOLAR2</name>
                            <description>External interrupt 2 EINT2 polarity.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>FALLING_EDGE</name>
                                    <description>Falling edge. EINT2 is low-active or falling-edge
                                        sensitive (depending on EXTMODE2).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING_EDGE</name>
                                    <description>Rising edge. EINT2 is high-active or rising-edge
                                        sensitive (depending on EXTMODE2).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EXTPOLAR3</name>
                            <description>External interrupt 3 EINT3 polarity.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>FALLING_EDGE</name>
                                    <description>Falling edge. EINT3 is low-active or falling-edge
                                        sensitive (depending on EXTMODE3).</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RISING_EDGE</name>
                                    <description>Rising edge. EINT3 is high-active or rising-edge
                                        sensitive (depending on EXTMODE3).</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RSID</name>
                    <description>Reset Source Identification Register</description>
                    <addressOffset>0x180</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>POR</name>
                            <description>Assertion of the POR signal sets this bit, and clears all
                                of the other bits in this register. But if another Reset signal
                                (e.g., External Reset) remains asserted after the POR signal is
                                negated, then its bit is set. This bit is not affected by any of the
                                other sources of Reset.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EXTR</name>
                            <description>Assertion of the RESET signal sets this bit. This bit is
                                cleared only by software or POR.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>WDTR</name>
                            <description>This bit is set when the Watchdog Timer times out and the
                                WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared
                                only by software or POR.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>BODR</name>
                            <description>This bit is set when the VDD(REG)(3V3) voltage reaches a
                                level below the BOD reset trip level (typically 1.85 V under nominal
                                room temperature conditions). If the VDD(REG)(3V3) voltage dips from
                                the normal operating range to below the BOD reset trip level and
                                recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3)
                                voltage dips from the normal operating range to below the BOD reset
                                trip level and continues to decline to the level at which POR is
                                asserted (nominally 1 V), the BODR bit is cleared. If the
                                VDD(REG)(3V3) voltage rises continuously from below 1 V to a level
                                above the BOD reset trip level, the BODR will be set to 1. This bit
                                is cleared only by software or POR. Note: Only in the case where a
                                reset occurs and the POR = 0, the BODR bit indicates if the
                                VDD(REG)(3V3) voltage was below the BOD reset trip level or not.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SCS</name>
                    <description>System control and status</description>
                    <addressOffset>0x1A0</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. User software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>OSCRANGE</name>
                            <description>Main oscillator range select.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LOW</name>
                                    <description>Low. The frequency range of the main oscillator is
                                        1 MHz to 20 MHz.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>HIGH</name>
                                    <description>High. The frequency range of the main oscillator is
                                        15 MHz to 25 MHz.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>OSCEN</name>
                            <description>Main oscillator enable.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED</name>
                                    <description>Disabled. The main oscillator is disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED</name>
                                    <description>Enabled.The main oscillator is enabled, and will
                                        start up if the correct external circuitry is connected to
                                        the XTAL1 and XTAL2 pins.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>OSCSTAT</name>
                            <description>Main oscillator status.</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NOT_READY</name>
                                    <description>Not ready. The main oscillator is not ready to be
                                        used as a clock source.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>READY</name>
                                    <description>Ready. The main oscillator is ready to be used as a
                                        clock source. The main oscillator must be enabled via the
                                        OSCEN bit.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. User software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:7]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PCLKSEL0</name>
                    <description>Peripheral Clock Selection register 0.</description>
                    <addressOffset>0x1A8</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PCLK_WDT</name>
                            <description>Peripheral clock selection for WDT.</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_TIMER0</name>
                            <description>Peripheral clock selection for TIMER0.</description>
                            <bitRange>[3:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_TIMER1</name>
                            <description>Peripheral clock selection for TIMER1.</description>
                            <bitRange>[5:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_UART0</name>
                            <description>Peripheral clock selection for UART0.</description>
                            <bitRange>[7:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_UART1</name>
                            <description>Peripheral clock selection for UART1.</description>
                            <bitRange>[9:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[11:10]</bitRange>
                        </field>
                        <field>
                            <name>PCLK_PWM1</name>
                            <description>Peripheral clock selection for PWM1.</description>
                            <bitRange>[13:12]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_I2C0</name>
                            <description>Peripheral clock selection for I2C0.</description>
                            <bitRange>[15:14]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_SPI</name>
                            <description>Peripheral clock selection for SPI.</description>
                            <bitRange>[17:16]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[19:18]</bitRange>
                        </field>
                        <field>
                            <name>PCLK_SSP1</name>
                            <description>Peripheral clock selection for SSP1.</description>
                            <bitRange>[21:20]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_DAC</name>
                            <description>Peripheral clock selection for DAC.</description>
                            <bitRange>[23:22]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_ADC</name>
                            <description>Peripheral clock selection for ADC.</description>
                            <bitRange>[25:24]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_CAN1</name>
                            <description>Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2
                                must have the same PCLK divide value when the CAN function is used.</description>
                            <bitRange>[27:26]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_6</name>
                                    <description>CCLK div 6. PCLK_peripheral = CCLK/6.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_CAN2</name>
                            <description>Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2
                                must have the same PCLK divide value when the CAN function is used.</description>
                            <bitRange>[29:28]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_6</name>
                                    <description>CCLK div 6. PCLK_peripheral = CCLK/6,</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_ACF</name>
                            <description>Peripheral clock selection for CAN acceptance
                                filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide
                                value when the CAN function is used.</description>
                            <bitRange>[31:30]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_6</name>
                                    <description>CCLK div 6. PCLK_peripheral = CCLK/6</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PCLKSEL1</name>
                    <description>Peripheral Clock Selection register 1.</description>
                    <addressOffset>0x1AC</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PCLK_QEI</name>
                            <description>Peripheral clock selection for the Quadrature Encoder
                                Interface.</description>
                            <bitRange>[1:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_GPIOINT</name>
                            <description>Peripheral clock selection for GPIO interrupts.</description>
                            <bitRange>[3:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_PCB</name>
                            <description>Peripheral clock selection for the Pin Connect block.</description>
                            <bitRange>[5:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_I2C1</name>
                            <description>Peripheral clock selection for I2C1.</description>
                            <bitRange>[7:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[9:8]</bitRange>
                        </field>
                        <field>
                            <name>PCLK_SSP0</name>
                            <description>Peripheral clock selection for SSP0.</description>
                            <bitRange>[11:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_TIMER2</name>
                            <description>Peripheral clock selection for TIMER2.</description>
                            <bitRange>[13:12]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_TIMER3</name>
                            <description>Peripheral clock selection for TIMER3.</description>
                            <bitRange>[15:14]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_UART2</name>
                            <description>Peripheral clock selection for UART2.</description>
                            <bitRange>[17:16]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_UART3</name>
                            <description>Peripheral clock selection for UART3.</description>
                            <bitRange>[19:18]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_I2C2</name>
                            <description>Peripheral clock selection for I2C2.</description>
                            <bitRange>[21:20]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_I2S</name>
                            <description>Peripheral clock selection for I2S.</description>
                            <bitRange>[23:22]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved.</description>
                            <bitRange>[25:24]</bitRange>
                        </field>
                        <field>
                            <name>PCLK_RIT</name>
                            <description>Peripheral clock selection for Repetitive Interrupt Timer.</description>
                            <bitRange>[27:26]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_SYSCON</name>
                            <description>Peripheral clock selection for the System Control block.</description>
                            <bitRange>[29:28]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PCLK_MC</name>
                            <description>Peripheral clock selection for the Motor Control PWM.</description>
                            <bitRange>[31:30]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>CCLK_DIV_4</name>
                                    <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK</name>
                                    <description>CCLK. PCLK_peripheral = CCLK</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_2</name>
                                    <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>CCLK_DIV_8</name>
                                    <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>USBINTST</name>
                    <description>USB Interrupt Status</description>
                    <addressOffset>0x1C0</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x80000000</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>USB_INT_REQ_LP</name>
                            <description>Low priority interrupt line status. This bit is read-only.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>USB_INT_REQ_HP</name>
                            <description>High priority interrupt line status. This bit is read-only.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>USB_INT_REQ_DMA</name>
                            <description>DMA interrupt line status. This bit is read-only.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>USB_HOST_INT</name>
                            <description>USB host interrupt line status. This bit is read-only.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>USB_ATX_INT</name>
                            <description>External ATX interrupt line status. This bit is read-only.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>USB_OTG_INT</name>
                            <description>OTG interrupt line status. This bit is read-only.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>USB_I2C_INT</name>
                            <description>I2C module interrupt line status. This bit is read-only.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>USB_NEED_CLK</name>
                            <description>USB need clock indicator. This bit is read-only. This bit
                                is set to 1 when USB activity or a change of state on the USB data
                                pins is detected, and it indicates that a PLL supplied clock of 48
                                MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms
                                after the last packet has been received/sent, or 2 ms after the
                                Suspend Change (SUS_CH) interrupt has occurred. A change of this bit
                                from 0 to 1 can wake up the microcontroller if activity on the USB
                                bus is selected to wake up the part from the Power-down mode (see
                                Section 4.7.9 Wake-up from Reduced Power Modes for details). Also
                                see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power
                                Control for Peripherals register (PCONP - 0x400F C0C4) for
                                considerations about the PLL and invoking the Power-down mode. This
                                bit is read-only.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[30:9]</bitRange>
                        </field>
                        <field>
                            <name>EN_USB_INTS</name>
                            <description>Enable all USB interrupts. When this bit is cleared, the
                                NVIC does not see the ORed output of the USB interrupt lines.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DMACREQSEL</name>
                    <description>Selects between alternative requests on DMA channels 0 through 7
                        and 10 through 15</description>
                    <addressOffset>0x1C4</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DMASEL08</name>
                            <description>Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 -
                                Timer 0 match 0 is selected.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>DMASEL09</name>
                            <description>Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 -
                                Timer 0 match 1 is selected.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>DMASEL10</name>
                            <description>Selects the DMA request for GPDMA input 10: 0 - uart1 tx is
                                selected. 1 - Timer 1 match 0 is selected.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DMASEL11</name>
                            <description>Selects the DMA request for GPDMA input 11: 0 - uart1 rx is
                                selected. 1 - Timer 1 match 1 is selected.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>DMASEL12</name>
                            <description>Selects the DMA request for GPDMA input 12: 0 - uart2 tx is
                                selected. 1 - Timer 2 match 0 is selected.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>DMASEL13</name>
                            <description>Selects the DMA request for GPDMA input 13: 0 - uart2 rx is
                                selected. 1 - Timer 2 match 1 is selected.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>DMASEL14</name>
                            <description>Selects the DMA request for GPDMA input 14: 0 - uart3 tx is
                                selected. 1 - I2S channel 0 is selected.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>DMASEL15</name>
                            <description>Selects the DMA request for GPDMA input 15: 0 - uart3 rx is
                                selected. 1 - I2S channel 1 is selected.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CLKOUTCFG</name>
                    <description>Clock Output Configuration Register</description>
                    <addressOffset>0x1C8</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CLKOUTSEL</name>
                            <description>Selects the clock source for the CLKOUT function. Other
                                values are reserved. Do not use.</description>
                            <bitRange>[3:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>SELECTS_THE_CPU_CLOC</name>
                                    <description>Selects the CPU clock as the CLKOUT source.</description>
                                    <value>0x0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECTS_THE_MAIN_OSC</name>
                                    <description>Selects the main oscillator as the CLKOUT source.</description>
                                    <value>0x1</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECTS_THE_INTERNAL</name>
                                    <description>Selects the Internal RC oscillator as the CLKOUT
                                        source.</description>
                                    <value>0x2</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECTS_THE_USB_CLOC</name>
                                    <description>Selects the USB clock as the CLKOUT source.</description>
                                    <value>0x3</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>SELECTS_THE_RTC_OSCI</name>
                                    <description>Selects the RTC oscillator as the CLKOUT source.</description>
                                    <value>0x4</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CLKOUTDIV</name>
                            <description>Integer value to divide the output clock by, minus one. 0 =
                                Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is
                                divided by 3. ... 15 = Clock is divided by 16.</description>
                            <bitRange>[7:4]</bitRange>
                        </field>
                        <field>
                            <name>CLKOUT_EN</name>
                            <description>CLKOUT enable control, allows switching the CLKOUT source
                                without glitches. Clear to stop CLKOUT on the next falling edge. Set
                                to enable CLKOUT.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>CLKOUT_ACT</name>
                            <description>CLKOUT activity indication. Reads as 1 when CLKOUT is
                                enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN
                                bit and the clock has completed being stopped.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved, user software should not write ones to reserved
                                bits. The value read from a reserved bit is not defined.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>EMAC</name>
            <description>Ethernet</description>
            <groupName>ETHERNET</groupName>
            <baseAddress>0x50000000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>ENET</name>
                <value>28</value>
            </interrupt>
            <registers>
                <register>
                    <name>MAC1</name>
                    <description>MAC configuration register 1.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x8000</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXENABLE</name>
                            <description>RECEIVE ENABLE. Set this to allow receive frames to be
                                received. Internally the MAC synchronizes this control bit to the
                                incoming receive stream.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PARF</name>
                            <description>PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC
                                will pass all frames regardless of type (normal vs. Control). When
                                disabled, the MAC does not pass valid Control frames.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RXFLOWCTRL</name>
                            <description>RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon
                                received PAUSE Flow Control frames. When disabled, received PAUSE
                                Flow Control frames are ignored.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>TXFLOWCTRL</name>
                            <description>TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow
                                Control frames are allowed to be transmitted. When disabled, Flow
                                Control frames are blocked.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>LOOPBACK</name>
                            <description>Setting this bit will cause the MAC Transmit interface to
                                be looped back to the MAC Receive interface. Clearing this bit
                                results in normal operation.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[7:5]</bitRange>
                        </field>
                        <field>
                            <name>RESETTX</name>
                            <description>Setting this bit will put the Transmit Function logic in
                                reset.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>RESETMCSTX</name>
                            <description>Setting this bit resets the MAC Control Sublayer / Transmit
                                logic. The MCS logic implements flow control.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESETRX</name>
                            <description>Setting this bit will put the Ethernet receive logic in
                                reset.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESETMCSRX</name>
                            <description>Setting this bit resets the MAC Control Sublayer / Receive
                                logic. The MCS logic implements flow control.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[13:12]</bitRange>
                        </field>
                        <field>
                            <name>SIMRESET</name>
                            <description>SIMULATION RESET. Setting this bit will cause a reset to
                                the random number generator within the Transmit Function.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>SOFTRESET</name>
                            <description>SOFT RESET. Setting this bit will put all modules within
                                the MAC in reset except the Host Interface.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MAC2</name>
                    <description>MAC configuration register 2.</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FULLDUPLEX</name>
                            <description>When enabled (set to 1), the MAC operates in Full-Duplex
                                mode. When disabled, the MAC operates in Half-Duplex mode.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>FLC</name>
                            <description>FRAMELENGTH CHECKING. When enabled (set to 1), both
                                transmit and receive frame lengths are compared to the Length/Type
                                field. If the Length/Type field represents a length then the check
                                is performed. Mismatches are reported in the StatusInfo word for
                                each received frame.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>HFEN</name>
                            <description>HUGE FRAME ENABLEWhen enabled (set to 1), frames of any
                                length are transmitted and received.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DELAYEDCRC</name>
                            <description>DELAYED CRC. This bit determines the number of bytes, if
                                any, of proprietary header information that exist on the front of
                                IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC
                                function) are added. When 0, there is no proprietary header.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CRCEN</name>
                            <description>CRC ENABLESet this bit to append a CRC to every frame
                                whether padding was required or not. Must be set if PAD/CRC ENABLE
                                is set. Clear this bit if frames presented to the MAC contain a CRC.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>PADCRCEN</name>
                            <description>PAD CRC ENABLE. Set this bit to have the MAC pad all short
                                frames. Clear this bit if frames presented to the MAC have a valid
                                length. This bit is used in conjunction with AUTO PAD ENABLE and
                                VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the
                                pad function.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>VLANPADEN</name>
                            <description>VLAN PAD ENABLE. Set this bit to cause the MAC to pad all
                                short frames to 64 bytes and append a valid CRC. Consult Table 153 -
                                Pad Operation for more information on the various padding features.
                                Note: This bit is ignored if PAD / CRC ENABLE is cleared.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>AUTODETPADEN</name>
                            <description>AUTODETECTPAD ENABLE. Set this bit to cause the MAC to
                                automatically detect the type of frame, either tagged or un-tagged,
                                by comparing the two octets following the source address with 0x8100
                                (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation
                                provides a description of the pad function based on the
                                configuration of this register. Note: This bit is ignored if PAD /
                                CRC ENABLE is cleared.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>PPENF</name>
                            <description>PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC
                                will verify the content of the preamble to ensure it contains 0x55
                                and is error-free. A packet with an incorrect preamble is discarded.
                                When disabled, no preamble checking is performed.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>LPENF</name>
                            <description>LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC
                                only allows receive packets which contain preamble fields less than
                                12 bytes in length. When disabled, the MAC allows any length
                                preamble as per the Standard.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[11:10]</bitRange>
                        </field>
                        <field>
                            <name>NOBACKOFF</name>
                            <description>When enabled (set to 1), the MAC will immediately
                                retransmit following a collision rather than using the Binary
                                Exponential Backoff algorithm as specified in the Standard.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>BP_NOBACKOFF</name>
                            <description>BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after
                                the MAC incidentally causes a collision during back pressure, it
                                will immediately retransmit without backoff, reducing the chance of
                                further collisions and ensuring transmit packets get sent.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EXCESSDEFER</name>
                            <description>When enabled (set to 1) the MAC will defer to carrier
                                indefinitely as per the Standard. When disabled, the MAC will abort
                                when the excessive deferral limit is reached.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:15]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IPGT</name>
                    <description>Back-to-Back Inter-Packet-Gap register.</description>
                    <addressOffset>0x008</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>BTOBINTEGAP</name>
                            <description>BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field
                                representing the nibble time offset of the minimum possible period
                                between the end of any transmitted packet to the beginning of the
                                next. In Full-Duplex mode, the register value should be the desired
                                period in nibble times minus 3. In Half-Duplex mode, the register
                                value should be the desired period in nibble times minus 6. In
                                Full-Duplex the recommended setting is 0x15 (21d), which represents
                                the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps
                                mode). In Half-Duplex the recommended setting is 0x12 (18d), which
                                also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6
                                us (in 10 Mbps mode).</description>
                            <bitRange>[6:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:7]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>IPGR</name>
                    <description>Non Back-to-Back Inter-Packet-Gap register.</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>NBTOBINTEGAP2</name>
                            <description>NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a
                                programmable field representing the Non-Back-to-Back
                                Inter-Packet-Gap. The recommended value is 0x12 (18d), which
                                represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us
                                (in 10 Mbps mode).</description>
                            <bitRange>[6:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>NBTOBINTEGAP1</name>
                            <description>NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a
                                programmable field representing the optional carrierSense window
                                referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier
                                is detected during the timing of IPGR1, the MAC defers to carrier.
                                If, however, carrier becomes active after IPGR1, the MAC continues
                                timing IPGR2 and transmits, knowingly causing a collision, thus
                                ensuring fair access to medium. Its range of values is 0x0 to IPGR2.
                                The recommended value is 0xC (12d)</description>
                            <bitRange>[14:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:15]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CLRT</name>
                    <description>Collision window / Retry register.</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x370F</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RETRANSMAX</name>
                            <description>RETRANSMISSION MAXIMUM.This is a programmable field
                                specifying the number of retransmission attempts following a
                                collision before aborting the packet due to excessive collisions.
                                The Standard specifies the attemptLimit to be 0xF (15d). See IEEE
                                802.3/4.2.3.2.5.</description>
                            <bitRange>[3:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[7:4]</bitRange>
                        </field>
                        <field>
                            <name>COLLWIN</name>
                            <description>COLLISION WINDOW. This is a programmable field representing
                                the slot time or collision window during which collisions occur in
                                properly configured networks. The default value of 0x37 (55d)
                                represents a 56 byte window following the preamble and SFD.</description>
                            <bitRange>[13:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:14]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MAXF</name>
                    <description>Maximum Frame register.</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x0600</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MAXFLEN</name>
                            <description>MAXIMUM FRAME LENGTH. This field resets to the value
                                0x0600, which represents a maximum receive frame of 1536 octets. An
                                untagged maximum size Ethernet frame is 1518 octets. A tagged frame
                                adds four octets for a total of 1522 octets. If a shorter maximum
                                length restriction is desired, program this 16-bit field.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SUPP</name>
                    <description>PHY Support register.</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>SPEED</name>
                            <description>This bit configures the Reduced MII logic for the current
                                operating speed. When set, 100 Mbps mode is selected. When cleared,
                                10 Mbps mode is selected.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:9]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TEST</name>
                    <description>Test register.</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SCPQ</name>
                            <description>SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE
                                quanta from 64 byte-times to 1 byte-time.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TESTPAUSE</name>
                            <description>This bit causes the MAC Control sublayer to inhibit
                                transmissions, just as if a PAUSE Receive Control frame with a
                                nonzero pause time parameter was received.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>TESTBP</name>
                            <description>TEST BACKPRESSURE. Setting this bit will cause the MAC to
                                assert backpressure on the link. Backpressure causes preamble to be
                                transmitted, raising carrier sense. A transmit packet from the
                                system will be sent during backpressure.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MCFG</name>
                    <description>MII Mgmt Configuration register.</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SCANINC</name>
                            <description>SCAN INCREMENT. Set this bit to cause the MII Management
                                hardware to perform read cycles across a range of PHYs. When set,
                                the MII Management hardware will perform read cycles from address 1
                                through the value set in PHY ADDRESS[4:0]. Clear this bit to allow
                                continuous reads of the same PHY.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>SUPPPREAMBLE</name>
                            <description>SUPPRESS PREAMBLE. Set this bit to cause the MII Management
                                hardware to perform read/write cycles without the 32-bit preamble
                                field. Clear this bit to cause normal cycles to be performed. Some
                                PHYs support suppressed preamble.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>CLOCKSEL</name>
                            <description>CLOCK SELECT. This field is used by the clock divide logic
                                in creating the MII Management Clock (MDC) which IEEE 802.3u defines
                                to be no faster than 2.5 MHz. Some PHYs support clock rates up to
                                12.5 MHz, however. The AHB bus clock (HCLK) is divided by the
                                specified amount. Refer to Table 160 below for the definition of
                                values for this field.</description>
                            <bitRange>[5:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[14:6]</bitRange>
                        </field>
                        <field>
                            <name>RESETMIIMGMT</name>
                            <description>RESET MII MGMT. This bit resets the MII Management
                                hardware.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MCMD</name>
                    <description>MII Mgmt Command register.</description>
                    <addressOffset>0x024</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>READ</name>
                            <description>This bit causes the MII Management hardware to perform a
                                single Read cycle. The Read data is returned in Register MRDD (MII
                                Mgmt Read Data).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>SCAN</name>
                            <description>This bit causes the MII Management hardware to perform Read
                                cycles continuously. This is useful for monitoring Link Fail for
                                example.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MADR</name>
                    <description>MII Mgmt Address register.</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>REGADDR</name>
                            <description>REGISTER ADDRESS. This field represents the 5-bit Register
                                Address field of Mgmt cycles. Up to 32 registers can be accessed.</description>
                            <bitRange>[4:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[7:5]</bitRange>
                        </field>
                        <field>
                            <name>PHYADDR</name>
                            <description>PHY ADDRESS. This field represents the 5-bit PHY Address
                                field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is
                                reserved).</description>
                            <bitRange>[12:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:13]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MWTD</name>
                    <description>MII Mgmt Write Data register.</description>
                    <addressOffset>0x02C</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>WRITEDATA</name>
                            <description>WRITE DATA. When written, an MII Mgmt write cycle is
                                performed using the 16-bit data and the pre-configured PHY and
                                Register addresses from the MII Mgmt Address register (MADR).</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MRDD</name>
                    <description>MII Mgmt Read Data register.</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>READDATA</name>
                            <description>READ DATA. Following an MII Mgmt Read Cycle, the 16-bit
                                data can be read from this location.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MIND</name>
                    <description>MII Mgmt Indicators register.</description>
                    <addressOffset>0x034</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>BUSY</name>
                            <description>When 1 is returned - indicates MII Mgmt is currently
                                performing an MII Mgmt Read or Write cycle.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>SCANNING</name>
                            <description>When 1 is returned - indicates a scan operation (continuous
                                MII Mgmt Read cycles) is in progress.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>NOTVALID</name>
                            <description>When 1 is returned - indicates MII Mgmt Read cycle has not
                                completed and the Read Data is not yet valid.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>MIILINKFAIL</name>
                            <description>When 1 is returned - indicates that an MII Mgmt link fail
                                has occurred.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SA0</name>
                    <description>Station Address 0 register.</description>
                    <addressOffset>0x040</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SADDR2</name>
                            <description>STATION ADDRESS, 2nd octet. This field holds the second
                                octet of the station address.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>SADDR1</name>
                            <description>STATION ADDRESS, 1st octet. This field holds the first
                                octet of the station address.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SA1</name>
                    <description>Station Address 1 register.</description>
                    <addressOffset>0x044</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SADDR4</name>
                            <description>STATION ADDRESS, 4th octet. This field holds the fourth
                                octet of the station address.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>SADDR3</name>
                            <description>STATION ADDRESS, 3rd octet. This field holds the third
                                octet of the station address.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SA2</name>
                    <description>Station Address 2 register.</description>
                    <addressOffset>0x048</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SADDR6</name>
                            <description>STATION ADDRESS, 6th octet. This field holds the sixth
                                octet of the station address.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>SADDR5</name>
                            <description>STATION ADDRESS, 5th octet. This field holds the fifth
                                octet of the station address.</description>
                            <bitRange>[15:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>COMMAND</name>
                    <description>Command register.</description>
                    <addressOffset>0x100</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXENABLE</name>
                            <description>Enable receive.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TXENABLE</name>
                            <description>Enable transmit.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>REGRESET</name>
                            <description>When a 1 is written, all datapaths and the host registers
                                are reset. The MAC needs to be reset separately.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>TXRESET</name>
                            <description>When a 1 is written, the transmit datapath is reset.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RXRESET</name>
                            <description>When a 1 is written, the receive datapath is reset.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>PASSRUNTFRAME</name>
                            <description>When set to 1 , passes runt frames s1maller than 64 bytes
                                to memory unless they have a CRC error. If 0 runt frames are
                                filtered out.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>PASSRXFILTER</name>
                            <description>When set to 1 , disables receive filtering i.e. all frames
                                received are written to memory.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>TXFLOWCONTROL</name>
                            <description>Enable IEEE 802.3 / clause 31 flow control sending pause
                                frames in full duplex and continuous preamble in half duplex.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>RMII</name>
                            <description>When set to 1 , RMII mode is selected; if 0, MII mode is
                                selected.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>FULLDUPLEX</name>
                            <description>When set to 1 , indicates full duplex operation.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:11]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>STATUS</name>
                    <description>Status register.</description>
                    <addressOffset>0x104</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXSTATUS</name>
                            <description>If 1, the receive channel is active. If 0, the receive
                                channel is inactive.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>TXSTATUS</name>
                            <description>If 1, the transmit channel is active. If 0, the transmit
                                channel is inactive.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXDESCRIPTOR</name>
                    <description>Receive descriptor base address register.</description>
                    <addressOffset>0x108</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Fixed to 00</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>RXDESCRIPTOR</name>
                            <description>MSBs of receive descriptor base address.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXSTATUS</name>
                    <description>Receive status base address register.</description>
                    <addressOffset>0x10C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Fixed to 000</description>
                            <bitRange>[2:0]</bitRange>
                        </field>
                        <field>
                            <name>RXSTATUS</name>
                            <description>MSBs of receive status base address.</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXDESCRIPTORNUMBER</name>
                    <description>Receive number of descriptors register.</description>
                    <addressOffset>0x110</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXDESCRIPTORN</name>
                            <description>RxDescriptorNumber. Number of descriptors in the descriptor
                                array for which RxDescriptor is the base address. The number of
                                descriptors is minus one encoded.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXPRODUCEINDEX</name>
                    <description>Receive produce index register.</description>
                    <addressOffset>0x114</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXPRODUCEIX</name>
                            <description>Index of the descriptor that is going to be filled next by
                                the receive datapath.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXCONSUMEINDEX</name>
                    <description>Receive consume index register.</description>
                    <addressOffset>0x118</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXCONSUMEIX</name>
                            <description>Index of the descriptor that is going to be processed next
                                by the receive</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXDESCRIPTOR</name>
                    <description>Transmit descriptor base address register.</description>
                    <addressOffset>0x11C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Fixed to 00</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>TXD</name>
                            <description>TxDescriptor. MSBs of transmit descriptor base address.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXSTATUS</name>
                    <description>Transmit status base address register.</description>
                    <addressOffset>0x120</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Fixed to 00</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>TXSTAT</name>
                            <description>TxStatus. MSBs of transmit status base address.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXDESCRIPTORNUMBER</name>
                    <description>Transmit number of descriptors register.</description>
                    <addressOffset>0x124</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TXDN</name>
                            <description>TxDescriptorNumber. Number of descriptors in the descriptor
                                array for which TxDescriptor is the base address. The register is
                                minus one encoded.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXPRODUCEINDEX</name>
                    <description>Transmit produce index register.</description>
                    <addressOffset>0x128</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TXPI</name>
                            <description>TxProduceIndex. Index of the descriptor that is going to be
                                filled next by the transmit software driver.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXCONSUMEINDEX</name>
                    <description>Transmit consume index register.</description>
                    <addressOffset>0x12C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TXCI</name>
                            <description>TxConsumeIndex. Index of the descriptor that is going to be
                                transmitted next by the transmit datapath.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TSV0</name>
                    <description>Transmit status vector 0 register.</description>
                    <addressOffset>0x158</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CRCERR</name>
                            <description>CRC error. The attached CRC in the packet did not match the
                                internally generated CRC.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>LCE</name>
                            <description>Length check error. Indicates the frame length field does
                                not match the actual number of data items and is not a type field.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>LOR</name>
                            <description>Length out of range. Indicates that frame type/length field
                                was larger than 1500 bytes. The EMAC doesn't distinguish the frame
                                type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806)
                                packets are received, it compares the frame type with the max length
                                and gives the "Length out of range" error. In fact, this bit is not
                                an error indication, but simply a statement by the chip regarding
                                the status of the received frame.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DONE</name>
                            <description>Transmission of packet was completed.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>MULTICAST</name>
                            <description>Packet's destination was a multicast address.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>BROADCAST</name>
                            <description>Packet's destination was a broadcast address.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>PACKETDEFER</name>
                            <description>Packet was deferred for at least one attempt, but less than
                                an excessive defer.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EXDF</name>
                            <description>Excessive Defer. Packet was deferred in excess of 6071
                                nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EXCOL</name>
                            <description>Excessive Collision. Packet was aborted due to exceeding of
                                maximum allowed number of collisions.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>LCOL</name>
                            <description>Late Collision. Collision occurred beyond collision window,
                                512 bit times.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>GIANT</name>
                            <description>Byte count in frame was greater than can be represented in
                                the transmit byte count field in TSV1.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>UNDERRUN</name>
                            <description>Host side caused buffer underrun.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>TOTALBYTES</name>
                            <description>The total number of bytes transferred including collided
                                attempts.</description>
                            <bitRange>[27:12]</bitRange>
                        </field>
                        <field>
                            <name>CONTROLFRAME</name>
                            <description>The frame was a control frame.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>PAUSE</name>
                            <description>The frame was a control frame with a valid PAUSE opcode.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>BACKPRESSURE</name>
                            <description>Carrier-sense method backpressure was previously applied.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>VLAN</name>
                            <description>Frame's length/type field contained 0x8100 which is the
                                VLAN protocol identifier.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TSV1</name>
                    <description>Transmit status vector 1 register.</description>
                    <addressOffset>0x15C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TBC</name>
                            <description>Transmit byte count. The total number of bytes in the
                                frame, not counting the collided bytes.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>TCC</name>
                            <description>Transmit collision count. Number of collisions the current
                                packet incurred during transmission attempts. The maximum number of
                                collisions (16) cannot be represented.</description>
                            <bitRange>[19:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:20]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RSV</name>
                    <description>Receive status vector register.</description>
                    <addressOffset>0x160</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RBC</name>
                            <description>Received byte count. Indicates length of received frame.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>PPI</name>
                            <description>Packet previously ignored. Indicates that a packet was
                                dropped.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>RXDVSEEN</name>
                            <description>RXDV event previously seen. Indicates that the last receive
                                event seen was not long enough to be a valid packet.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>CESEEN</name>
                            <description>Carrier event previously seen. Indicates that at some time
                                since the last receive statistics, a carrier event was detected.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>RCV</name>
                            <description>Receive code violation. Indicates that received PHY data
                                does not represent a valid receive code.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>CRCERR</name>
                            <description>CRC error. The attached CRC in the packet did not match the
                                internally generated CRC.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>LCERR</name>
                            <description>Length check error. Indicates the frame length field does
                                not match the actual number of data items and is not a type field.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>LOR</name>
                            <description>Length out of range. Indicates that frame type/length field
                                was larger than 1518 bytes. The EMAC doesn't distinguish the frame
                                type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806)
                                packets are received, it compares the frame type with the max length
                                and gives the "Length out of range" error. In fact, this bit is not
                                an error indication, but simply a statement by the chip regarding
                                the status of the received frame.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>ROK</name>
                            <description>Receive OK. The packet had valid CRC and no symbol errors.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>MULTICAST</name>
                            <description>The packet destination was a multicast address.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>BROADCAST</name>
                            <description>The packet destination was a broadcast address.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>DRIBBLENIBBLE</name>
                            <description>Indicates that after the end of packet another 1-7 bits
                                were received. A single nibble, called dribble nibble, is formed but
                                not sent out.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>CONTROLFRAME</name>
                            <description>The frame was a control frame.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>PAUSE</name>
                            <description>The frame was a control frame with a valid PAUSE opcode.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>UO</name>
                            <description>Unsupported Opcode. The current frame was recognized as a
                                Control Frame but contains an unknown opcode.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>VLAN</name>
                            <description>Frame's length/type field contained 0x8100 which is the
                                VLAN protocol identifier.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FLOWCONTROLCOUNTER</name>
                    <description>Flow control counter register.</description>
                    <addressOffset>0x170</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MC</name>
                            <description>MirrorCounter. In full duplex mode the MirrorCounter
                                specifies the number of cycles before re-issuing the Pause control
                                frame.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>PT</name>
                            <description>PauseTimer. In full-duplex mode the PauseTimer specifies
                                the value that is inserted into the pause timer field of a pause
                                flow control frame. In half duplex mode the PauseTimer specifies the
                                number of backpressure cycles.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>FLOWCONTROLSTATUS</name>
                    <description>Flow control status register.</description>
                    <addressOffset>0x174</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MCC</name>
                            <description>MirrorCounterCurrent. In full duplex mode this register
                                represents the current value of the datapath's mirror counter which
                                counts up to the value specified by the MirrorCounter field in the
                                FlowControlCounter register. In half duplex mode the register counts
                                until it reaches the value of the PauseTimer bits in the
                                FlowControlCounter register.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXFILTERCTRL</name>
                    <description>Receive filter control register.</description>
                    <addressOffset>0x200</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>AUE</name>
                            <description>AcceptUnicastEn. When set to 1, all unicast frames are
                                accepted.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>ABE</name>
                            <description>AcceptBroadcastEn. When set to 1, all broadcast frames are
                                accepted.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>AME</name>
                            <description>AcceptMulticastEn. When set to 1, all multicast frames are
                                accepted.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>AUHE</name>
                            <description>AcceptUnicastHashEn. When set to 1, unicast frames that
                                pass the imperfect hash filter are accepted.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>AMHE</name>
                            <description>AcceptMulticastHashEn. When set to 1, multicast frames that
                                pass the imperfect hash filter are accepted.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>APE</name>
                            <description>AcceptPerfectEn. When set to 1, the frames with a
                                destination address identical to the station address are accepted.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[11:6]</bitRange>
                        </field>
                        <field>
                            <name>MPEW</name>
                            <description>MagicPacketEnWoL. When set to 1, the result of the magic
                                packet filter will generate a WoL interrupt when there is a match.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>RFEW</name>
                            <description>RxFilterEnWoL. When set to 1, the result of the perfect
                                address matching filter and the imperfect hash filter will generate
                                a WoL interrupt when there is a match.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:14]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXFILTERWOLSTATUS</name>
                    <description>Receive filter WoL status register.</description>
                    <addressOffset>0x204</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>AUW</name>
                            <description>AcceptUnicastWoL. When the value is 1, a unicast frames
                                caused WoL.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>ABW</name>
                            <description>AcceptBroadcastWoL. When the value is 1, a broadcast frame
                                caused WoL.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>AMW</name>
                            <description>AcceptMulticastWoL. When the value is 1, a multicast frame
                                caused WoL.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>AUHW</name>
                            <description>AcceptUnicastHashWoL. When the value is 1, a unicast frame
                                that passes the imperfect hash filter caused WoL.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>AMHW</name>
                            <description>AcceptMulticastHashWoL. When the value is 1, a multicast
                                frame that passes the imperfect hash filter caused WoL.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>APW</name>
                            <description>AcceptPerfectWoL. When the value is 1, the perfect address
                                matching filter caused WoL.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RFW</name>
                            <description>RxFilterWoL. When the value is 1, the receive filter caused
                                WoL.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>MPW</name>
                            <description>MagicPacketWoL. When the value is 1, the magic packet
                                filter caused WoL.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:9]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXFILTERWOLCLEAR</name>
                    <description>Receive filter WoL clear register.</description>
                    <addressOffset>0x208</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>AUWCLR</name>
                            <description>AcceptUnicastWoLClr. When a 1 is written, the corresponding
                                status bit in the RxFilterWoLStatus register is cleared.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>ABWCLR</name>
                            <description>AcceptBroadcastWoLClr. When a 1 is written, the
                                corresponding status bit in the RxFilterWoLStatus register is
                                cleared.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>AMWCLR</name>
                            <description>AcceptMulticastWoLClr. When a 1 is written, the
                                corresponding status bit in the RxFilterWoLStatus register is
                                cleared.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>AUHWCLR</name>
                            <description>AcceptUnicastHashWoLClr. When a 1 is written, the
                                corresponding status bit in the RxFilterWoLStatus register is
                                cleared.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>AMHWCLR</name>
                            <description>AcceptMulticastHashWoLClr. When a 1 is written, the
                                corresponding status bit in the RxFilterWoLStatus register is
                                cleared.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>APWCLR</name>
                            <description>AcceptPerfectWoLClr. When a 1 is written, the corresponding
                                status bit in the RxFilterWoLStatus register is cleared.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RFWCLR</name>
                            <description>RxFilterWoLClr. When a 1 is written, the corresponding
                                status bit in the RxFilterWoLStatus register is cleared.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>MPWCLR</name>
                            <description>MagicPacketWoLClr. When a 1 is written, the corresponding
                                status bit in the RxFilterWoLStatus register is cleared.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:9]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>HASHFILTERL</name>
                    <description>Hash filter table LSBs register.</description>
                    <addressOffset>0x210</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>HFL</name>
                            <description>HashFilterL. Bits 31:0 of the imperfect filter hash table
                                for receive filtering.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>HASHFILTERH</name>
                    <description>Hash filter table MSBs register.</description>
                    <addressOffset>0x214</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>HFH</name>
                            <description>Bits 63:32 of the imperfect filter hash table for receive
                                filtering.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTSTATUS</name>
                    <description>Interrupt status register.</description>
                    <addressOffset>0xFE0</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXOVERRUNINT</name>
                            <description>Interrupt set on a fatal overrun error in the receive
                                queue. The fatal interrupt should be resolved by a Rx soft-reset.
                                The bit is not set when there is a nonfatal overrun error.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RXERRORINT</name>
                            <description>Interrupt trigger on receive errors: AlignmentError,
                                RangeError, LengthError, SymbolError, CRCError or NoDescriptor or
                                Overrun.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RXFINISHEDINT</name>
                            <description>Interrupt triggered when all receive descriptors have been
                                processed i.e. on the transition to the situation where ProduceIndex
                                == ConsumeIndex.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RXDONEINT</name>
                            <description>Interrupt triggered when a receive descriptor has been
                                processed while the Interrupt bit in the Control field of the
                                descriptor was set.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>TXUNDERRUNINT</name>
                            <description>Interrupt set on a fatal underrun error in the transmit
                                queue. The fatal interrupt should be resolved by a Tx soft-reset.
                                The bit is not set when there is a nonfatal underrun error.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>TXERRORINT</name>
                            <description>Interrupt trigger on transmit errors: LateCollision,
                                ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>TXFINISHEDINT</name>
                            <description>Interrupt triggered when all transmit descriptors have been
                                processed i.e. on the transition to the situation where ProduceIndex
                                == ConsumeIndex.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TXDONEINT</name>
                            <description>Interrupt triggered when a descriptor has been transmitted
                                while the Interrupt bit in the Control field of the descriptor was
                                set.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>SOFTINT</name>
                            <description>Interrupt triggered by software writing a 1 to the
                                SoftIntSet bit in the IntSet register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>WAKEUPINT</name>
                            <description>Interrupt triggered by a Wake-up event detected by the
                                receive filter.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:14]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTENABLE</name>
                    <description>Interrupt enable register.</description>
                    <addressOffset>0xFE4</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXOVERRUNINTEN</name>
                            <description>Enable for interrupt trigger on receive buffer overrun or
                                descriptor underrun situations.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RXERRORINTEN</name>
                            <description>Enable for interrupt trigger on receive errors.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RXFINISHEDINTEN</name>
                            <description>Enable for interrupt triggered when all receive descriptors
                                have been processed i.e. on the transition to the situation where
                                ProduceIndex == ConsumeIndex.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RXDONEINTEN</name>
                            <description>Enable for interrupt triggered when a receive descriptor
                                has been processed while the Interrupt bit in the Control field of
                                the descriptor was set.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>TXUNDERRUNINTEN</name>
                            <description>Enable for interrupt trigger on transmit buffer or
                                descriptor underrun situations.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>TXERRORINTEN</name>
                            <description>Enable for interrupt trigger on transmit errors.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>TXFINISHEDINTEN</name>
                            <description>Enable for interrupt triggered when all transmit
                                descriptors have been processed i.e. on the transition to the
                                situation where ProduceIndex == ConsumeIndex.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TXDONEINTEN</name>
                            <description>Enable for interrupt triggered when a descriptor has been
                                transmitted while the Interrupt bit in the Control field of the
                                descriptor was set.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>SOFTINTEN</name>
                            <description>Enable for interrupt triggered by the SoftInt bit in the
                                IntStatus register, caused by software writing a 1 to the SoftIntSet
                                bit in the IntSet register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>WAKEUPINTEN</name>
                            <description>Enable for interrupt triggered by a Wake-up event detected
                                by the receive filter.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:14]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTCLEAR</name>
                    <description>Interrupt clear register.</description>
                    <addressOffset>0xFE8</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXOVERRUNINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RXERRORINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RXFINISHEDINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RXDONEINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>TXUNDERRUNINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>TXERRORINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>TXFINISHEDINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TXDONEINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>SOFTINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>WAKEUPINTCLR</name>
                            <description>Writing a 1 clears the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:14]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTSET</name>
                    <description>Interrupt set register.</description>
                    <addressOffset>0xFEC</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RXOVERRUNINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RXERRORINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RXFINISHEDINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RXDONEINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>TXUNDERRUNINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>TXERRORINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>TXFINISHEDINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TXDONEINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[11:8]</bitRange>
                        </field>
                        <field>
                            <name>SOFTINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>WAKEUPINTSET</name>
                            <description>Writing a 1 to one sets the corresponding status bit in
                                interrupt status register IntStatus.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[31:14]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>POWERDOWN</name>
                    <description>Power-down register.</description>
                    <addressOffset>0xFF4</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Unused</description>
                            <bitRange>[30:0]</bitRange>
                        </field>
                        <field>
                            <name>PD</name>
                            <description>PowerDownMACAHB. If true, all AHB accesses will return a
                                read/write error, except accesses to the Power-Down register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>GPDMA</name>
            <description>General purpose DMA controller</description>
            <groupName>GPDMA</groupName>
            <baseAddress>0x50004000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>DMA</name>
                <value>26</value>
            </interrupt>
            <registers>
                <register>
                    <name>INTSTAT</name>
                    <description>DMA Interrupt Status Register</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>INTSTAT0</name>
                            <description>Status of DMA channel interrupts after masking. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                interrupt request. 1 - the corresponding channel does have an active
                                interrupt request.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>INTSTAT1</name>
                            <description>Status of DMA channel interrupts after masking. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                interrupt request. 1 - the corresponding channel does have an active
                                interrupt request.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>INTSTAT2</name>
                            <description>Status of DMA channel interrupts after masking. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                interrupt request. 1 - the corresponding channel does have an active
                                interrupt request.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>INTSTAT3</name>
                            <description>Status of DMA channel interrupts after masking. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                interrupt request. 1 - the corresponding channel does have an active
                                interrupt request.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>INTSTAT4</name>
                            <description>Status of DMA channel interrupts after masking. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                interrupt request. 1 - the corresponding channel does have an active
                                interrupt request.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>INTSTAT5</name>
                            <description>Status of DMA channel interrupts after masking. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                interrupt request. 1 - the corresponding channel does have an active
                                interrupt request.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>INTSTAT6</name>
                            <description>Status of DMA channel interrupts after masking. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                interrupt request. 1 - the corresponding channel does have an active
                                interrupt request.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>INTSTAT7</name>
                            <description>Status of DMA channel interrupts after masking. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                interrupt request. 1 - the corresponding channel does have an active
                                interrupt request.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTTCSTAT</name>
                    <description>DMA Interrupt Terminal Count Request Status Register</description>
                    <addressOffset>0x004</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>INTTCSTAT0</name>
                            <description>Terminal count interrupt request status for DMA channels.
                                Each bit represents one channel: 0 - the corresponding channel has
                                no active terminal count interrupt request. 1 - the corresponding
                                channel does have an active terminal count interrupt request.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>INTTCSTAT1</name>
                            <description>Terminal count interrupt request status for DMA channels.
                                Each bit represents one channel: 0 - the corresponding channel has
                                no active terminal count interrupt request. 1 - the corresponding
                                channel does have an active terminal count interrupt request.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>INTTCSTAT2</name>
                            <description>Terminal count interrupt request status for DMA channels.
                                Each bit represents one channel: 0 - the corresponding channel has
                                no active terminal count interrupt request. 1 - the corresponding
                                channel does have an active terminal count interrupt request.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>INTTCSTAT3</name>
                            <description>Terminal count interrupt request status for DMA channels.
                                Each bit represents one channel: 0 - the corresponding channel has
                                no active terminal count interrupt request. 1 - the corresponding
                                channel does have an active terminal count interrupt request.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>INTTCSTAT4</name>
                            <description>Terminal count interrupt request status for DMA channels.
                                Each bit represents one channel: 0 - the corresponding channel has
                                no active terminal count interrupt request. 1 - the corresponding
                                channel does have an active terminal count interrupt request.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>INTTCSTAT5</name>
                            <description>Terminal count interrupt request status for DMA channels.
                                Each bit represents one channel: 0 - the corresponding channel has
                                no active terminal count interrupt request. 1 - the corresponding
                                channel does have an active terminal count interrupt request.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>INTTCSTAT6</name>
                            <description>Terminal count interrupt request status for DMA channels.
                                Each bit represents one channel: 0 - the corresponding channel has
                                no active terminal count interrupt request. 1 - the corresponding
                                channel does have an active terminal count interrupt request.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>INTTCSTAT7</name>
                            <description>Terminal count interrupt request status for DMA channels.
                                Each bit represents one channel: 0 - the corresponding channel has
                                no active terminal count interrupt request. 1 - the corresponding
                                channel does have an active terminal count interrupt request.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTTCCLEAR</name>
                    <description>DMA Interrupt Terminal Count Request Clear Register</description>
                    <addressOffset>0x008</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>INTTCCLEAR0</name>
                            <description>Allows clearing the Terminal count interrupt request
                                (IntTCStat) for DMA channels. Each bit represents one channel: 0 -
                                writing 0 has no effect. 1 - clears the corresponding channel
                                terminal count interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>INTTCCLEAR1</name>
                            <description>Allows clearing the Terminal count interrupt request
                                (IntTCStat) for DMA channels. Each bit represents one channel: 0 -
                                writing 0 has no effect. 1 - clears the corresponding channel
                                terminal count interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>INTTCCLEAR2</name>
                            <description>Allows clearing the Terminal count interrupt request
                                (IntTCStat) for DMA channels. Each bit represents one channel: 0 -
                                writing 0 has no effect. 1 - clears the corresponding channel
                                terminal count interrupt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>INTTCCLEAR3</name>
                            <description>Allows clearing the Terminal count interrupt request
                                (IntTCStat) for DMA channels. Each bit represents one channel: 0 -
                                writing 0 has no effect. 1 - clears the corresponding channel
                                terminal count interrupt.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>INTTCCLEAR4</name>
                            <description>Allows clearing the Terminal count interrupt request
                                (IntTCStat) for DMA channels. Each bit represents one channel: 0 -
                                writing 0 has no effect. 1 - clears the corresponding channel
                                terminal count interrupt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>INTTCCLEAR5</name>
                            <description>Allows clearing the Terminal count interrupt request
                                (IntTCStat) for DMA channels. Each bit represents one channel: 0 -
                                writing 0 has no effect. 1 - clears the corresponding channel
                                terminal count interrupt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>INTTCCLEAR6</name>
                            <description>Allows clearing the Terminal count interrupt request
                                (IntTCStat) for DMA channels. Each bit represents one channel: 0 -
                                writing 0 has no effect. 1 - clears the corresponding channel
                                terminal count interrupt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>INTTCCLEAR7</name>
                            <description>Allows clearing the Terminal count interrupt request
                                (IntTCStat) for DMA channels. Each bit represents one channel: 0 -
                                writing 0 has no effect. 1 - clears the corresponding channel
                                terminal count interrupt.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTERRSTAT</name>
                    <description>DMA Interrupt Error Status Register</description>
                    <addressOffset>0x00C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>INTERRSTAT0</name>
                            <description>Interrupt error status for DMA channels. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                error interrupt request. 1 - the corresponding channel does have an
                                active error interrupt request.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>INTERRSTAT1</name>
                            <description>Interrupt error status for DMA channels. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                error interrupt request. 1 - the corresponding channel does have an
                                active error interrupt request.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>INTERRSTAT2</name>
                            <description>Interrupt error status for DMA channels. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                error interrupt request. 1 - the corresponding channel does have an
                                active error interrupt request.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>INTERRSTAT3</name>
                            <description>Interrupt error status for DMA channels. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                error interrupt request. 1 - the corresponding channel does have an
                                active error interrupt request.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>INTERRSTAT4</name>
                            <description>Interrupt error status for DMA channels. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                error interrupt request. 1 - the corresponding channel does have an
                                active error interrupt request.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>INTERRSTAT5</name>
                            <description>Interrupt error status for DMA channels. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                error interrupt request. 1 - the corresponding channel does have an
                                active error interrupt request.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>INTERRSTAT6</name>
                            <description>Interrupt error status for DMA channels. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                error interrupt request. 1 - the corresponding channel does have an
                                active error interrupt request.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>INTERRSTAT7</name>
                            <description>Interrupt error status for DMA channels. Each bit
                                represents one channel: 0 - the corresponding channel has no active
                                error interrupt request. 1 - the corresponding channel does have an
                                active error interrupt request.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTERRCLR</name>
                    <description>DMA Interrupt Error Clear Register</description>
                    <addressOffset>0x010</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>INTERRCLR0</name>
                            <description>Writing a 1 clears the error interrupt request (IntErrStat)
                                for DMA channels. Each bit represents one channel: 0 - writing 0 has
                                no effect. 1 - clears the corresponding channel error interrupt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>INTERRCLR1</name>
                            <description>Writing a 1 clears the error interrupt request (IntErrStat)
                                for DMA channels. Each bit represents one channel: 0 - writing 0 has
                                no effect. 1 - clears the corresponding channel error interrupt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>INTERRCLR2</name>
                            <description>Writing a 1 clears the error interrupt request (IntErrStat)
                                for DMA channels. Each bit represents one channel: 0 - writing 0 has
                                no effect. 1 - clears the corresponding channel error interrupt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>INTERRCLR3</name>
                            <description>Writing a 1 clears the error interrupt request (IntErrStat)
                                for DMA channels. Each bit represents one channel: 0 - writing 0 has
                                no effect. 1 - clears the corresponding channel error interrupt.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>INTERRCLR4</name>
                            <description>Writing a 1 clears the error interrupt request (IntErrStat)
                                for DMA channels. Each bit represents one channel: 0 - writing 0 has
                                no effect. 1 - clears the corresponding channel error interrupt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>INTERRCLR5</name>
                            <description>Writing a 1 clears the error interrupt request (IntErrStat)
                                for DMA channels. Each bit represents one channel: 0 - writing 0 has
                                no effect. 1 - clears the corresponding channel error interrupt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>INTERRCLR6</name>
                            <description>Writing a 1 clears the error interrupt request (IntErrStat)
                                for DMA channels. Each bit represents one channel: 0 - writing 0 has
                                no effect. 1 - clears the corresponding channel error interrupt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>INTERRCLR7</name>
                            <description>Writing a 1 clears the error interrupt request (IntErrStat)
                                for DMA channels. Each bit represents one channel: 0 - writing 0 has
                                no effect. 1 - clears the corresponding channel error interrupt.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RAWINTTCSTAT</name>
                    <description>DMA Raw Interrupt Terminal Count Status Register</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RAWINTTCSTAT0</name>
                            <description>Status of the terminal count interrupt for DMA channels
                                prior to masking. Each bit represents one channel: 0 - the
                                corresponding channel has no active terminal count interrupt
                                request. 1 - the corresponding channel does have an active terminal
                                count interrupt request.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTTCSTAT1</name>
                            <description>Status of the terminal count interrupt for DMA channels
                                prior to masking. Each bit represents one channel: 0 - the
                                corresponding channel has no active terminal count interrupt
                                request. 1 - the corresponding channel does have an active terminal
                                count interrupt request.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTTCSTAT2</name>
                            <description>Status of the terminal count interrupt for DMA channels
                                prior to masking. Each bit represents one channel: 0 - the
                                corresponding channel has no active terminal count interrupt
                                request. 1 - the corresponding channel does have an active terminal
                                count interrupt request.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTTCSTAT3</name>
                            <description>Status of the terminal count interrupt for DMA channels
                                prior to masking. Each bit represents one channel: 0 - the
                                corresponding channel has no active terminal count interrupt
                                request. 1 - the corresponding channel does have an active terminal
                                count interrupt request.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTTCSTAT4</name>
                            <description>Status of the terminal count interrupt for DMA channels
                                prior to masking. Each bit represents one channel: 0 - the
                                corresponding channel has no active terminal count interrupt
                                request. 1 - the corresponding channel does have an active terminal
                                count interrupt request.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTTCSTAT5</name>
                            <description>Status of the terminal count interrupt for DMA channels
                                prior to masking. Each bit represents one channel: 0 - the
                                corresponding channel has no active terminal count interrupt
                                request. 1 - the corresponding channel does have an active terminal
                                count interrupt request.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTTCSTAT6</name>
                            <description>Status of the terminal count interrupt for DMA channels
                                prior to masking. Each bit represents one channel: 0 - the
                                corresponding channel has no active terminal count interrupt
                                request. 1 - the corresponding channel does have an active terminal
                                count interrupt request.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTTCSTAT7</name>
                            <description>Status of the terminal count interrupt for DMA channels
                                prior to masking. Each bit represents one channel: 0 - the
                                corresponding channel has no active terminal count interrupt
                                request. 1 - the corresponding channel does have an active terminal
                                count interrupt request.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RAWINTERRSTAT</name>
                    <description>DMA Raw Error Interrupt Status Register</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RAWINTERRSTAT0</name>
                            <description>Status of the error interrupt for DMA channels prior to
                                masking. Each bit represents one channel: 0 - the corresponding
                                channel has no active error interrupt request. 1 - the corresponding
                                channel does have an active error interrupt request.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTERRSTAT1</name>
                            <description>Status of the error interrupt for DMA channels prior to
                                masking. Each bit represents one channel: 0 - the corresponding
                                channel has no active error interrupt request. 1 - the corresponding
                                channel does have an active error interrupt request.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTERRSTAT2</name>
                            <description>Status of the error interrupt for DMA channels prior to
                                masking. Each bit represents one channel: 0 - the corresponding
                                channel has no active error interrupt request. 1 - the corresponding
                                channel does have an active error interrupt request.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTERRSTAT3</name>
                            <description>Status of the error interrupt for DMA channels prior to
                                masking. Each bit represents one channel: 0 - the corresponding
                                channel has no active error interrupt request. 1 - the corresponding
                                channel does have an active error interrupt request.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTERRSTAT4</name>
                            <description>Status of the error interrupt for DMA channels prior to
                                masking. Each bit represents one channel: 0 - the corresponding
                                channel has no active error interrupt request. 1 - the corresponding
                                channel does have an active error interrupt request.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTERRSTAT5</name>
                            <description>Status of the error interrupt for DMA channels prior to
                                masking. Each bit represents one channel: 0 - the corresponding
                                channel has no active error interrupt request. 1 - the corresponding
                                channel does have an active error interrupt request.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTERRSTAT6</name>
                            <description>Status of the error interrupt for DMA channels prior to
                                masking. Each bit represents one channel: 0 - the corresponding
                                channel has no active error interrupt request. 1 - the corresponding
                                channel does have an active error interrupt request.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RAWINTERRSTAT7</name>
                            <description>Status of the error interrupt for DMA channels prior to
                                masking. Each bit represents one channel: 0 - the corresponding
                                channel has no active error interrupt request. 1 - the corresponding
                                channel does have an active error interrupt request.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>ENBLDCHNS</name>
                    <description>DMA Enabled Channel Register</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>ENABLEDCHANNELS0</name>
                            <description>Enable status for DMA channels. Each bit represents one
                                channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>ENABLEDCHANNELS1</name>
                            <description>Enable status for DMA channels. Each bit represents one
                                channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>ENABLEDCHANNELS2</name>
                            <description>Enable status for DMA channels. Each bit represents one
                                channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>ENABLEDCHANNELS3</name>
                            <description>Enable status for DMA channels. Each bit represents one
                                channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>ENABLEDCHANNELS4</name>
                            <description>Enable status for DMA channels. Each bit represents one
                                channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>ENABLEDCHANNELS5</name>
                            <description>Enable status for DMA channels. Each bit represents one
                                channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>ENABLEDCHANNELS6</name>
                            <description>Enable status for DMA channels. Each bit represents one
                                channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>ENABLEDCHANNELS7</name>
                            <description>Enable status for DMA channels. Each bit represents one
                                channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SOFTBREQ</name>
                    <description>DMA Software Burst Request Register</description>
                    <addressOffset>0x020</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SOFTBREQ0</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ1</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ2</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ3</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ4</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ5</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ6</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ7</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ8</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ9</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ10</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ11</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ12</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ13</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ14</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>SOFTBREQ15</name>
                            <description>Software burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                Description (refer to Table 672 for peripheral hardware connections
                                to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA burst request for the corresponding request line.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SOFTSREQ</name>
                    <description>DMA Software Single Request Register</description>
                    <addressOffset>0x024</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00000000</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SOFTSREQ0</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ1</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ2</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ3</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ4</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ5</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ6</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ7</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ8</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ9</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ10</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ11</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ12</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ13</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ14</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>SOFTSREQ15</name>
                            <description>Software single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read undefined. Write reserved bits as zero.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SOFTLBREQ</name>
                    <description>DMA Software Last Burst Request Register</description>
                    <addressOffset>0x028</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SOFTLBREQ0</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ1</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ2</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ3</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ4</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ5</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ6</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ7</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ8</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ9</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ10</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ11</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ12</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ13</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ14</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLBREQ15</name>
                            <description>Software last burst request flags for each of 16 possible
                                sources. Each bit represents one DMA request line or peripheral
                                function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA
                                last burst request for the corresponding request line.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SOFTLSREQ</name>
                    <description>DMA Software Last Single Request Register</description>
                    <addressOffset>0x02C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>SOFTLSREQ0</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ1</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ2</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ3</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ4</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ5</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ6</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ7</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ8</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ9</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ10</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ11</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ12</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ13</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ14</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>SOFTLSREQ15</name>
                            <description>Software last single transfer request flags for each of 16
                                possible sources. Each bit represents one DMA request line or
                                peripheral function: 0 - writing 0 has no effect. 1 - writing 1
                                generates a DMA last single transfer request for the corresponding
                                request line.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CONFIG</name>
                    <description>DMA Configuration Register</description>
                    <addressOffset>0x030</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>E</name>
                            <description>DMA Controller enable: 0 = disabled (default). Disabling
                                the DMA Controller reduces power consumption. 1 = enabled.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>M</name>
                            <description>AHB Master endianness configuration: 0 = little-endian mode
                                (default). 1 = big-endian mode.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SYNC</name>
                    <description>DMA Synchronization Register</description>
                    <addressOffset>0x034</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>DMACSYNC0</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC1</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC2</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC3</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC4</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC5</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC6</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC7</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC8</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC9</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC10</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC11</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC12</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC13</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC14</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>DMACSYNC15</name>
                            <description>Controls the synchronization logic for DMA request signals.
                                Each bit represents one set of DMA request lines as described in the
                                preceding text: 0 - synchronization logic for the corresponding DMA
                                request signals are enabled. 1 - synchronization logic for the
                                corresponding DMA request signals are disabled.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <cluster>
                    <dim>8</dim>
                    <dimIncrement>0x20</dimIncrement>
                    <name>CH[%s]</name>
                    <description>DMA Channel registers.</description>
                    <headerStructName>dma_ch</headerStructName>
                    <addressOffset>0x100</addressOffset>
                    <access>read-write</access>
                    <register>
                        <name>SRCADDR</name>
                        <description>DMA Channel Source Address Register</description>
                        <addressOffset>0x0</addressOffset>
                        <access>read-write</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>SRCADDR</name>
                                <description>DMA source address. Reading this register will return
                                    the current source address.</description>
                                <bitRange>[31:0]</bitRange>
                            </field>
                        </fields>
                    </register>
                    <register>
                        <name>DESTADDR</name>
                        <description>DMA Channel Destination Address Register</description>
                        <addressOffset>0x4</addressOffset>
                        <access>read-write</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>DESTADDR</name>
                                <description>DMA Destination address. Reading this register will
                                    return the current destination address.</description>
                                <bitRange>[31:0]</bitRange>
                            </field>
                        </fields>
                    </register>
                    <register>
                        <name>LLI</name>
                        <description>DMA Channel Linked List Item Register</description>
                        <addressOffset>0x8</addressOffset>
                        <access>read-write</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>RESERVED</name>
                                <description>Reserved, and must be written as 0.</description>
                                <bitRange>[1:0]</bitRange>
                            </field>
                            <field>
                                <name>LLI</name>
                                <description>Linked list item. Bits [31:2] of the address for the
                                    next LLI. Address bits [1:0] are 0.</description>
                                <bitRange>[31:2]</bitRange>
                            </field>
                        </fields>
                    </register>
                    <register>
                        <name>CONTROL</name>
                        <description>DMA Channel Control Register</description>
                        <addressOffset>0xC</addressOffset>
                        <access>read-write</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>TRANSFERSIZE</name>
                                <description>Transfer size. This field sets the size of the transfer
                                    when the DMA controller is the flow controller, in which case
                                    the value must be set before the channel is enabled. Transfer
                                    size is updated as data transfers are completed. A read from
                                    this field indicates the number of transfers completed on the
                                    destination bus. Reading the register when the channel is active
                                    does not give useful information because by the time that the
                                    software has processed the value read, the channel might have
                                    progressed. It is intended to be used only when a channel is
                                    enabled and then disabled. The transfer size value is not used
                                    if a peripheral is the flow controller.</description>
                                <bitRange>[11:0]</bitRange>
                            </field>
                            <field>
                                <name>SBSIZE</name>
                                <description>Source burst size. Indicates the number of transfers
                                    that make up a source burst. This value must be set to the burst
                                    size of the source peripheral, or if the source is memory, to
                                    the memory boundary size. The burst size is the amount of data
                                    that is transferred when the DMACBREQ signal goes active in the
                                    source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101
                                    - 64 110 - 128 111 - 256</description>
                                <bitRange>[14:12]</bitRange>
                            </field>
                            <field>
                                <name>DBSIZE</name>
                                <description>Destination burst size. Indicates the number of
                                    transfers that make up a destination burst transfer request.
                                    This value must be set to the burst size of the destination
                                    peripheral or, if the destination is memory, to the memory
                                    boundary size. The burst size is the amount of data that is
                                    transferred when the DMACBREQ signal goes active in the
                                    destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 -
                                    32 101 - 64 110 - 128 111 - 256</description>
                                <bitRange>[17:15]</bitRange>
                            </field>
                            <field>
                                <name>SWIDTH</name>
                                <description>Source transfer width. The source and destination
                                    widths can be different from each other. The hardware
                                    automatically packs and unpacks the data as required. 000 - Byte
                                    (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 -
                                    Reserved</description>
                                <bitRange>[20:18]</bitRange>
                            </field>
                            <field>
                                <name>DWIDTH</name>
                                <description>Destination transfer width. The source and destination
                                    widths can be different from each other. The hardware
                                    automatically packs and unpacks the data as required. 000 - Byte
                                    (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 -
                                    Reserved</description>
                                <bitRange>[23:21]</bitRange>
                            </field>
                            <field>
                                <name>RESERVED</name>
                                <description>Reserved, and must be written as 0.</description>
                                <bitRange>[25:24]</bitRange>
                            </field>
                            <field>
                                <name>SI</name>
                                <description>Source increment: 0 - the source address is not
                                    incremented after each transfer. 1 - the source address is
                                    incremented after each transfer.</description>
                                <bitRange>[26:26]</bitRange>
                            </field>
                            <field>
                                <name>DI</name>
                                <description>Destination increment: 0 - the destination address is
                                    not incremented after each transfer. 1 - the destination address
                                    is incremented after each transfer.</description>
                                <bitRange>[27:27]</bitRange>
                            </field>
                            <field>
                                <name>PROT1</name>
                                <description>This is provided to the peripheral during a DMA bus
                                    access and indicates that the access is in user mode or
                                    privileged mode. This information is not used in the
                                    LPC178x/177x. 0 - access is in user mode. 1 - access is in
                                    privileged mode.</description>
                                <bitRange>[28:28]</bitRange>
                            </field>
                            <field>
                                <name>PROT2</name>
                                <description>This is provided to the peripheral during a DMA bus
                                    access and indicates to the peripheral that the access is
                                    bufferable or not bufferable. This information is not used in
                                    the LPC178x/177x. 0 - access is not bufferable. 1 - access is
                                    bufferable.</description>
                                <bitRange>[29:29]</bitRange>
                            </field>
                            <field>
                                <name>PROT3</name>
                                <description>This is provided to the peripheral during a DMA bus
                                    access and indicates to the peripheral that the access is
                                    cacheable or not cacheable. This information is not used in the
                                    LPC178x/177x. 0 - access is not cacheable. 1 - access is
                                    cacheable.</description>
                                <bitRange>[30:30]</bitRange>
                            </field>
                            <field>
                                <name>I</name>
                                <description>Terminal count interrupt enable bit. 0 - the terminal
                                    count interrupt is disabled. 1 - the terminal count interrupt is
                                    enabled.</description>
                                <bitRange>[31:31]</bitRange>
                            </field>
                        </fields>
                    </register>
                    <register>
                        <name>CONFIG</name>
                        <description>DMA Channel 0 Configuration Register[1]</description>
                        <addressOffset>0x10</addressOffset>
                        <access>read-write</access>
                        <resetValue>0</resetValue>
                        <resetMask>0xFFFFFFFF</resetMask>
                        <fields>
                            <field>
                                <name>E</name>
                                <description>Channel enable. Reading this bit indicates whether a
                                    channel is currently enabled or disabled: 0 = channel disabled.
                                    1 = channel enabled. The Channel Enable bit status can also be
                                    found by reading the DMACEnbldChns Register. A channel is
                                    enabled by setting this bit. A channel can be disabled by
                                    clearing the Enable bit. This causes the current AHB transfer
                                    (if one is in progress) to complete and the channel is then
                                    disabled. Any data in the FIFO of the relevant channel is lost.
                                    Restarting the channel by setting the Channel Enable bit has
                                    unpredictable effects, the channel must be fully re-initialized.
                                    The channel is also disabled, and Channel Enable bit cleared,
                                    when the last LLI is reached, the DMA transfer is completed, or
                                    if a channel error is encountered. If a channel must be disabled
                                    without losing data in the FIFO, the Halt bit must be set so
                                    that further DMA requests are ignored. The Active bit must then
                                    be polled until it reaches 0, indicating that there is no data
                                    left in the FIFO. Finally, the Channel Enable bit can be
                                    cleared.</description>
                                <bitRange>[0:0]</bitRange>
                            </field>
                            <field>
                                <name>SRCPERIPHERAL</name>
                                <description>Source peripheral. This value selects the DMA source
                                    request peripheral. This field is ignored if the source of the
                                    transfer is from memory. See Table 672 for peripheral
                                    identification.</description>
                                <bitRange>[5:1]</bitRange>
                            </field>
                            <field>
                                <name>DESTPERIPHERAL</name>
                                <description>Destination peripheral. This value selects the DMA
                                    destination request peripheral. This field is ignored if the
                                    destination of the transfer is to memory. See Table 672 for
                                    peripheral identification.</description>
                                <bitRange>[10:6]</bitRange>
                            </field>
                            <field>
                                <name>TRANSFERTYPE</name>
                                <description>This value indicates the type of transfer and specifies
                                    the flow controller. The transfer type can be memory-to-memory,
                                    memory-to-peripheral, peripheral-to-memory, or
                                    peripheral-to-peripheral. Flow can be controlled by the DMA
                                    controller, the source peripheral, or the destination
                                    peripheral. Refer to Table 694 for the encoding of this field.</description>
                                <bitRange>[13:11]</bitRange>
                            </field>
                            <field>
                                <name>IE</name>
                                <description>Interrupt error mask. When cleared, this bit masks out
                                    the error interrupt of the relevant channel.</description>
                                <bitRange>[14:14]</bitRange>
                            </field>
                            <field>
                                <name>ITC</name>
                                <description>Terminal count interrupt mask. When cleared, this bit
                                    masks out the terminal count interrupt of the relevant channel.</description>
                                <bitRange>[15:15]</bitRange>
                            </field>
                            <field>
                                <name>L</name>
                                <description>Lock. When set, this bit enables locked transfers. This
                                    information is not used in the LPC178x/177x.</description>
                                <bitRange>[16:16]</bitRange>
                            </field>
                            <field>
                                <name>A</name>
                                <description>Active: 0 = there is no data in the FIFO of the
                                    channel. 1 = the channel FIFO has data. This value can be used
                                    with the Halt and Channel Enable bits to cleanly disable a DMA
                                    channel. This is a read-only bit.</description>
                                <bitRange>[17:17]</bitRange>
                            </field>
                            <field>
                                <name>H</name>
                                <description>Halt: 0 = enable DMA requests. 1 = ignore further
                                    source DMA requests. The contents of the channel FIFO are
                                    drained. This value can be used with the Active and Channel
                                    Enable bits to cleanly disable a DMA channel.</description>
                                <bitRange>[18:18]</bitRange>
                            </field>
                            <field>
                                <name>RESERVED</name>
                                <description>Reserved. Read value is undefined, only zero should be
                                    written.</description>
                                <bitRange>[31:19]</bitRange>
                            </field>
                        </fields>
                    </register>
                </cluster>
            </registers>
        </peripheral>
        <peripheral>
            <name>USB</name>
            <description>USB device/host/OTG controller</description>
            <groupName>USB</groupName>
            <baseAddress>0x5000c000</baseAddress>
            <addressBlock>
                <offset>0x0</offset>
                <size>0xFFF</size>
                <usage>registers</usage>
            </addressBlock>
            <interrupt>
                <name>USB</name>
                <value>24</value>
            </interrupt>
            <interrupt>
                <name>USBActivity</name>
                <value>33</value>
            </interrupt>
            <registers>
                <register>
                    <name>INTST</name>
                    <description>OTG Interrupt Status</description>
                    <addressOffset>0x100</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TMR</name>
                            <description>Timer time-out.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>REMOVE_PU</name>
                            <description>Remove pull-up. This bit is set by hardware to indicate
                                that software needs to disable the D+ pull-up resistor.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>HNP_FAILURE</name>
                            <description>HNP failed. This bit is set by hardware to indicate that
                                the HNP switching has failed.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>HNP_SUCCESS</name>
                            <description>HNP succeeded. This bit is set by hardware to indicate that
                                the HNP switching has succeeded.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTEN</name>
                    <description>OTG Interrupt Enable</description>
                    <addressOffset>0x104</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TMR_EN</name>
                            <description>1 = enable the corresponding bit in the IntSt register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>REMOVE_PU_EN</name>
                            <description>1 = enable the corresponding bit in the IntSt register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>HNP_FAILURE_EN</name>
                            <description>1 = enable the corresponding bit in the IntSt register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>HNP_SUCCES_EN</name>
                            <description>1 = enable the corresponding bit in the IntSt register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTSET</name>
                    <description>OTG Interrupt Set</description>
                    <addressOffset>0x108</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>TMR_SET</name>
                            <description>0 = no effect. 1 = set the corresponding bit in the IntSt
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>REMOVE_PU_SET</name>
                            <description>0 = no effect. 1 = set the corresponding bit in the IntSt
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>HNP_FAILURE_SET</name>
                            <description>0 = no effect. 1 = set the corresponding bit in the IntSt
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>HNP_SUCCES_SET</name>
                            <description>0 = no effect. 1 = set the corresponding bit in the IntSt
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>INTCLR</name>
                    <description>OTG Interrupt Clear</description>
                    <addressOffset>0x10C</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>TMR_CLR</name>
                            <description>0 = no effect. 1 = clear the corresponding bit in the IntSt
                                register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>REMOVE_PU_CLR</name>
                            <description>0 = no effect. 1 = clear the corresponding bit in the IntSt
                                register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>HNP_FAILURE_CLR</name>
                            <description>0 = no effect. 1 = clear the corresponding bit in the IntSt
                                register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>HNP_SUCCES_CLR</name>
                            <description>0 = no effect. 1 = clear the corresponding bit in the IntSt
                                register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:4]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>STCTRL</name>
                    <description>OTG Status and Control and USB port select</description>
                    <addressOffset>0x110</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PORT_FUNC</name>
                            <description>Controls connection of USB functions (see Figure 51). Bit 0
                                is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set
                                and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host
                                01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 =
                                device In a device-only configuration, the following values are
                                allowed: 00: U1 = device. The USB device controller signals are
                                mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1.
                                11: U2 = device. The USB device controller signals are mapped to the
                                U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2.</description>
                            <bitRange>[1:0]</bitRange>
                        </field>
                        <field>
                            <name>TMR_SCALE</name>
                            <description>Timer scale selection. This field determines the duration
                                of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10:
                                1000 ms (1 KHz) 11: Reserved</description>
                            <bitRange>[3:2]</bitRange>
                        </field>
                        <field>
                            <name>TMR_MODE</name>
                            <description>Timer mode selection. 0: monoshot 1: free running</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>TMR_EN</name>
                            <description>Timer enable. When set, TMR_CNT increments. When cleared,
                                TMR_CNT is reset to 0.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>TMR_RST</name>
                            <description>Timer reset. Writing one to this bit resets TMR_CNT to 0.
                                This provides a single bit control for the software to restart the
                                timer when the timer is enabled.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>B_HNP_TRACK</name>
                            <description>Enable HNP tracking for B-device (peripheral), see Section
                                14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is
                                set.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>A_HNP_TRACK</name>
                            <description>Enable HNP tracking for A-device (host), see Section 14.9.
                                Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PU_REMOVED</name>
                            <description>When the B-device changes its role from peripheral to host,
                                software sets this bit when it removes the D+ pull-up, see Section
                                14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is
                                set.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[15:11]</bitRange>
                        </field>
                        <field>
                            <name>TMR_CNT</name>
                            <description>Current timer count value.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TMR</name>
                    <description>OTG Timer</description>
                    <addressOffset>0x114</addressOffset>
                    <access>read-write</access>
                    <resetValue>0xFFFF</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TIMEOUT_CNT</name>
                            <description>The TMR interrupt is set when TMR_CNT reaches this value.</description>
                            <bitRange>[15:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:16]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DEVINTST</name>
                    <description>USB Device Interrupt Status</description>
                    <addressOffset>0x200</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x10</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FRAME</name>
                            <description>The frame interrupt occurs every 1 ms. This is used in
                                isochronous packet transfers.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EP_FAST</name>
                            <description>Fast endpoint interrupt. If an Endpoint Interrupt Priority
                                register (USBEpIntPri) bit is set, the corresponding endpoint
                                interrupt will be routed to this bit.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EP_SLOW</name>
                            <description>Slow endpoints interrupt. If an Endpoint Interrupt Priority
                                Register (USBEpIntPri) bit is not set, the corresponding endpoint
                                interrupt will be routed to this bit.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DEV_STAT</name>
                            <description>Set when USB Bus reset, USB suspend change or Connect
                                change event occurs. Refer to Section 13.12.6 Set Device Status
                                (Command: 0xFE, Data: write 1 byte) on page 366.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CCEMPTY</name>
                            <description>The command code register (USBCmdCode) is empty (New
                                command can be written).</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>CDFULL</name>
                            <description>Command data register (USBCmdData) is full (Data can be
                                read now).</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RxENDPKT</name>
                            <description>The current packet in the endpoint buffer is transferred to
                                the CPU.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TxENDPKT</name>
                            <description>The number of data bytes transferred to the endpoint buffer
                                equals the number of bytes programmed in the TxPacket length
                                register (USBTxPLen).</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EP_RLZED</name>
                            <description>Endpoints realized. Set when Realize Endpoint register
                                (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the
                                corresponding operation is completed.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INT</name>
                            <description>Error Interrupt. Any bus error interrupt from the USB
                                device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB,
                                Data: read 1 byte) on page 368</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DEVINTEN</name>
                    <description>USB Device Interrupt Enable</description>
                    <addressOffset>0x204</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FRAMEEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EP_FASTEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EP_SLOWEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DEV_STATEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CCEMPTYEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>CDFULLEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RxENDPKTEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TxENDPKTEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EP_RLZEDEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INTEN</name>
                            <description>0 = No interrupt is generated. 1 = An interrupt will be
                                generated when the corresponding bit in the Device Interrupt Status
                                (USBDevIntSt) register (Table 261) is set. By default, the interrupt
                                is routed to the USB_INT_REQ_LP interrupt line. Optionally, either
                                the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP
                                interrupt line by changing the value of USBDevIntPri.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DEVINTCLR</name>
                    <description>USB Device Interrupt Clear</description>
                    <addressOffset>0x208</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FRAMECLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EP_FASTCLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EP_SLOWCLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DEV_STATCLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CCEMPTYCLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>CDFULLCLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RxENDPKTCLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TxENDPKTCLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EP_RLZEDCLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INTCLR</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is cleared.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DEVINTSET</name>
                    <description>USB Device Interrupt Set</description>
                    <addressOffset>0x20C</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FRAMESET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EP_FASTSET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EP_SLOWSET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>DEV_STATSET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>CCEMPTYSET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>CDFULLSET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>RxENDPKTSET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>TxENDPKTSET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EP_RLZEDSET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>ERR_INTSET</name>
                            <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt
                                (Section 13.10.3.2) is set.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CMDCODE</name>
                    <description>USB Command Code</description>
                    <addressOffset>0x210</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>CMD_PHASE</name>
                            <description>The command phase:</description>
                            <bitRange>[15:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>READ</name>
                                    <description>Read</description>
                                    <value>0x02</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>WRITE</name>
                                    <description>Write</description>
                                    <value>0x01</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>COMMAND</name>
                                    <description>Command</description>
                                    <value>0x05</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>CMD_CODE_WDATA</name>
                            <description>This is a multi-purpose field. When CMD_PHASE is Command or
                                Read, this field contains the code for the command (CMD_CODE). When
                                CMD_PHASE is Write, this field contains the command write data
                                (CMD_WDATA).</description>
                            <bitRange>[23:16]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:24]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CMDDATA</name>
                    <description>USB Command Data</description>
                    <addressOffset>0x214</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CMD_RDATA</name>
                            <description>Command Read Data.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXDATA</name>
                    <description>USB Receive Data</description>
                    <addressOffset>0x218</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RX_DATA</name>
                            <description>Data received.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXDATA</name>
                    <description>USB Transmit Data</description>
                    <addressOffset>0x21C</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TX_DATA</name>
                            <description>Transmit Data.</description>
                            <bitRange>[31:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>RXPLEN</name>
                    <description>USB Receive Packet Length</description>
                    <addressOffset>0x220</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PKT_LNGTH</name>
                            <description>The remaining number of bytes to be read from the currently
                                selected endpoint's buffer. When this field decrements to 0, the
                                RxENDPKT bit will be set in USBDevIntSt.</description>
                            <bitRange>[9:0]</bitRange>
                        </field>
                        <field>
                            <name>DV</name>
                            <description>Data valid. This bit is useful for isochronous endpoints.
                                Non-isochronous endpoints do not raise an interrupt when an
                                erroneous data packet is received. But invalid data packet can be
                                produced with a bus reset. For isochronous endpoints, data transfer
                                will happen even if an erroneous packet is received. In this case DV
                                bit will not be set for the packet.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DATA_IS_INVALID_</name>
                                    <description>Data is invalid.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DATA_IS_VALID_</name>
                                    <description>Data is valid.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>PKT_RDY</name>
                            <description>The PKT_LNGTH field is valid and the packet is ready for
                                reading.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>TXPLEN</name>
                    <description>USB Transmit Packet Length</description>
                    <addressOffset>0x224</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PKT_LNGTH</name>
                            <description>The remaining number of bytes to be written to the selected
                                endpoint buffer. This field is decremented by 4 by hardware after
                                each write to USBTxData. When this field decrements to 0, the
                                TxENDPKT bit will be set in USBDevIntSt.</description>
                            <bitRange>[9:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CTRL</name>
                    <description>USB Control</description>
                    <addressOffset>0x228</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RD_EN</name>
                            <description>Read mode control. Enables reading data from the OUT
                                endpoint buffer for the endpoint specified in the LOG_ENDPOINT field
                                using the USBRxData register. This bit is cleared by hardware when
                                the last word of the current packet is read from USBRxData.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED_</name>
                                    <description>Enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>WR_EN</name>
                            <description>Write mode control. Enables writing data to the IN endpoint
                                buffer for the endpoint specified in the LOG_ENDPOINT field using
                                the USBTxData register. This bit is cleared by hardware when the
                                number of bytes in USBTxLen have been sent.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED_</name>
                                    <description>Enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>LOG_ENDPOINT</name>
                            <description>Logical Endpoint number.</description>
                            <bitRange>[5:2]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:6]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DEVINTPRI</name>
                    <description>USB Device Interrupt Priority</description>
                    <addressOffset>0x22C</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>FRAME</name>
                            <description>Frame interrupt routing</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LP</name>
                                    <description>FRAME interrupt is routed to USB_INT_REQ_LP.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>HP</name>
                                    <description>FRAME interrupt is routed to USB_INT_REQ_HP.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>EP_FAST</name>
                            <description>Fast endpoint interrupt routing</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>LP</name>
                                    <description>EP_FAST interrupt is routed to USB_INT_REQ_LP.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>HP</name>
                                    <description>EP_FAST interrupt is routed to USB_INT_REQ_HP.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EPINTST</name>
                    <description>USB Endpoint Interrupt Status</description>
                    <addressOffset>0x230</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPST0</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPST1</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPST2</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPST3</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPST4</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPST5</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPST6</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPST7</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPST8</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPST9</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPST10</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPST11</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPST12</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPST13</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPST14</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPST15</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPST16</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPST17</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPST18</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPST19</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPST20</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPST21</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPST22</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPST23</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPST24</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPST25</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPST26</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPST27</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPST28</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPST29</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPST30</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPST31</name>
                            <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or
                                Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EPINTEN</name>
                    <description>USB Endpoint Interrupt Enable</description>
                    <addressOffset>0x234</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPEN0</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPEN1</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPEN2</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPEN3</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPEN4</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPEN5</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPEN6</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPEN7</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPEN8</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPEN9</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPEN10</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPEN11</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPEN12</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPEN13</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPEN14</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPEN15</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPEN16</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPEN17</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPEN18</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPEN19</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPEN20</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPEN21</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPEN22</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPEN23</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPEN24</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPEN25</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPEN26</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPEN27</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPEN28</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPEN29</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPEN30</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPEN31</name>
                            <description>0= The corresponding bit in USBDMARSt is set when an
                                interrupt occurs for this endpoint. 1 = The corresponding bit in
                                USBEpIntSt is set when an interrupt occurs for this endpoint.
                                Implies Slave mode for this endpoint.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EPINTCLR</name>
                    <description>USB Endpoint Interrupt Clear</description>
                    <addressOffset>0x238</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPCLR0</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR1</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR2</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR3</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR4</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR5</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR6</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR7</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR8</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR9</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR10</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR11</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR12</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR13</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR14</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR15</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR16</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR17</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR18</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR19</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR20</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR21</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR22</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR23</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR24</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR25</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR26</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR27</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR28</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR29</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR30</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPCLR31</name>
                            <description>0 = No effect. 1 = Clears the corresponding bit in
                                USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt
                                command for this endpoint.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EPINTSET</name>
                    <description>USB Endpoint Interrupt Set</description>
                    <addressOffset>0x23C</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPSET0</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPSET1</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPSET2</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPSET3</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPSET4</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPSET5</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPSET6</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPSET7</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPSET8</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPSET9</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPSET10</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPSET11</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPSET12</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPSET13</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPSET14</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPSET15</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPSET16</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPSET17</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPSET18</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPSET19</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPSET20</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPSET21</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPSET22</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPSET23</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPSET24</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPSET25</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPSET26</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPSET27</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPSET28</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPSET29</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPSET30</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPSET31</name>
                            <description>0 = No effect. 1 = Sets the corresponding bit in
                                USBEpIntSt.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EPINTPRI</name>
                    <description>USB Endpoint Priority</description>
                    <addressOffset>0x240</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPPRI0</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI1</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI2</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI3</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI4</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI5</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI6</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI7</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI8</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI9</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI10</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI11</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI12</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI13</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI14</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI15</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI16</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI17</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI18</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI19</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI20</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI21</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI22</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI23</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI24</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI25</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI26</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI27</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI28</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI29</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI30</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPPRI31</name>
                            <description>0 = The corresponding interrupt is routed to the EP_SLOW
                                bit of USBDevIntSt 1 = The corresponding interrupt is routed to the
                                EP_FAST bit of USBDevIntSt</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>REEP</name>
                    <description>USB Realize Endpoint</description>
                    <addressOffset>0x244</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x3</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPR0</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPR1</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPR2</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPR3</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPR4</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPR5</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPR6</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPR7</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPR8</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPR9</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPR10</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPR11</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPR12</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPR13</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPR14</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPR15</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPR16</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPR17</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPR18</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPR19</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPR20</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPR21</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPR22</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPR23</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPR24</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPR25</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPR26</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPR27</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPR28</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPR29</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPR30</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPR31</name>
                            <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is
                                realized.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EPIND</name>
                    <description>USB Endpoint Index</description>
                    <addressOffset>0x248</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PHY_EP</name>
                            <description>Physical endpoint number (0-31)</description>
                            <bitRange>[4:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MAXPSIZE</name>
                    <description>USB MaxPacketSize</description>
                    <addressOffset>0x24C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x8</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>MPS</name>
                            <description>The maximum packet size value.</description>
                            <bitRange>[9:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DMARST</name>
                    <description>USB DMA Request Status</description>
                    <addressOffset>0x250</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPRST0</name>
                            <description>Control endpoint OUT (DMA cannot be enabled for this
                                endpoint and EP0 bit must be 0).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPRST1</name>
                            <description>Control endpoint IN (DMA cannot be enabled for this
                                endpoint and EP1 bit must be 0).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPRST2</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPRST3</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPRST4</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPRST5</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPRST6</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPRST7</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPRST8</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPRST9</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPRST10</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPRST11</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPRST12</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPRST13</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPRST14</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPRST15</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPRST16</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPRST17</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPRST18</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPRST19</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPRST20</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPRST21</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPRST22</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPRST23</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPRST24</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPRST25</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPRST26</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPRST27</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPRST28</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPRST29</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPRST30</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPRST31</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 = DMA not
                                requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DMARCLR</name>
                    <description>USB DMA Request Clear</description>
                    <addressOffset>0x254</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPRCLR0</name>
                            <description>Control endpoint OUT (DMA cannot be enabled for this
                                endpoint and the EP0 bit must be 0).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR1</name>
                            <description>Control endpoint IN (DMA cannot be enabled for this
                                endpoint and the EP1 bit must be 0).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR2</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR3</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR4</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR5</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR6</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR7</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR8</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR9</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR10</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR11</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR12</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR13</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR14</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR15</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR16</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR17</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR18</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR19</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR20</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR21</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR22</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR23</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR24</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR25</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR26</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR27</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR28</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR29</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR30</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPRCLR31</name>
                            <description>Clear the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0
                                = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DMARSET</name>
                    <description>USB DMA Request Set</description>
                    <addressOffset>0x258</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPRSET0</name>
                            <description>Control endpoint OUT (DMA cannot be enabled for this
                                endpoint and the EP0 bit must be 0).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET1</name>
                            <description>Control endpoint IN (DMA cannot be enabled for this
                                endpoint and the EP1 bit must be 0).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET2</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET3</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET4</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET5</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET6</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET7</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET8</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET9</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET10</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET11</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET12</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET13</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET14</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET15</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET16</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET17</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET18</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET19</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET20</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET21</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET22</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET23</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET24</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET25</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET26</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET27</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET28</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET29</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET30</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPRSET31</name>
                            <description>Set the endpoint xx (2 &lt;= xx &lt;= 31) DMA request. 0 =
                                No effect 1 = Set the corresponding bit in USBDMARSt.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>UDCAH</name>
                    <description>USB UDCA Head</description>
                    <addressOffset>0x280</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written. The UDCA is aligned to 128-byte boundaries.</description>
                            <bitRange>[6:0]</bitRange>
                        </field>
                        <field>
                            <name>UDCA_ADDR</name>
                            <description>Start address of the UDCA.</description>
                            <bitRange>[31:7]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EPDMAST</name>
                    <description>USB Endpoint DMA Status</description>
                    <addressOffset>0x284</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EP_DMA_ST0</name>
                            <description>Control endpoint OUT (DMA cannot be enabled for this
                                endpoint and the EP0_DMA_ENABLE bit must be 0).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST1</name>
                            <description>Control endpoint IN (DMA cannot be enabled for this
                                endpoint and the EP1_DMA_ENABLE bit must be 0).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST2</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST3</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST4</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST5</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST6</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST7</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST8</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST9</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST10</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST11</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST12</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST13</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST14</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST15</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST16</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST17</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST18</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST19</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST20</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST21</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST22</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST23</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST24</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST25</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST26</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST27</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST28</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST29</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST30</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_ST31</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA enabled bit. 0 = The
                                DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is
                                enabled.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EPDMAEN</name>
                    <description>USB Endpoint DMA Enable</description>
                    <addressOffset>0x288</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EP_DMA_EN0</name>
                            <description>Control endpoint OUT (DMA cannot be enabled for this
                                endpoint and the EP0_DMA_ENABLE bit value must be 0).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_EN1</name>
                            <description>Control endpoint IN (DMA cannot be enabled for this
                                endpoint and the EP1_DMA_ENABLE bit must be 0).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_EN</name>
                            <description>Endpoint xx(2 &lt;= xx &lt;= 31) DMA enable control bit. 0
                                = No effect. 1 = Enable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[31:2]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EPDMADIS</name>
                    <description>USB Endpoint DMA Disable</description>
                    <addressOffset>0x28C</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EP_DMA_DIS0</name>
                            <description>Control endpoint OUT (DMA cannot be enabled for this
                                endpoint and the EP0_DMA_DISABLE bit value must be 0).</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS1</name>
                            <description>Control endpoint IN (DMA cannot be enabled for this
                                endpoint and the EP1_DMA_DISABLE bit value must be 0).</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS2</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS3</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS4</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS5</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS6</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS7</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS8</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS9</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS10</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS11</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS12</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS13</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS14</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS15</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS16</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS17</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS18</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS19</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS20</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS21</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS22</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS23</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS24</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS25</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS26</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS27</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS28</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS29</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS30</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EP_DMA_DIS31</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) DMA disable control bit.
                                0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DMAINTST</name>
                    <description>USB DMA Interrupt Status</description>
                    <addressOffset>0x290</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EOT</name>
                            <description>End of Transfer Interrupt bit.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ALL_BITS_IN_THE_USBE</name>
                                    <description>All bits in the USBEoTIntSt register are 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>AT_LEAST_ONE_BIT_IN_</name>
                                    <description>At least one bit in the USBEoTIntSt is set.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>NDDR</name>
                            <description>New DD Request Interrupt bit.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ALL_BITS_IN_THE_USBN</name>
                                    <description>All bits in the USBNDDRIntSt register are 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>AT_LEAST_ONE_BIT_IN_</name>
                                    <description>At least one bit in the USBNDDRIntSt is set.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ERR</name>
                            <description>System Error Interrupt bit.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ALL_BITS_IN_THE_USBS</name>
                                    <description>All bits in the USBSysErrIntSt register are 0.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>AT_LEAST_ONE_BIT_IN_</name>
                                    <description>At least one bit in the USBSysErrIntSt is set.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>DMAINTEN</name>
                    <description>USB DMA Interrupt Enable</description>
                    <addressOffset>0x294</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EOT</name>
                            <description>End of Transfer Interrupt enable bit.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED_</name>
                                    <description>Enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>NDDR</name>
                            <description>New DD Request Interrupt enable bit.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED_</name>
                                    <description>Enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>ERR</name>
                            <description>System Error Interrupt enable bit.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLED_</name>
                                    <description>Disabled.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLED_</name>
                                    <description>Enabled.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:3]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EOTINTST</name>
                    <description>USB End of Transfer Interrupt Status</description>
                    <addressOffset>0x2A0</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPTXINTST0</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST1</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST2</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST3</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST4</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST5</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST6</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST7</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST8</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST9</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST10</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST11</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST12</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST13</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST14</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST15</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST16</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST17</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST18</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST19</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST20</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST21</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST22</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST23</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST24</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST25</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST26</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST27</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST28</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST29</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST30</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTST31</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer Interrupt
                                request. 0 = There is no End of Transfer interrupt request for
                                endpoint xx. 1 = There is an End of Transfer Interrupt request for
                                endpoint xx.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EOTINTCLR</name>
                    <description>USB End of Transfer Interrupt Clear</description>
                    <addressOffset>0x2A4</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPTXINTCLR0</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR1</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR2</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR3</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR4</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR5</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR6</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR7</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR8</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR9</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR10</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR11</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR12</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR13</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR14</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR15</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR16</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR17</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR18</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR19</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR20</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR21</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR22</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR23</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR24</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR25</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR26</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR27</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR28</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR29</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR30</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTCLR31</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>EOTINTSET</name>
                    <description>USB End of Transfer Interrupt Set</description>
                    <addressOffset>0x2A8</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPTXINTSET0</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET1</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET2</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET3</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET4</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET5</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET6</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET7</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET8</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET9</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET10</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET11</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET12</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET13</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET14</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET15</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET16</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET17</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET18</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET19</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET20</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET21</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET22</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET23</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET24</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET25</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET26</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET27</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET28</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET29</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET30</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPTXINTSET31</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) End of Transfer
                                Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer
                                Interrupt request in the USBEoTIntSt register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>NDDRINTST</name>
                    <description>USB New DD Request Interrupt Status</description>
                    <addressOffset>0x2AC</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPNDDINTST0</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST1</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST2</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST3</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST4</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST5</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST6</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST7</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST8</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST9</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST10</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST11</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST12</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST13</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST14</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST15</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST16</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST17</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST18</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST19</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST20</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST21</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST22</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST23</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST24</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST25</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST26</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST27</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST28</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST29</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST30</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTST31</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt request.
                                0 = There is no new DD interrupt request for endpoint xx. 1 = There
                                is a new DD interrupt request for endpoint xx.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>NDDRINTCLR</name>
                    <description>USB New DD Request Interrupt Clear</description>
                    <addressOffset>0x2B0</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPNDDINTCLR0</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR1</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR2</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR3</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR4</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR5</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR6</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR7</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR8</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR9</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR10</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR11</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR12</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR13</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR14</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR15</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR16</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR17</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR18</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR19</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR20</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR21</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR22</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR23</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR24</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR25</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR26</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR27</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR28</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR29</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR30</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTCLR31</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request
                                in the USBNDDRIntSt register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>NDDRINTSET</name>
                    <description>USB New DD Request Interrupt Set</description>
                    <addressOffset>0x2B4</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPNDDINTSET0</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET1</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET2</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET3</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET4</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET5</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET6</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET7</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET8</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET9</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET10</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET11</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET12</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET13</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET14</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET15</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET16</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET17</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET18</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET19</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET20</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET21</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET22</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET23</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET24</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET25</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET26</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET27</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET28</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET29</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET30</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPNDDINTSET31</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) new DD interrupt
                                request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in
                                the USBNDDRIntSt register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SYSERRINTST</name>
                    <description>USB System Error Interrupt Status</description>
                    <addressOffset>0x2B8</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPERRINTST0</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST1</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST2</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST3</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST4</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST5</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST6</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST7</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST8</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST9</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST10</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST11</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST12</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST13</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST14</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST15</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST16</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST17</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST18</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST19</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST20</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST21</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST22</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST23</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST24</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST25</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST26</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST27</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST28</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST29</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST30</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTST31</name>
                            <description>Endpoint xx (2 &lt;= xx &lt;= 31) System Error Interrupt
                                request. 0 = There is no System Error Interrupt request for endpoint
                                xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SYSERRINTCLR</name>
                    <description>USB System Error Interrupt Clear</description>
                    <addressOffset>0x2BC</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPERRINTCLR0</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR1</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR2</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR3</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR4</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR5</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR6</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR7</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR8</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR9</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR10</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR11</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR12</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR13</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR14</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR15</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR16</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR17</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR18</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR19</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR20</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR21</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR22</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR23</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR24</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR25</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR26</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR27</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR28</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR29</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR30</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTCLR31</name>
                            <description>Clear endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SYSERRINTSET</name>
                    <description>USB System Error Interrupt Set</description>
                    <addressOffset>0x2C0</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>EPERRINTSET0</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET1</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET2</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET3</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET4</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET5</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET6</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET7</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET8</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET9</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET10</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET11</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET12</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET13</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET14</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET15</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET16</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET17</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET18</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET19</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET20</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET21</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET22</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET23</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET24</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET25</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET26</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET27</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET28</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET29</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET30</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>EPERRINTSET31</name>
                            <description>Set endpoint xx (2 &lt;= xx &lt;= 31) System Error
                                Interrupt request. 0 = No effect. 1 = Set the EPxx System Error
                                Interrupt request in the USBSysErrIntSt register.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>I2C_RX</name>
                    <description>I2C Receive</description>
                    <addressOffset>0x300</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>RXDATA</name>
                            <description>Receive data.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>I2C_WO</name>
                    <description>I2C Transmit</description>
                    <alternateRegister>I2C_RX</alternateRegister>
                    <addressOffset>0x300</addressOffset>
                    <access>write-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0x00000000</resetMask>
                    <fields>
                        <field>
                            <name>TXDATA</name>
                            <description>Transmit data.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>START</name>
                            <description>When 1, issue a START condition before transmitting this
                                byte.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>STOP</name>
                            <description>When 1, issue a STOP condition after transmitting this
                                byte.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:10]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>I2C_STS</name>
                    <description>I2C Status</description>
                    <addressOffset>0x304</addressOffset>
                    <access>read-only</access>
                    <resetValue>0x0A00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TDI</name>
                            <description>Transaction Done Interrupt. This flag is set if a
                                transaction completes successfully. It is cleared by writing a one
                                to bit 0 of the status register. It is unaffected by slave
                                transactions.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NOT_COMPLETE</name>
                                    <description>Transaction has not completed.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>COMPLETE</name>
                                    <description>Transaction completed.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>AFI</name>
                            <description>Arbitration Failure Interrupt. When transmitting, if the
                                SDA is low when SDAOUT is high, then this I2C has lost the
                                arbitration to another device on the bus. The Arbitration Failure
                                bit is set when this happens. It is cleared by writing a one to bit
                                1 of the status register.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_ARBITRATION_FAILU</name>
                                    <description>No arbitration failure on last transmission.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ARBITRATION_FAILURE_</name>
                                    <description>Arbitration failure occurred on last transmission.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>NAI</name>
                            <description>No Acknowledge Interrupt. After every byte of data is sent,
                                the transmitter expects an acknowledge from the receiver. This bit
                                is set if the acknowledge is not received. It is cleared when a byte
                                is written to the master TX FIFO.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>ACKNOWLEDGE_RCVD</name>
                                    <description>Last transmission received an acknowledge.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NO_ACKNOWLEDGE_RCVD</name>
                                    <description>Last transmission did not receive an acknowledge.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DRMI</name>
                            <description>Master Data Request Interrupt. Once a transmission is
                                started, the transmitter must have data to transmit as long as it
                                isn't followed by a stop condition or it will hold SCL low until
                                more data is available. The Master Data Request bit is set when the
                                master transmitter is data-starved. If the master TX FIFO is empty
                                and the last byte did not have a STOP condition flag, then SCL is
                                held low until the CPU writes another byte to transmit. This bit is
                                cleared when a byte is written to the master TX FIFO.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>BUSY</name>
                                    <description>Master transmitter does not need data.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NEED_DATA</name>
                                    <description>Master transmitter needs data.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DRSI</name>
                            <description>Slave Data Request Interrupt. Once a transmission is
                                started, the transmitter must have data to transmit as long as it
                                isn't followed by a STOP condition or it will hold SCL low until
                                more data is available. The Slave Data Request bit is set when the
                                slave transmitter is data-starved. If the slave TX FIFO is empty and
                                the last byte transmitted was acknowledged, then SCL is held low
                                until the CPU writes another byte to transmit. This bit is cleared
                                when a byte is written to the slave Tx FIFO.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>BUSY</name>
                                    <description>Slave transmitter does not need data.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>NEED_DATA</name>
                                    <description>Slave transmitter needs data.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>Active</name>
                            <description>Indicates whether the bus is busy. This bit is set when a
                                START condition has been seen. It is cleared when a STOP condition
                                is seen..</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>SCL</name>
                            <description>The current value of the SCL signal.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>SDA</name>
                            <description>The current value of the SDA signal.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>RFF</name>
                            <description>Receive FIFO Full (RFF). This bit is set when the RX FIFO
                                is full and cannot accept any more data. It is cleared when the RX
                                FIFO is not full. If a byte arrives when the Receive FIFO is full,
                                the SCL is held low until the CPU reads the RX FIFO and makes room
                                for it.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>RX_FIFO_IS_NOT_FULL</name>
                                    <description>RX FIFO is not full</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RX_FIFO_IS_FULL</name>
                                    <description>RX FIFO is full</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RFE</name>
                            <description>Receive FIFO Empty. RFE is set when the RX FIFO is empty
                                and is cleared when the RX FIFO contains valid data.</description>
                            <bitRange>[9:9]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DATA</name>
                                    <description>RX FIFO contains data.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EMPTY</name>
                                    <description>RX FIFO is empty</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TFF</name>
                            <description>Transmit FIFO Full. TFF is set when the TX FIFO is full and
                                is cleared when the TX FIFO is not full.</description>
                            <bitRange>[10:10]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>TX_FIFO_IS_NOT_FULL_</name>
                                    <description>TX FIFO is not full.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>TX_FIFO_IS_FULL</name>
                                    <description>TX FIFO is full</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TFE</name>
                            <description>Transmit FIFO Empty. TFE is set when the TX FIFO is empty
                                and is cleared when the TX FIFO contains valid data.</description>
                            <bitRange>[11:11]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>VALID_DATA</name>
                                    <description>TX FIFO contains valid data.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>EMPTY</name>
                                    <description>TX FIFO is empty</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:12]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>I2C_CTL</name>
                    <description>I2C Control</description>
                    <addressOffset>0x308</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>TDIE</name>
                            <description>Transmit Done Interrupt Enable. This enables the TDI
                                interrupt signalling that this I2C issued a STOP condition.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_TDI_INTE</name>
                                    <description>Disable the TDI interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_TDI_INTER</name>
                                    <description>Enable the TDI interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>AFIE</name>
                            <description>Transmitter Arbitration Failure Interrupt Enable. This
                                enables the AFI interrupt which is asserted during transmission when
                                trying to set SDA high, but the bus is driven low by another device.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_AFI_</name>
                                    <description>Disable the AFI.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_AFI_</name>
                                    <description>Enable the AFI.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>NAIE</name>
                            <description>Transmitter No Acknowledge Interrupt Enable. This enables
                                the NAI interrupt signalling that transmitted byte was not
                                acknowledged.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_NAI_</name>
                                    <description>Disable the NAI.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_NAI_</name>
                                    <description>Enable the NAI.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DRMIE</name>
                            <description>Master Transmitter Data Request Interrupt Enable. This
                                enables the DRMI interrupt which signals that the master transmitter
                                has run out of data, has not issued a STOP, and is holding the SCL
                                line low.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_DRMI_INT</name>
                                    <description>Disable the DRMI interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_DRMI_INTE</name>
                                    <description>Enable the DRMI interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DRSIE</name>
                            <description>Slave Transmitter Data Request Interrupt Enable. This
                                enables the DRSI interrupt which signals that the slave transmitter
                                has run out of data and the last byte was acknowledged, so the SCL
                                line is being held low.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_DRSI_INT</name>
                                    <description>Disable the DRSI interrupt.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_DRSI_INTE</name>
                                    <description>Enable the DRSI interrupt.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>REFIE</name>
                            <description>Receive FIFO Full Interrupt Enable. This enables the
                                Receive FIFO Full interrupt to indicate that the receive FIFO cannot
                                accept any more data.</description>
                            <bitRange>[5:5]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_RFFI_</name>
                                    <description>Disable the RFFI.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_RFFI_</name>
                                    <description>Enable the RFFI.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RFDAIE</name>
                            <description>Receive Data Available Interrupt Enable. This enables the
                                DAI interrupt to indicate that data is available in the receive FIFO
                                (i.e. not empty).</description>
                            <bitRange>[6:6]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_DAI_</name>
                                    <description>Disable the DAI.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_DAI_</name>
                                    <description>Enable the DAI.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>TFFIE</name>
                            <description>Transmit FIFO Not Full Interrupt Enable. This enables the
                                Transmit FIFO Not Full interrupt to indicate that the more data can
                                be written to the transmit FIFO. Note that this is not full. It is
                                intended help the CPU to write to the I2C block only when there is
                                room in the FIFO and do this without polling the status register.</description>
                            <bitRange>[7:7]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_TFFI_</name>
                                    <description>Disable the TFFI.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_TFFI_</name>
                                    <description>Enable the TFFI.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>SRST</name>
                            <description>Soft reset. This is only needed in unusual circumstances.
                                If a device issues a start condition without issuing a stop
                                condition. A system timer may be used to reset the I2C if the bus
                                remains busy longer than the time-out period. On a soft reset, the
                                Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all
                                internal state machines are reset to appear idle. The I2C_CLKHI,
                                I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a
                                soft reset.</description>
                            <bitRange>[8:8]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>NO_RESET</name>
                                    <description>No reset.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>RESET</name>
                                    <description>Reset the I2C to idle state. Self clearing.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:9]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>I2C_CLKHI</name>
                    <description>I2C Clock High</description>
                    <addressOffset>0x30C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0xB9</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CDHI</name>
                            <description>Clock divisor high. This value is the number of 48 MHz
                                clocks the serial clock (SCL) will be high.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>I2C_CLKLO</name>
                    <description>I2C Clock Low</description>
                    <addressOffset>0x310</addressOffset>
                    <access>write-only</access>
                    <resetValue>0xB9</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>CDLO</name>
                            <description>Clock divisor low. This value is the number of 48 MHz
                                clocks the serial clock (SCL) will be low.</description>
                            <bitRange>[7:0]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:8]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>USBCLKCTRL</name>
                    <description>USB Clock Control</description>
                    <addressOffset>0xFF4</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>DEV_CLK_EN</name>
                            <description>Device clock enable. Enables the usbclk input to the device
                                controller</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PORTSEL_CLK_EN</name>
                            <description>Port select register clock enable.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>AHB_CLK_EN</name>
                            <description>AHB clock enable</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>OTGCLKCTRL</name>
                    <description>OTG clock controller</description>
                    <alternateRegister>USBCLKCTRL</alternateRegister>
                    <addressOffset>0xFF4</addressOffset>
                    <access>read-write</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>HOST_CLK_EN</name>
                            <description>Host clock enable</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_HOST_CLO</name>
                                    <description>Disable the Host clock.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_HOST_CLOC</name>
                                    <description>Enable the Host clock.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DEV_CLK_EN</name>
                            <description>Device clock enable</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_DEVICE_C</name>
                                    <description>Disable the Device clock.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_DEVICE_CL</name>
                                    <description>Enable the Device clock.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>I2C_CLK_EN</name>
                            <description>I2C clock enable</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_I2C_CLOC</name>
                                    <description>Disable the I2C clock.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_I2C_CLOCK</name>
                                    <description>Enable the I2C clock.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>OTG_CLK_EN</name>
                            <description>OTG clock enable. In device-only applications, this bit
                                enables access to the PORTSEL register.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_OTG_CLOC</name>
                                    <description>Disable the OTG clock.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_OTG_CLOCK</name>
                                    <description>Enable the OTG clock.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>AHB_CLK_EN</name>
                            <description>AHB master clock enable</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DISABLE_THE_AHB_CLOC</name>
                                    <description>Disable the AHB clock.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>ENABLE_THE_AHB_CLOCK</name>
                                    <description>Enable the AHB clock.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>USBCLKST</name>
                    <description>USB Clock Status</description>
                    <addressOffset>0xFF8</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>DEV_CLK_ON</name>
                            <description>Device clock on. The usbclk input to the device controller
                                is active .</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PORTSEL_CLK_ON</name>
                            <description>Port select register clock on.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>AHB_CLK_ON</name>
                            <description>AHB clock on.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. The value read from a reserved bit is not
                                defined.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>OTGCLKST</name>
                    <description>OTG clock status</description>
                    <alternateRegister>USBCLKST</alternateRegister>
                    <addressOffset>0xFF8</addressOffset>
                    <access>read-only</access>
                    <resetValue>0</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>HOST_CLK_ON</name>
                            <description>Host clock status.</description>
                            <bitRange>[0:0]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>HOST_CLOCK_IS_NOT_AV</name>
                                    <description>Host clock is not available.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>HOST_CLOCK_IS_AVAILA</name>
                                    <description>Host clock is available.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>DEV_CLK_ON</name>
                            <description>Device clock status.</description>
                            <bitRange>[1:1]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>DEVICE_CLOCK_IS_NOT_</name>
                                    <description>Device clock is not available.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>DEVICE_CLOCK_IS_AVAI</name>
                                    <description>Device clock is available.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>I2C_CLK_ON</name>
                            <description>I2C clock status.</description>
                            <bitRange>[2:2]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>I2C_CLOCK_IS_NOT_AVA</name>
                                    <description>I2C clock is not available.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>I2C_CLOCK_IS_AVAILAB</name>
                                    <description>I2C clock is available.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>OTG_CLK_ON</name>
                            <description>OTG clock status.</description>
                            <bitRange>[3:3]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>OTG_CLOCK_IS_NOT_AVA</name>
                                    <description>OTG clock is not available.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>OTG_CLOCK_IS_AVAILAB</name>
                                    <description>OTG clock is available.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>AHB_CLK_ON</name>
                            <description>AHB master clock status.</description>
                            <bitRange>[4:4]</bitRange>
                            <enumeratedValues>
                                <name>ENUM</name>
                                <enumeratedValue>
                                    <name>AHB_CLOCK_IS_NOT_AVA</name>
                                    <description>AHB clock is not available.</description>
                                    <value>0</value>
                                </enumeratedValue>
                                <enumeratedValue>
                                    <name>AHB_CLOCK_IS_AVAILAB</name>
                                    <description>AHB clock is available.</description>
                                    <value>1</value>
                                </enumeratedValue>
                            </enumeratedValues>
                        </field>
                        <field>
                            <name>RESERVED</name>
                            <description>Reserved. Read value is undefined, only zero should be
                                written.</description>
                            <bitRange>[31:5]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral>
            <name>GPIO0</name>
            <description>General Purpose I/O</description>
            <groupName>GPIO</groupName>
            <baseAddress>0x2009C000</baseAddress>
            <addressBlock>
                <offset>0</offset>
                <size>0x020</size>
                <usage>registers</usage>
            </addressBlock>
            <registers>
                <register>
                    <name>DIR</name>
                    <description>GPIO Port Direction control register.</description>
                    <addressOffset>0x000</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PINDIR0</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR1</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR2</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR3</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR4</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR5</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR6</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR7</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR8</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR9</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR10</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR11</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR12</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR13</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR14</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR15</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR16</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR17</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR18</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR19</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR20</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR21</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR22</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR23</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR24</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR25</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR26</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR27</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR28</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR29</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR30</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>PINDIR31</name>
                            <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx
                                controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 =
                                Controlled pin is input. 1 = Controlled pin is output.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>MASK</name>
                    <description>Mask register for Port.</description>
                    <addressOffset>0x010</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PINMASK0</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK1</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK2</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK3</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK4</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK5</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK6</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK7</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK8</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK9</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK10</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK11</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK12</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK13</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK14</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK15</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK16</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK17</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK18</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK19</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK20</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK21</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK22</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK23</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK24</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK25</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK26</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK27</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK28</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK29</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK30</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>PINMASK31</name>
                            <description>Fast GPIO physical pin access control. 0 = Controlled pin
                                is affected by writes to the port's SETx, CLRx, and PINx
                                register(s). Current state of the pin can be read from the PINx
                                register. 1 = Controlled pin is not affected by writes into the
                                port's SETx, CLRx and PINx register(s). When the PINx register is
                                read, this bit will not be updated with the state of the physical
                                pin.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>PIN</name>
                    <description>Port Pin value register using FIOMASK.</description>
                    <addressOffset>0x014</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PINVAL0</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL1</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL2</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL3</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL4</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL5</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL6</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL7</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL8</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL9</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL10</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL11</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL12</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL13</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL14</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL15</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL16</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL17</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL18</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL19</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL20</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL21</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL22</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL23</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL24</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL25</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL26</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL27</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL28</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL29</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL30</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>PINVAL31</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds
                                to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 =
                                Controlled pin output is set to LOW. 1 = Controlled pin output is
                                set to HIGH.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>SET</name>
                    <description>Port Output Set register using FIOMASK.</description>
                    <addressOffset>0x018</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PINSET0</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PINSET1</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>PINSET2</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PINSET3</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>PINSET4</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>PINSET5</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>PINSET6</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>PINSET7</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>PINSET8</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>PINSET9</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PINSET10</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>PINSET11</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>PINSET12</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>PINSET13</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>PINSET14</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>PINSET15</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>PINSET16</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>PINSET17</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>PINSET18</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>PINSET19</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>PINSET20</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>PINSET21</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>PINSET22</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>PINSET23</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>PINSET24</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>PINSET25</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>PINSET26</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>PINSET27</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>PINSET28</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>PINSET29</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>PINSET30</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>PINSET31</name>
                            <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin
                                Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output
                                is unchanged. 1 = Controlled pin output is set to HIGH.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
                <register>
                    <name>CLR</name>
                    <description>Port Output Clear register using FIOMASK.</description>
                    <addressOffset>0x01C</addressOffset>
                    <access>read-write</access>
                    <resetValue>0x00</resetValue>
                    <resetMask>0xFFFFFFFF</resetMask>
                    <fields>
                        <field>
                            <name>PINCLR0</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[0:0]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR1</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[1:1]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR2</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[2:2]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR3</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[3:3]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR4</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[4:4]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR5</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[5:5]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR6</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[6:6]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR7</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[7:7]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR8</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[8:8]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR9</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[9:9]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR10</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[10:10]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR11</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[11:11]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR12</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[12:12]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR13</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[13:13]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR14</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[14:14]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR15</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[15:15]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR16</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[16:16]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR17</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[17:17]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR18</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[18:18]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR19</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[19:19]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR20</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[20:20]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR21</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[21:21]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR22</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[22:22]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR23</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[23:23]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR24</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[24:24]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR25</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[25:25]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR26</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[26:26]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR27</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[27:27]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR28</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[28:28]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR29</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[29:29]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR30</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[30:30]</bitRange>
                        </field>
                        <field>
                            <name>PINCLR31</name>
                            <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls
                                pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin
                                output is unchanged. 1 = Controlled pin output is set to LOW.</description>
                            <bitRange>[31:31]</bitRange>
                        </field>
                    </fields>
                </register>
            </registers>
        </peripheral>
        <peripheral derivedFrom="GPIO0">
            <name>GPIO1</name>
            <baseAddress>0x2009C020</baseAddress>
        </peripheral>
        <peripheral derivedFrom="GPIO0">
            <name>GPIO2</name>
            <baseAddress>0x2009C040</baseAddress>
        </peripheral>
        <peripheral derivedFrom="GPIO0">
            <name>GPIO3</name>
            <baseAddress>0x2009C060</baseAddress>
        </peripheral>
        <peripheral derivedFrom="GPIO0">
            <name>GPIO4</name>
            <baseAddress>0x2009C080</baseAddress>
        </peripheral>
    </peripherals>
</device>