Explanation of automatic CE/valid bit wiring?

[jameshegarty]

When exactly are valid bits and CE bits implicitly added? Is there a reasonable way to have systolic deal with this automatically?

It looks like valid bits are automatically added whenever stateful elements are present. This is NOT how CE bits behave. CE is only added if explicitly declared. Consider making this consistent! Is there ever a reason to generate a pipeline in systolic without these signals? (meaning, in pipelines with stateful elements, always add these signals. In pipelines without, don't add them).