-
Notifications
You must be signed in to change notification settings - Fork 2
/
grammar.txt
1711 lines (1711 loc) · 86.9 KB
/
grammar.txt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
A.1 Source text
A.1.1 Library source text
library_text ::= { library_description }
library_description ::= library_declaration
| include_statement | config_declaration |;
library_declaration ::=
library library_identifier file_path_spec { , file_path_spec }
[ -incdir file_path_spec { , file_path_spec } ] ; include_statement ::= include file_path_spec ;
A.1.2 SystemVerilog source text
source_text ::= [ timeunits_declaration ] { description }
description ::= module_declaration
| udp_declaration
| interface_declaration
| program_declaration
1136
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
| package_declaration
| { attribute_instance } package_item | { attribute_instance } bind_directive | config_declaration
module_nonansi_header ::=
{ attribute_instance } module_keyword [ lifetime ] module_identifier
{ package_import_declaration } [ parameter_port_list ] list_of_ports ; module_ansi_header ::=
{ attribute_instance } module_keyword [ lifetime ] module_identifier
{ package_import_declaration }1 [ parameter_port_list ] [ list_of_port_declarations ] ;
module_declaration ::=
module_nonansi_header [ timeunits_declaration ] { module_item }
endmodule [ : module_identifier ]
| module_ansi_header [ timeunits_declaration ] { non_port_module_item }
endmodule [ : module_identifier ]
| { attribute_instance } module_keyword [ lifetime ] module_identifier ( .* ) ;
[ timeunits_declaration ] { module_item } endmodule [ : module_identifier ]
| extern module_nonansi_header
| extern module_ansi_header
module_keyword ::= module | macromodule
interface_declaration ::=
interface_nonansi_header [ timeunits_declaration ] { interface_item }
endinterface [ : interface_identifier ]
| interface_ansi_header [ timeunits_declaration ] { non_port_interface_item }
endinterface [ : interface_identifier ]
| { attribute_instance } interface interface_identifier ( .* ) ;
[ timeunits_declaration ] { interface_item } endinterface [ : interface_identifier ]
| extern interface_nonansi_header
| extern interface_ansi_header
interface_nonansi_header ::=
{ attribute_instance } interface [ lifetime ] interface_identifier
{ package_import_declaration } [ parameter_port_list ] list_of_ports ; interface_ansi_header ::=
{attribute_instance } interface [ lifetime ] interface_identifier
{ package_import_declaration }1 [ parameter_port_list ] [ list_of_port_declarations ] ;
program_declaration ::=
program_nonansi_header [ timeunits_declaration ] { program_item }
endprogram [ : program_identifier ]
| program_ansi_header [ timeunits_declaration ] { non_port_program_item }
endprogram [ : program_identifier ]
| { attribute_instance } program program_identifier ( .* ) ;
[ timeunits_declaration ] { program_item } endprogram [ : program_identifier ]
| extern program_nonansi_header
| extern program_ansi_header
program_nonansi_header ::=
{ attribute_instance } program [ lifetime ] program_identifier
{ package_import_declaration } [ parameter_port_list ] list_of_ports ; program_ansi_header ::=
{attribute_instance } program [ lifetime ] program_identifier 1137
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
{ package_import_declaration }1 [ parameter_port_list ] [ list_of_port_declarations ] ;
checker_declaration ::=
checker checker_identifier [ ( [ checker_port_list ] ) ] ;
{ { attribute_instance } checker_or_generate_item } endchecker [ : checker_identifier ]
class_declaration ::=
[ virtual ] class [ lifetime ] class_identifier [ parameter_port_list ]
[ extends class_type [ ( list_of_arguments ) ] ]
[ implements interface_class_type { , interface_class_type } ] ; { class_item }
endclass [ : class_identifier]
interface_class_type ::= ps_class_identifier [ parameter_value_assignment ]
interface_class_declaration ::=
interface class class_identifier [ parameter_port_list ]
[ extends interface_class_type { , interface_class_type } ] ;
{ interface_class_item } endclass [ : class_identifier]
interface_class_item ::= type_declaration
| { attribute_instance } interface_class_method
| local_parameter_declaration ;
| parameter_declaration7 ; |;
interface_class_method ::=
pure virtual method_prototype ;
package_declaration ::=
{ attribute_instance } package [ lifetime ] package_identifier ;
[ timeunits_declaration ] { { attribute_instance } package_item } endpackage [ : package_identifier ]
timeunits_declaration ::=
timeunit time_literal [ / time_literal ] ;
| timeprecision time_literal ;
| timeunit time_literal ; timeprecision time_literal ; | timeprecision time_literal ; timeunit time_literal ;
A.1.3 Module parameters and ports
parameter_port_list ::=
# (list_of_param_assignments{,parameter_port_declaration})
| # ( parameter_port_declaration { , parameter_port_declaration } ) | #( )
parameter_port_declaration ::= parameter_declaration
| local_parameter_declaration
| data_type list_of_param_assignments
| type list_of_type_assignments
list_of_ports ::= ( port { , port } ) list_of_port_declarations2 ::=
( [ { attribute_instance} ansi_port_declaration { , { attribute_instance} ansi_port_declaration } ] ) 1138
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
port_declaration ::=
{ attribute_instance } inout_declaration
| { attribute_instance } input_declaration
| { attribute_instance } output_declaration
| { attribute_instance } ref_declaration
| { attribute_instance } interface_port_declaration
port ::=
[ port_expression ]
| . port_identifier ( [ port_expression ] )
port_expression ::= port_reference
| { port_reference { , port_reference } } port_reference ::=
port_identifier constant_select
port_direction ::= input | output | inout | ref net_port_header ::= [ port_direction ] net_port_type variable_port_header ::= [ port_direction ] variable_port_type
interface_port_header ::=
interface_identifier [ . modport_identifier ]
| interface [ . modport_identifier ]
ansi_port_declaration ::=
[ net_port_header | interface_port_header ] port_identifier { unpacked_dimension }
[ = constant_expression ]
| [ variable_port_header ] port_identifier { variable_dimension } [ = constant_expression ]
| [ port_direction ] . port_identifier ( [ expression ] )
A.1.4 Module items
elaboration_system_task ::=
$fatal [ ( finish_number [, list_of_arguments ] ) ] ;
| $error [ ( [ list_of_arguments ] ) ] ;
| $warning [ ( [ list_of_arguments ] ) ] ; | $info [ ( [ list_of_arguments ] ) ] ;
finish_number ::= 0 | 1 | 2
module_common_item ::= module_or_generate_item_declaration
| interface_instantiation
| program_instantiation
| assertion_item
| bind_directive
| continuous_assign
| net_alias
| initial_construct
| final_construct
| always_construct
| loop_generate_construct
| conditional_generate_construct
| elaboration_system_task
module_item ::= port_declaration ;
1139
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
| non_port_module_item
module_or_generate_item ::=
{ attribute_instance } parameter_override
| { attribute_instance } gate_instantiation
| { attribute_instance } udp_instantiation
| { attribute_instance } module_instantiation
| { attribute_instance } module_common_item
module_or_generate_item_declaration ::= package_or_generate_item_declaration
| genvar_declaration
| clocking_declaration
| default clocking clocking_identifier ;
| default disable iff expression_or_dist ;
non_port_module_item ::= generate_region
| module_or_generate_item
| specify_block
| { attribute_instance } specparam_declaration
| program_declaration
| module_declaration
| interface_declaration
| timeunits_declaration3
parameter_override ::= defparam list_of_defparam_assignments ;
bind_directive4 ::=
bind bind_target_scope [: bind_target_instance_list] bind_instantiation ;
| bind bind_target_instance bind_instantiation ;
bind_target_scope ::= module_identifier
| interface_identifier
bind_target_instance ::= hierarchical_identifier constant_bit_select
bind_target_instance_list ::=
bind_target_instance { , bind_target_instance }
bind_instantiation ::= program_instantiation
| module_instantiation
| interface_instantiation
| checker_instantiation
A.1.5 Configuration source text
config_declaration ::=
config config_identifier ;
{ local_parameter_declaration ; } design_statement
{ config_rule_statement }
endconfig [ : config_identifier ]
design_statement ::= design { [ library_identifier . ] cell_identifier } ;
config_rule_statement ::= default_clause liblist_clause ;
1140
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
| inst_clause liblist_clause ; | inst_clause use_clause ;
| cell_clause liblist_clause ; | cell_clause use_clause ;
default_clause ::= default
inst_clause ::= instance inst_name
inst_name ::= topmodule_identifier { . instance_identifier } cell_clause::=cell [library_identifier. ]cell_identifier liblist_clause ::= liblist {library_identifier}
use_clause ::= use [ library_identifier . ] cell_identifier [ : config ]
| use named_parameter_assignment { , named_parameter_assignment } [ : config ] | use [ library_identifier . ] cell_identifier named_parameter_assignment
{ , named_parameter_assignment } [ : config ] A.1.6 Interface items
interface_or_generate_item ::=
{ attribute_instance } module_common_item
| { attribute_instance } extern_tf_declaration
extern_tf_declaration ::=
extern method_prototype ;
| extern forkjoin task_prototype ;
interface_item ::= port_declaration ;
| non_port_interface_item
non_port_interface_item ::= generate_region
| interface_or_generate_item
| program_declaration
| modport_declaration
| interface_declaration
| timeunits_declaration3 A.1.7 Program items
program_item ::= port_declaration ;
| non_port_program_item
non_port_program_item ::=
{ attribute_instance } continuous_assign
| { attribute_instance } module_or_generate_item_declaration
| { attribute_instance } initial_construct
| { attribute_instance } final_construct
| { attribute_instance } concurrent_assertion_item
| timeunits_declaration3
| program_generate_item
program_generate_item5 ::= loop_generate_construct
| conditional_generate_construct
1141
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
| generate_region
| elaboration_system_task
A.1.8 Checker items
checker_port_list ::=
checker_port_item {, checker_port_item}
checker_port_item ::=
{ attribute_instance } [ checker_port_direction ] property_formal_type formal_port_identifier
{variable_dimension} [ = property_actual_arg ] checker_port_direction ::=
input | output
checker_or_generate_item ::= checker_or_generate_item_declaration
| initial_construct
| always_construct
| final_construct
| assertion_item
| continuous_assign
| checker_generate_item
checker_or_generate_item_declaration ::= [ rand ] data_declaration
| function_declaration
| checker_declaration
| assertion_item_declaration
| covergroup_declaration
| genvar_declaration
| clocking_declaration
| default clocking clocking_identifier ;
| default disable iff expression_or_dist ; |;
checker_generate_item6 ::= loop_generate_construct
| conditional_generate_construct
| generate_region
| elaboration_system_task
A.1.9 Class items
class_item ::=
{ attribute_instance } class_property
| { attribute_instance } class_method
| { attribute_instance } class_constraint
| { attribute_instance } class_declaration
| { attribute_instance } covergroup_declaration
| local_parameter_declaration ;
| parameter_declaration7 ; |;
class_property ::=
{ property_qualifier } data_declaration
| const { class_item_qualifier } data_type const_identifier [ = constant_expression ] ; 1142
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
class_method ::=
{ method_qualifier } task_declaration
| { method_qualifier } function_declaration
| pure virtual { class_item_qualifier } method_prototype ;
| extern { method_qualifier } method_prototype ;
| { method_qualifier } class_constructor_declaration
| extern { method_qualifier } class_constructor_prototype
class_constructor_prototype ::=
function new [([tf_port_list])];
class_constraint ::= constraint_prototype
| constraint_declaration
class_item_qualifier8 ::= static
| protected | local
property_qualifier8 ::= random_qualifier
| class_item_qualifier
random_qualifier8 ::= rand
| randc
method_qualifier8 ::=
[ pure ] virtual
| class_item_qualifier
method_prototype ::= task_prototype
| function_prototype
class_constructor_declaration ::= function[class_scope]new[([tf_port_list]) ];
{ block_item_declaration }
[super . new[(list_of_arguments)];] { function_statement_or_null }
endfunction [ : new ] A.1.10 Constraints
constraint_declaration ::= [ static ] constraint constraint_identifier constraint_block
constraint_block ::= { { constraint_block_item } }
constraint_block_item ::=
solve solve_before_list before solve_before_list ;
| constraint_expression
solve_before_list ::= constraint_primary { , constraint_primary }
constraint_primary ::= [ implicit_class_handle . | class_scope ] hierarchical_identifier select
constraint_expression ::=
[ soft ] expression_or_dist ;
| uniqueness_constraint ;
| expression –> constraint_set
| if ( expression ) constraint_set [ else constraint_set ]
1143
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
| foreach ( ps_or_hierarchical_array_identifier [ loop_variables ] ) constraint_set | disable soft constraint_primary ;
uniqueness_constraint ::=
unique { open_range_list9 }
constraint_set ::= constraint_expression
| { { constraint_expression } } dist_list ::= dist_item { , dist_item } dist_item ::= value_range [ dist_weight ]
dist_weight ::=
:= expression
| :/ expression
constraint_prototype ::= [constraint_prototype_qualifier] [ static ] constraint constraint_identifier ;
constraint_prototype_qualifier ::= extern | pure
extern_constraint_declaration ::=
[ static ] constraint class_scope constraint_identifier constraint_block
identifier_list ::= identifier { , identifier } A.1.11 Package items
package_item ::= package_or_generate_item_declaration
| anonymous_program
| package_export_declaration
| timeunits_declaration3
package_or_generate_item_declaration ::= net_declaration
| data_declaration
| task_declaration
| function_declaration
| checker_declaration
| dpi_import_export
| extern_constraint_declaration
| class_declaration
| class_constructor_declaration
| local_parameter_declaration ;
| parameter_declaration ;
| covergroup_declaration
| assertion_item_declaration |;
anonymous_program::=program ;{anonymous_program_item}endprogram
anonymous_program_item ::= task_declaration
| function_declaration
| class_declaration
| covergroup_declaration
| class_constructor_declaration |;
1144
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
A.2 Declarations
A.2.1 Declaration types
A.2.1.1 Module parameter declarations
local_parameter_declaration ::=
localparam data_type_or_implicit list_of_param_assignments | localparam type list_of_type_assignments
parameter_declaration ::=
parameter data_type_or_implicit list_of_param_assignments
| parameter type list_of_type_assignments specparam_declaration ::=
specparam [ packed_dimension ] list_of_specparam_assignments ; A.2.1.2 Port declarations
inout_declaration ::=
inout net_port_type list_of_port_identifiers
input_declaration ::=
input net_port_type list_of_port_identifiers
| input variable_port_type list_of_variable_identifiers
output_declaration ::=
output net_port_type list_of_port_identifiers
| output variable_port_type list_of_variable_port_identifiers
interface_port_declaration ::=
interface_identifier list_of_interface_identifiers
| interface_identifier . modport_identifier list_of_interface_identifiers ref_declaration ::= ref variable_port_type list_of_variable_identifiers
A.2.1.3 Type declarations
data_declaration ::=
[ const ] [ var ] [ lifetime ] data_type_or_implicit list_of_variable_decl_assignments ;10
| type_declaration
| package_import_declaration11
| net_type_declaration
package_import_declaration ::=
import package_import_item { , package_import_item } ;
package_import_item ::= package_identifier :: identifier
| package_identifier :: *
package_export_declaration ::=
export *::* ;
| export package_import_item { , package_import_item } ;
genvar_declaration ::= genvar list_of_genvar_identifiers ;
net_declaration12 ::=
net_type [ drive_strength | charge_strength ] [ vectored | scalared ]
data_type_or_implicit [ delay3 ] list_of_net_decl_assignments ;
| net_type_identifier [ delay_control ]
list_of_net_decl_assignments ;
| interconnect implicit_data_type [ # delay_value ]
1145
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
net_identifier { unpacked_dimension }
[ , net_identifier { unpacked_dimension }] ;
type_declaration ::=
typedef data_type type_identifier { variable_dimension } ;
| typedef interface_instance_identifier constant_bit_select . type_identifier type_identifier ; | typedef [ enum | struct | union | class | interface class ] type_identifier ;
net_type_declaration ::=
nettype data_type net_type_identifier
[ with [ package_scope | class_scope ] tf_identifier ] ;
| nettype [ package_scope | class_scope ] net_type_identifier net_type_identifier ;
lifetime ::= static | automatic A.2.2 Declaration data types
A.2.2.1 Net and variable types
casting_type ::= simple_type | constant_primary | signing | string | const
data_type ::=
integer_vector_type [ signing ] { packed_dimension }
| integer_atom_type [ signing ]
| non_integer_type
| struct_union [ packed [ signing ] ] { struct_union_member { struct_union_member } }
{ packed_dimension }13
| enum [ enum_base_type ] { enum_name_declaration { , enum_name_declaration } }
{ packed_dimension }
| string
| chandle
| virtual [ interface ] interface_identifier [ parameter_value_assignment ] [ . modport_identifier ]
| [ class_scope | package_scope ] type_identifier { packed_dimension }
| class_type
| event
| ps_covergroup_identifier
| type_reference14
data_type_or_implicit ::= data_type
| implicit_data_type
implicit_data_type ::= [ signing ] { packed_dimension }
enum_base_type ::= integer_atom_type [ signing ]
| integer_vector_type [ signing ] [ packed_dimension ]
| type_identifier [ packed_dimension ]15 enum_name_declaration ::=
enum_identifier [ [ integral_number [ : integral_number ] ] ] [ = constant_expression ]
class_scope ::= class_type ::
class_type ::=
ps_class_identifier [ parameter_value_assignment ]
{ :: class_identifier [ parameter_value_assignment ] } integer_type ::= integer_vector_type | integer_atom_type integer_atom_type ::= byte | shortint | int | longint | integer | time integer_vector_type ::= bit | logic | reg
1146
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
non_integer_type ::= shortreal | real | realtime
net_type ::= supply0 | supply1 | tri | triand | trior | trireg| tri0 | tri1 | uwire| wire | wand | wor
net_port_type ::=
[ net_type ] data_type_or_implicit
| net_type_identifier
| interconnect implicit_data_type
variable_port_type ::= var_data_type
var_data_type ::= data_type | var data_type_or_implicit
signing ::= signed | unsigned
simple_type ::= integer_type | non_integer_type | ps_type_identifier | ps_parameter_identifier
struct_union_member16 ::=
{ attribute_instance } [random_qualifier] data_type_or_void list_of_variable_decl_assignments ;
data_type_or_void ::= data_type | void struct_union ::= struct | union [ tagged ] type_reference ::=
type ( expression17 ) | type ( data_type )
A.2.2.2 Strengths
drive_strength ::=
( strength0 , strength1 )
| ( strength1 , strength0 ) | ( strength0 , highz1 )
| ( strength1 , highz0 )
| ( highz0 , strength1 )
| ( highz1 , strength0 )
strength0 ::= supply0 | strong0 | pull0 | weak0
strength1 ::= supply1 | strong1 | pull1 | weak1 charge_strength::=( small )|( medium )|( large )
A.2.2.3 Delays
delay3::=#delay_value|# (mintypmax_expression[,mintypmax_expression[, mintypmax_expression ] ] )
delay2::=#delay_value|# (mintypmax_expression[,mintypmax_expression])
delay_value ::= unsigned_number
| real_number
| ps_identifier
| time_literal
| 1step
A.2.3 Declaration lists
list_of_defparam_assignments ::= defparam_assignment { , defparam_assignment }
list_of_genvar_identifiers ::= genvar_identifier { , genvar_identifier }
list_of_interface_identifiers ::= interface_identifier { unpacked_dimension } { , interface_identifier { unpacked_dimension } }
list_of_net_decl_assignments ::= net_decl_assignment { , net_decl_assignment } 1147
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
list_of_param_assignments ::= param_assignment { , param_assignment } list_of_port_identifiers ::= port_identifier { unpacked_dimension }
{ , port_identifier { unpacked_dimension } }
list_of_udp_port_identifiers ::= port_identifier { , port_identifier }
list_of_specparam_assignments ::= specparam_assignment { , specparam_assignment }
list_of_tf_variable_identifiers ::= port_identifier { variable_dimension } [ = expression ] { , port_identifier { variable_dimension } [ = expression ] }
list_of_type_assignments ::= type_assignment { , type_assignment }
list_of_variable_decl_assignments ::= variable_decl_assignment { , variable_decl_assignment }
list_of_variable_identifiers ::= variable_identifier { variable_dimension } { , variable_identifier { variable_dimension } }
list_of_variable_port_identifiers ::= port_identifier { variable_dimension } [ = constant_expression ] { , port_identifier { variable_dimension } [ = constant_expression ] }
A.2.4 Declaration assignments
defparam_assignment ::= hierarchical_parameter_identifier = constant_mintypmax_expression net_decl_assignment ::= net_identifier { unpacked_dimension } [ = expression ] param_assignment ::=
parameter_identifier { unpacked_dimension } [ = constant_param_expression ]18
specparam_assignment ::=
specparam_identifier = constant_mintypmax_expression
| pulse_control_specparam type_assignment ::=
type_identifier [ = data_type ]18
pulse_control_specparam ::=
PATHPULSE$ = ( reject_limit_value [ , error_limit_value ] )
| PATHPULSE$specify_input_terminal_descriptor$specify_output_terminal_descriptor = (reject_limit_value[,error_limit_value])
error_limit_value ::= limit_value reject_limit_value ::= limit_value
limit_value ::= constant_mintypmax_expression
variable_decl_assignment ::=
variable_identifier { variable_dimension } [ = expression ]
| dynamic_array_variable_identifier unsized_dimension { variable_dimension } [ = dynamic_array_new ]
| class_variable_identifier [ = class_new ]
class_new19 ::=
[ class_scope ] new [ ( list_of_arguments ) ]
| new expression
dynamic_array_new::=new [expression][(expression)]
A.2.5 Declaration ranges
unpacked_dimension ::= [ constant_range ]
| [ constant_expression ]
1148
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
packed_dimension20 ::= [ constant_range ] | unsized_dimension
associative_dimension ::= [ data_type ]
|[*]
variable_dimension ::= unsized_dimension
| unpacked_dimension
| associative_dimension
| queue_dimension
queue_dimension::=[ $[:constant_expression]] unsized_dimension::=[ ]
A.2.6 Function declarations
function_data_type_or_implicit ::= data_type_or_void
| implicit_data_type
function_declaration ::= function [ lifetime ] function_body_declaration
function_body_declaration ::= function_data_type_or_implicit
[ interface_identifier . | class_scope ] function_identifier ; { tf_item_declaration }
{ function_statement_or_null }
endfunction [ : function_identifier ]
| function_data_type_or_implicit
[ interface_identifier . | class_scope ] function_identifier ( [ tf_port_list ] ) ;
{ block_item_declaration }
{ function_statement_or_null } endfunction [ : function_identifier ]
function_prototype ::= function data_type_or_void function_identifier [ ( [ tf_port_list ] ) ]
dpi_import_export ::=
import dpi_spec_string [ dpi_function_import_property ] [ c_identifier = ] dpi_function_proto ;
| import dpi_spec_string [ dpi_task_import_property ] [ c_identifier = ] dpi_task_proto ; | export dpi_spec_string [ c_identifier = ] function function_identifier ;
| export dpi_spec_string [ c_identifier = ] task task_identifier ;
dpi_spec_string ::= "DPI-C" | "DPI" dpi_function_import_property ::= context | pure dpi_task_import_property ::= context
dpi_function_proto21,22 ::= function_prototype dpi_task_proto22 ::= task_prototype
A.2.7 Task declarations
task_declaration ::= task [ lifetime ] task_body_declaration task_body_declaration ::=
[ interface_identifier . | class_scope ] task_identifier ; 1149
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
{ tf_item_declaration }
{ statement_or_null } endtask [ : task_identifier ]
| [ interface_identifier . | class_scope ] task_identifier ( [ tf_port_list ] ) ; { block_item_declaration }
{ statement_or_null }
endtask [ : task_identifier ]
tf_item_declaration ::= block_item_declaration
| tf_port_declaration tf_port_list ::=
tf_port_item { , tf_port_item }
tf_port_item23 ::=
{ attribute_instance }
[ tf_port_direction ] [ var ] data_type_or_implicit
[ port_identifier { variable_dimension } [ = expression ] ]
tf_port_direction ::= port_direction | const ref tf_port_declaration ::=
{ attribute_instance } tf_port_direction [ var ] data_type_or_implicit list_of_tf_variable_identifiers ; task_prototype ::= task task_identifier [ ( [ tf_port_list ] ) ]
A.2.8 Block item declarations
block_item_declaration ::=
{ attribute_instance } data_declaration
| { attribute_instance } local_parameter_declaration ;
| { attribute_instance } parameter_declaration ;
| { attribute_instance } let_declaration
A.2.9 Interface declarations
modport_declaration ::= modport modport_item { , modport_item } ;
modport_item ::= modport_identifier ( modport_ports_declaration { , modport_ports_declaration } )
modport_ports_declaration ::=
{ attribute_instance } modport_simple_ports_declaration
| { attribute_instance } modport_tf_ports_declaration
| { attribute_instance } modport_clocking_declaration
modport_clocking_declaration ::= clocking clocking_identifier modport_simple_ports_declaration ::=
port_direction modport_simple_port { , modport_simple_port }
modport_simple_port ::= port_identifier
| . port_identifier ( [ expression ] ) modport_tf_ports_declaration ::=
import_export modport_tf_port { , modport_tf_port }
modport_tf_port ::= method_prototype
| tf_identifier
import_export ::= import | export
1150
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
A.2.10 Assertion declarations
concurrent_assertion_item ::=
[ block_identifier : ] concurrent_assertion_statement
| checker_instantiation
concurrent_assertion_statement ::= assert_property_statement
| assume_property_statement
| cover_property_statement
| cover_sequence_statement
| restrict_property_statement
assert_property_statement::=
assert property ( property_spec ) action_block
assume_property_statement::=
assume property ( property_spec ) action_block
cover_property_statement::=
cover property ( property_spec ) statement_or_null
expect_property_statement ::=
expect (property_spec)action_block
cover_sequence_statement::=
cover sequence ([clocking_event][disable iff (expression_or_dist)]
sequence_expr ) statement_or_null restrict_property_statement::=
restrict property ( property_spec ) ; property_instance ::=
ps_or_hierarchical_property_identifier [ ( [ property_list_of_arguments ] ) ]
property_list_of_arguments ::=
[property_actual_arg] { , [property_actual_arg] } { , . identifier ( [property_actual_arg] ) }
| . identifier ( [property_actual_arg] ) { , . identifier ( [property_actual_arg] ) }
property_actual_arg ::= property_expr
| sequence_actual_arg
assertion_item_declaration ::= property_declaration
| sequence_declaration
| let_declaration
property_declaration ::=
property property_identifier [ ( [ property_port_list ] ) ] ;
{ assertion_variable_declaration } property_spec [ ; ]
endproperty [ : property_identifier ] property_port_list ::=
property_port_item {, property_port_item}
property_port_item ::=
{ attribute_instance } [ local [ property_lvar_port_direction ] ] property_formal_type
formal_port_identifier {variable_dimension} [ = property_actual_arg ]
property_lvar_port_direction ::= input
property_formal_type ::= sequence_formal_type
| property
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
1151
Copyright © 2018 IEEE. All rights reserved.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
property_spec ::=
[clocking_event][disable iff(expression_or_dist)]property_expr
property_expr ::= sequence_expr
| strong ( sequence_expr ) | weak ( sequence_expr )
| ( property_expr )
| not property_expr
| property_expr or property_expr
| property_expr and property_expr
| sequence_expr |-> property_expr
| sequence_expr |=> property_expr
| if ( expression_or_dist ) property_expr [ else property_expr ]
| case ( expression_or_dist ) property_case_item { property_case_item } endcase | sequence_expr #-# property_expr
| sequence_expr #=# property_expr
| nexttime property_expr
| nexttime [ constant _expression ] property_expr
| s_nexttime property_expr
| s_nexttime [ constant_expression ] property_expr
| always property_expr
| always [ cycle_delay_const_range_expression ] property_expr
| s_always [ constant_range] property_expr
| s_eventually property_expr
| eventually [ constant_range ] property_expr
| s_eventually [ cycle_delay_const_range_expression ] property_expr
| property_expr until property_expr
| property_expr s_until property_expr
| property_expr until_with property_expr
| property_expr s_until_with property_expr
| property_expr implies property_expr
| property_expr iff property_expr
| accept_on ( expression_or_dist ) property_expr
| reject_on ( expression_or_dist ) property_expr
| sync_accept_on ( expression_or_dist ) property_expr
| sync_reject_on ( expression_or_dist ) property_expr
| property_instance
| clocking_event property_expr
property_case_item ::=
expression_or_dist { , expression_or_dist } : property_expr ;
| default [ : ] property_expr ;
sequence_declaration ::=
sequence sequence_identifier [ ( [ sequence_port_list ] ) ] ;
{ assertion_variable_declaration }
sequence_expr [ ; ]
endsequence [ : sequence_identifier ]
sequence_port_list ::=
sequence_port_item {, sequence_port_item}
sequence_port_item ::=
{ attribute_instance } [ local [ sequence_lvar_port_direction ] ] sequence_formal_type
formal_port_identifier {variable_dimension} [ = sequence_actual_arg ] sequence_lvar_port_direction ::= input | inout | output
1152
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
sequence_formal_type ::= data_type_or_implicit
| sequence | untyped
sequence_expr ::=
cycle_delay_range sequence_expr { cycle_delay_range sequence_expr }
| sequence_expr cycle_delay_range sequence_expr { cycle_delay_range sequence_expr }
| expression_or_dist [ boolean_abbrev ]
| sequence_instance [ sequence_abbrev ]
| ( sequence_expr {, sequence_match_item } ) [ sequence_abbrev ]
| sequence_expr and sequence_expr
| sequence_expr intersect sequence_expr
| sequence_expr or sequence_expr
| first_match ( sequence_expr {, sequence_match_item} )
| expression_or_dist throughout sequence_expr
| sequence_expr within sequence_expr | clocking_event sequence_expr
cycle_delay_range ::=
## constant_primary
| ## [ cycle_delay_const_range_expression ] | ##[*]
| ##[+]
sequence_method_call ::= sequence_instance . method_identifier
sequence_match_item ::= operator_assignment
| inc_or_dec_expression
| subroutine_call
sequence_instance ::=
ps_or_hierarchical_sequence_identifier [ ( [ sequence_list_of_arguments ] ) ]
sequence_list_of_arguments ::=
[sequence_actual_arg] { , [sequence_actual_arg] } { , . identifier ( [sequence_actual_arg] ) }
| . identifier ( [sequence_actual_arg] ) { , . identifier ( [sequence_actual_arg] ) }
sequence_actual_arg ::= event_expression
| sequence_expr
boolean_abbrev ::= consecutive_repetition
| non_consecutive_repetition
| goto_repetition
sequence_abbrev ::= consecutive_repetition
consecutive_repetition ::=
[* const_or_range_expression ]
| [*] | [+]
non_consecutive_repetition ::= [= const_or_range_expression ]
goto_repetition ::= [-> const_or_range_expression ]
const_or_range_expression ::= constant_expression
| cycle_delay_const_range_expression
1153
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
cycle_delay_const_range_expression ::= constant_expression : constant_expression
| constant_expression : $
expression_or_dist ::= expression [ dist { dist_list } ]
assertion_variable_declaration ::=
var_data_type list_of_variable_decl_assignments ;
A.2.11 Covergroup declarations
covergroup_declaration ::=
covergroup covergroup_identifier [ ( [ tf_port_list ] ) ] [ coverage_event ] ;
{ coverage_spec_or_option } endgroup [ : covergroup_identifier ]
coverage_spec_or_option ::= {attribute_instance} coverage_spec
| {attribute_instance} coverage_option ;
coverage_option ::= option.member_identifier = expression
| type_option.member_identifier = constant_expression
coverage_spec ::= cover_point
| cover_cross
coverage_event ::= clocking_event
| with function sample ( [ tf_port_list ] ) | @@( block_event_expression )
block_event_expression ::=
block_event_expression or block_event_expression
| begin hierarchical_btf_identifier | end hierarchical_btf_identifier
hierarchical_btf_identifier ::= hierarchical_tf_identifier
| hierarchical_block_identifier
| [ hierarchical_identifier. | class_scope ] method_identifier
cover_point ::=
[ [ data_type_or_implicit ] cover_point_identifier : ] coverpoint expression [ iff ( expression ) ]
bins_or_empty
bins_or_empty ::=
{ {attribute_instance} { bins_or_options ; } }
|;
bins_or_options ::= coverage_option
| [ wildcard ] bins_keyword bin_identifier [ [ [ covergroup_expression ] ] ] = { covergroup_range_list } [ with ( with_covergroup_expression ) ]
[ iff ( expression ) ]
| [ wildcard ] bins_keyword bin_identifier [ [ [ covergroup_expression ] ] ] = cover_point_identifier with ( with_covergroup_expression ) [ iff ( expression ) ]
| [ wildcard ] bins_keyword bin_identifier [ [ [ covergroup_expression ] ] ] = set_covergroup_expression [ iff ( expression ) ]
| [ wildcard] bins_keyword bin_identifier [ [ ] ] = trans_list [ iff ( expression ) ] 1154
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
| bins_keyword bin_identifier [ [ [ covergroup_expression ] ] ] = default [ iff ( expression ) ] | bins_keyword bin_identifier = default sequence [ iff ( expression ) ]
bins_keyword::= bins | illegal_bins | ignore_bins trans_list ::= ( trans_set ) { , ( trans_set ) }
trans_set ::= trans_range_list { => trans_range_list }
trans_range_list ::= trans_item
| trans_item [* repeat_range ]
| trans_item [–> repeat_range ]
| trans_item [= repeat_range ]
trans_item ::= covergroup_range_list
repeat_range ::= covergroup_expression
| covergroup_expression : covergroup_expression cover_cross ::=
[cross_identifier: ]crosslist_of_cross_items[iff(expression)]cross_body
list_of_cross_items ::= cross_item , cross_item { , cross_item }
cross_item ::= cover_point_identifier
| variable_identifier
cross_body ::=
{ { cross_body_item ; } }
|;
cross_body_item ::= function_declaraton
| bins_selection_or_option ;
bins_selection_or_option ::=
{ attribute_instance } coverage_option
| { attribute_instance } bins_selection
bins_selection ::= bins_keyword bin_identifier = select_expression [ iff ( expression ) ]
select_expression24 ::= select_condition
| ! select_condition
| select_expression && select_expression
| select_expression || select_expression
| ( select_expression )
| select_expression with ( with_covergroup_expression ) [ matches integer_covergroup_expression ]
| cross_identifier
| cross_set_expression [ matches integer_covergroup_expression ]
select_condition::=binsof (bins_expression)[intersect{covergroup_range_list}]
bins_expression ::= variable_identifier
| cover_point_identifier [ . bin_identifier ]
covergroup_range_list ::= covergroup_value_range { , covergroup_value_range }
covergroup_value_range ::= covergroup_expression
| [ covergroup_expression : covergroup_expression ]25 with_covergroup_expression ::= covergroup_expression26
1155
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
set_covergroup_expression ::= covergroup_expression27 integer_covergroup_expression ::= covergroup_expression cross_set_expression ::= covergroup_expression
covergroup_expression ::= expression28 A.2.12 Let declarations
let_declaration ::=
let let_identifier [ ( [ let_port_list ] ) ] = expression ;
let_identifier ::= identifier
let_port_list ::=
let_port_item {, let_port_item}
let_port_item ::=
{ attribute_instance } let_formal_type formal_port_identifier { variable_dimension } [ = expression ]
let_formal_type ::= data_type_or_implicit
| untyped let_expression ::=
[ package_scope ] let_identifier [ ( [ let_list_of_arguments ] ) ]
let_list_of_arguments ::=
[ let_actual_arg ] {, [ let_actual_arg ] } {, . identifier ( [ let_actual_arg ] ) }
| . identifier ( [ let_actual_arg ] ) { , . identifier ( [ let_actual_arg ] ) } let_actual_arg ::=
expression
A.3 Primitive instances
A.3.1 Primitive instantiation and instances
gate_instantiation ::=
cmos_switchtype [delay3] cmos_switch_instance { , cmos_switch_instance } ;
| enable_gatetype [drive_strength] [delay3] enable_gate_instance { , enable_gate_instance } ;
| mos_switchtype [delay3] mos_switch_instance { , mos_switch_instance } ;
| n_input_gatetype [drive_strength] [delay2] n_input_gate_instance { , n_input_gate_instance } ;
| n_output_gatetype [drive_strength] [delay2] n_output_gate_instance
{ , n_output_gate_instance } ;
| pass_en_switchtype [delay2] pass_enable_switch_instance { , pass_enable_switch_instance } ;
| pass_switchtype pass_switch_instance { , pass_switch_instance } ;
| pulldown [pulldown_strength] pull_gate_instance { , pull_gate_instance } ;
| pullup [pullup_strength] pull_gate_instance { , pull_gate_instance } ;
cmos_switch_instance ::= [ name_of_instance ] ( output_terminal , input_terminal , ncontrol_terminal , pcontrol_terminal )
enable_gate_instance ::= [ name_of_instance ] ( output_terminal , input_terminal , enable_terminal ) mos_switch_instance ::= [ name_of_instance ] ( output_terminal , input_terminal , enable_terminal ) n_input_gate_instance ::= [ name_of_instance ] ( output_terminal , input_terminal { , input_terminal } ) n_output_gate_instance ::= [ name_of_instance ] ( output_terminal { , output_terminal } ,
1156
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
input_terminal )
pass_switch_instance ::= [ name_of_instance ] ( inout_terminal , inout_terminal )
pass_enable_switch_instance ::= [ name_of_instance ] ( inout_terminal , inout_terminal , enable_terminal )
pull_gate_instance ::= [ name_of_instance ] ( output_terminal ) A.3.2 Primitive strengths
pulldown_strength ::=
( strength0 , strength1 )
| ( strength1 , strength0 ) | ( strength0 )
pullup_strength ::=
( strength0 , strength1 )
| ( strength1 , strength0 ) | ( strength1 )
A.3.3 Primitive terminals
enable_terminal ::= expression inout_terminal ::= net_lvalue input_terminal ::= expression ncontrol_terminal ::= expression output_terminal ::= net_lvalue pcontrol_terminal ::= expression
A.3.4 Primitive gate and switch types
cmos_switchtype ::= cmos | rcmos
enable_gatetype ::= bufif0 | bufif1 | notif0 | notif1 mos_switchtype ::= nmos | pmos | rnmos | rpmos
n_input_gatetype ::= and | nand | or | nor | xor | xnor n_output_gatetype ::= buf | not
pass_en_switchtype ::= tranif0 | tranif1 | rtranif1 | rtranif0 pass_switchtype ::= tran | rtran
A.4 Instantiations
A.4.1 Instantiation
A.4.1.1 Module instantiation
module_instantiation ::=
module_identifier [ parameter_value_assignment ] hierarchical_instance { , hierarchical_instance } ;
parameter_value_assignment::=# ([list_of_parameter_assignments]) list_of_parameter_assignments ::=
ordered_parameter_assignment { , ordered_parameter_assignment } 1157
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
| named_parameter_assignment { , named_parameter_assignment } ordered_parameter_assignment ::= param_expression named_parameter_assignment ::= . parameter_identifier ( [ param_expression ] ) hierarchical_instance ::= name_of_instance ( [ list_of_port_connections ] ) name_of_instance ::= instance_identifier { unpacked_dimension }
list_of_port_connections29 ::=
ordered_port_connection { , ordered_port_connection }
| named_port_connection { , named_port_connection }
ordered_port_connection ::= { attribute_instance } [ expression ]
named_port_connection ::=
{ attribute_instance } . port_identifier [ ( [ expression ] ) ]
| { attribute_instance } .* A.4.1.2 Interface instantiation
interface_instantiation ::=
interface_identifier [ parameter_value_assignment ] hierarchical_instance { , hierarchical_instance } ;
A.4.1.3 Program instantiation
program_instantiation ::=
program_identifier [ parameter_value_assignment ] hierarchical_instance { , hierarchical_instance } ;
A.4.1.4 Checker instantiation
checker_instantiation ::=
ps_checker_identifier name_of_instance ( [list_of_checker_port_connections] ) ;
list_of_checker_port_connections29 ::=
ordered_checker_port_connection { , ordered_checker_port_connection }
| named_checker_port_connection { , named_checker_port_connection }
ordered_checker_port_connection ::= { attribute_instance } [ property_actual_arg ]
named_checker_port_connection ::=
{ attribute_instance } . formal_port_identifier [ ( [ property_actual_arg ] ) ]
| { attribute_instance } .*
A.4.2 Generated instantiation
generate_region ::=
generate { generate_item } endgenerate
loop_generate_construct ::=
for ( genvar_initialization ; genvar_expression ; genvar_iteration )
generate_block genvar_initialization ::=
[ genvar ] genvar_identifier = constant_expression
genvar_iteration ::=
genvar_identifier assignment_operator genvar_expression
| inc_or_dec_operator genvar_identifier
| genvar_identifier inc_or_dec_operator
conditional_generate_construct ::= if_generate_construct
| case_generate_construct
1158
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
if_generate_construct ::=
if ( constant_expression ) generate_block [ else generate_block ] case_generate_construct ::=
case ( constant_expression ) case_generate_item { case_generate_item } endcase
case_generate_item ::=
constant_expression { , constant_expression } : generate_block
| default [ : ] generate_block
generate_block ::= generate_item
| [ generate_block_identifier : ] begin [ : generate_block_identifier ] { generate_item }
end [ : generate_block_identifier ]
generate_item30 ::= module_or_generate_item
| interface_or_generate_item
| checker_or_generate_item
A.5 UDP declaration and instantiation A.5.1 UDP declaration
udp_nonansi_declaration ::= {attribute_instance}primitiveudp_identifier(udp_port_list) ;
udp_ansi_declaration ::= {attribute_instance}primitiveudp_identifier(udp_declaration_port_list) ;
udp_declaration ::=
udp_nonansi_declaration udp_port_declaration { udp_port_declaration }
udp_body
endprimitive [ : udp_identifier ]
| udp_ansi_declaration udp_body
endprimitive [ : udp_identifier ]
| extern udp_nonansi_declaration
| extern udp_ansi_declaration
| { attribute_instance } primitive udp_identifier ( .* ) ;
{ udp_port_declaration }
udp_body
endprimitive [ : udp_identifier ]
A.5.2 UDP ports
udp_port_list ::= output_port_identifier , input_port_identifier { , input_port_identifier }
udp_declaration_port_list ::= udp_output_declaration , udp_input_declaration { , udp_input_declaration }
udp_port_declaration ::= udp_output_declaration ;
| udp_input_declaration ;
| udp_reg_declaration ;
udp_output_declaration ::=
{ attribute_instance } output port_identifier
1159
Copyright © 2018 IEEE. All rights reserved.
Authorized licensed use limited to: NOAA Boulder Labs Library. Downloaded on September 18,2018 at 23:08:29 UTC from IEEE Xplore. Restrictions apply.
IEEE Std 1800-2017
IEEE Standard for SystemVerilog—Unified Hardware Design, Specification, and Verification Language
| { attribute_instance } output reg port_identifier [ = constant_expression ] udp_input_declaration ::= { attribute_instance } input list_of_udp_port_identifiers udp_reg_declaration ::= { attribute_instance } reg variable_identifier
A.5.3 UDP body
udp_body ::= combinational_body | sequential_body
combinational_body ::= table combinational_entry { combinational_entry } endtable combinational_entry ::= level_input_list : output_symbol ;
sequential_body ::= [ udp_initial_statement ] table sequential_entry { sequential_entry } endtable udp_initial_statement ::= initial output_port_identifier = init_val ;
init_val ::= 1'b0 | 1'b1 | 1'bx | 1'bX | 1'B0 | 1'B1 | 1'Bx | 1'BX | 1 | 0
sequential_entry ::= seq_input_list : current_state : next_state ;
seq_input_list ::= level_input_list | edge_input_list
level_input_list ::= level_symbol { level_symbol }
edge_input_list ::= { level_symbol } edge_indicator { level_symbol }
edge_indicator ::= ( level_symbol level_symbol ) | edge_symbol
current_state ::= level_symbol
next_state ::= output_symbol | -
output_symbol ::= 0 | 1 | x | X
level_symbol ::= 0 | 1 | x | X | ? | b | B
edge_symbol ::= r | R | f | F | p | P | n | N | *
A.5.4 UDP instantiation
udp_instantiation ::= udp_identifier [ drive_strength ] [ delay2 ] udp_instance { , udp_instance } ; udp_instance ::= [ name_of_instance ] ( output_terminal , input_terminal { , input_terminal } )
A.6 Behavioral statements
A.6.1 Continuous assignment and net alias statements
continuous_assign ::=
assign [ drive_strength ] [ delay3 ] list_of_net_assignments ;
| assign [ delay_control ] list_of_variable_assignments ; list_of_net_assignments ::= net_assignment { , net_assignment } list_of_variable_assignments ::= variable_assignment { , variable_assignment } net_alias ::= alias net_lvalue = net_lvalue { = net_lvalue } ;