frontend.dts

/dts-v1/;

/ {
	#size-cells = <0x2>;
	#address-cells = <0x2>;
	interrupt-parent = <&gic>;

	cpus {
		#size-cells = <0x0>;
		#address-cells = <0x1>;

		cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			enable-method = "psci";
			reg = <0x0>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};
	
	memory@30000000 {
		device_type = "memory";
		reg = <0x0 0x30000000 0x0 0x40000000
			   0x0 0x20000000 0x0 0x01000000>;
	};
	
	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;

		reserved1: buffer@20000000 {
		    compatible = "restricted-dma-pool";
		    reg = <0x0 0x20000000 0x0 0x1000000>;
		};
    };

    gic: intc@8000000 {
		interrupts = <0x01 0x09 0x04>;
		reg = <0x00 0x8000000 0x00 0x10000 0x00 0x80a0000 0x00 0xf60000>;
		#redistributor-regions = <0x01>;
		compatible = "arm,gic-v3";
		ranges;
		#size-cells = <0x02>;
		#address-cells = <0x02>;
		interrupt-controller;
		#interrupt-cells = <0x03>;
	};

	timer {
		interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>;
		always-on;
		compatible = "arm,armv8-timer", "arm,armv7-timer";
	};
	
	virtio@a003e00 {
		dma-coherent;
		interrupts = <0x0 0x2f 0x1>;
		reg = <0x0 0xa003e00 0x0 0x200>;
		compatible = "virtio,mmio";
		memory-region = <&reserved1>;
	};

	pl011@9002000 {
		clock-names = "uartclk\0apb_pclk";
		clocks = <0x8000 0x8000>;
		interrupts = <0x00 0x0B 0x04>;
		reg = <0x00 0x9002000 0x00 0x1000>;
		compatible = "arm,pl011\0arm,primecell";
	};
    
    aliases {
		serial0 = "/pl011@9002000";
	};
	
	apb-pclk {
		phandle = <0x8000>;
		clock-output-names = "clk24mhz";
		clock-frequency = <0x16e3600>;
		#clock-cells = <0x00>;
		compatible = "fixed-clock";
	};
	
	chosen {
        bootargs = "earlycon console=ttyAMA0 ip=192.168.43.15 clk_ignore_unused init=/sbin/init";
        stdout-path = "/pl011@9002000";
	};

};