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CalculateTa.vhf
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CalculateTa.vhf
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : sch2hdl
-- / / Filename : CalculateTa.vhf
-- /___/ /\ Timestamp : 06/19/2023 15:05:23
-- \ \ / \
-- \___\/\___\
--
--Command: sch2hdl -sympath /home/user/workspace/melexis_mlx90641/ipcore_dir -intstyle ise -family virtex4 -flat -suppress -vhdl /home/user/workspace/melexis_mlx90641/CalculateTa.vhf -w /home/user/workspace/melexis_mlx90641/CalculateTa.sch
--Design Name: CalculateTa
--Device: virtex4
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesized and simulated, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity ExtractAlphaPTATParameter_MUSER_CalculateTa is
port ( i_clock : in std_logic;
i_ee0x2410 : in std_logic_vector (15 downto 0);
i_reset : in std_logic;
o_alphaptat : out std_logic_vector (31 downto 0));
end ExtractAlphaPTATParameter_MUSER_CalculateTa;
architecture BEHAVIORAL of ExtractAlphaPTATParameter_MUSER_CalculateTa is
attribute BOX_TYPE : string ;
attribute DOA_REG : string ;
attribute DOB_REG : string ;
attribute INIT_00 : string ;
attribute INIT_01 : string ;
attribute INIT_02 : string ;
attribute INIT_03 : string ;
attribute INIT_04 : string ;
attribute INIT_05 : string ;
attribute INIT_06 : string ;
attribute INIT_07 : string ;
attribute INIT_08 : string ;
attribute INIT_09 : string ;
attribute INIT_0A : string ;
attribute INIT_0B : string ;
attribute INIT_0C : string ;
attribute INIT_0D : string ;
attribute INIT_0E : string ;
attribute INIT_0F : string ;
attribute INIT_10 : string ;
attribute INIT_11 : string ;
attribute INIT_12 : string ;
attribute INIT_13 : string ;
attribute INIT_14 : string ;
attribute INIT_15 : string ;
attribute INIT_16 : string ;
attribute INIT_17 : string ;
attribute INIT_18 : string ;
attribute INIT_19 : string ;
attribute INIT_1A : string ;
attribute INIT_1B : string ;
attribute INIT_1C : string ;
attribute INIT_1D : string ;
attribute INIT_1E : string ;
attribute INIT_1F : string ;
attribute INIT_20 : string ;
attribute INIT_21 : string ;
attribute INIT_22 : string ;
attribute INIT_23 : string ;
attribute INIT_24 : string ;
attribute INIT_25 : string ;
attribute INIT_26 : string ;
attribute INIT_27 : string ;
attribute INIT_28 : string ;
attribute INIT_29 : string ;
attribute INIT_2A : string ;
attribute INIT_2B : string ;
attribute INIT_2C : string ;
attribute INIT_2D : string ;
attribute INIT_2E : string ;
attribute INIT_2F : string ;
attribute INIT_30 : string ;
attribute INIT_31 : string ;
attribute INIT_32 : string ;
attribute INIT_33 : string ;
attribute INIT_34 : string ;
attribute INIT_35 : string ;
attribute INIT_36 : string ;
attribute INIT_37 : string ;
attribute INIT_38 : string ;
attribute INIT_39 : string ;
attribute INIT_3A : string ;
attribute INIT_3B : string ;
attribute INIT_3C : string ;
attribute INIT_3D : string ;
attribute INIT_3E : string ;
attribute INIT_3F : string ;
attribute INIT_A : string ;
attribute INIT_B : string ;
attribute INITP_00 : string ;
attribute INITP_01 : string ;
attribute INITP_02 : string ;
attribute INITP_03 : string ;
attribute INITP_04 : string ;
attribute INITP_05 : string ;
attribute INITP_06 : string ;
attribute INITP_07 : string ;
attribute INIT_FILE : string ;
attribute INVERT_CLK_DOA_REG : string ;
attribute INVERT_CLK_DOB_REG : string ;
attribute RAM_EXTENSION_A : string ;
attribute RAM_EXTENSION_B : string ;
attribute READ_WIDTH_A : string ;
attribute READ_WIDTH_B : string ;
attribute SRVAL_A : string ;
attribute SRVAL_B : string ;
attribute WRITE_MODE_A : string ;
attribute WRITE_MODE_B : string ;
attribute WRITE_WIDTH_A : string ;
attribute WRITE_WIDTH_B : string ;
attribute SIM_COLLISION_CHECK : string ;
signal XLXN_1 : std_logic_vector (14 downto 0);
signal XLXN_10 : std_logic;
signal ROM_ALPHAPTAT_ADDRB_openSignal : std_logic_vector (14 downto 0);
signal ROM_ALPHAPTAT_CASCADEINA_openSignal : std_logic;
signal ROM_ALPHAPTAT_CASCADEINB_openSignal : std_logic;
signal ROM_ALPHAPTAT_CLKB_openSignal : std_logic;
signal ROM_ALPHAPTAT_DIA_openSignal : std_logic_vector (31 downto 0);
signal ROM_ALPHAPTAT_DIB_openSignal : std_logic_vector (31 downto 0);
signal ROM_ALPHAPTAT_DIPA_openSignal : std_logic_vector (3 downto 0);
signal ROM_ALPHAPTAT_DIPB_openSignal : std_logic_vector (3 downto 0);
signal ROM_ALPHAPTAT_ENB_openSignal : std_logic;
signal ROM_ALPHAPTAT_REGCEA_openSignal : std_logic;
signal ROM_ALPHAPTAT_REGCEB_openSignal : std_logic;
signal ROM_ALPHAPTAT_SSRB_openSignal : std_logic;
signal ROM_ALPHAPTAT_WEA_openSignal : std_logic_vector (3 downto 0);
signal ROM_ALPHAPTAT_WEB_openSignal : std_logic_vector (3 downto 0);
component BUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUF : component is "BLACK_BOX";
component RAMB16
-- synopsys translate_off
generic( DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_00 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := x"000000000";
INIT_B : bit_vector := x"000000000";
INITP_00 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_FILE : string := "NONE";
INVERT_CLK_DOA_REG : boolean := FALSE;
INVERT_CLK_DOB_REG : boolean := FALSE;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SRVAL_A : bit_vector := x"000000000";
SRVAL_B : bit_vector := x"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL");
-- synopsys translate_on
port ( ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_logic;
CASCADEINB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
REGCEB : in std_logic;
ENB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0);
CASCADEOUTA : out std_logic;
CASCADEOUTB : out std_logic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0));
end component;
attribute DOA_REG of RAMB16 : component is "0";
attribute DOB_REG of RAMB16 : component is "0";
attribute INIT_00 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_20 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_21 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_22 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_23 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_24 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_25 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_26 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_27 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_28 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_29 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_2F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_30 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_31 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_32 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_33 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_34 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_35 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_36 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_37 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_38 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_39 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_3F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_A of RAMB16 : component is "000000000";
attribute INIT_B of RAMB16 : component is "000000000";
attribute INITP_00 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_01 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_02 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_03 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_04 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_05 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_06 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INITP_07 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_FILE of RAMB16 : component is "NONE";
attribute INVERT_CLK_DOA_REG of RAMB16 : component is "FALSE";
attribute INVERT_CLK_DOB_REG of RAMB16 : component is "FALSE";
attribute RAM_EXTENSION_A of RAMB16 : component is "NONE";
attribute RAM_EXTENSION_B of RAMB16 : component is "NONE";
attribute READ_WIDTH_A of RAMB16 : component is "0";
attribute READ_WIDTH_B of RAMB16 : component is "0";
attribute SRVAL_A of RAMB16 : component is "000000000";
attribute SRVAL_B of RAMB16 : component is "000000000";
attribute WRITE_MODE_A of RAMB16 : component is "WRITE_FIRST";
attribute WRITE_MODE_B of RAMB16 : component is "WRITE_FIRST";
attribute WRITE_WIDTH_A of RAMB16 : component is "0";
attribute WRITE_WIDTH_B of RAMB16 : component is "0";
attribute SIM_COLLISION_CHECK of RAMB16 : component is "ALL";
attribute BOX_TYPE of RAMB16 : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
attribute INIT_00 of ROM_ALPHAPTAT : label is
"411c0000411800004114000041100000410c0000410800004104000041000000";
attribute INIT_01 of ROM_ALPHAPTAT : label is
"413c0000413800004134000041300000412c0000412800004124000041200000";
attribute WRITE_WIDTH_B of ROM_ALPHAPTAT : label is "36";
attribute WRITE_WIDTH_A of ROM_ALPHAPTAT : label is "36";
attribute WRITE_MODE_B of ROM_ALPHAPTAT : label is "READ_FIRST";
attribute WRITE_MODE_A of ROM_ALPHAPTAT : label is "READ_FIRST";
attribute READ_WIDTH_B of ROM_ALPHAPTAT : label is "36";
attribute READ_WIDTH_A of ROM_ALPHAPTAT : label is "36";
begin
BUF_0 : BUF
port map (I=>i_ee0x2410(12),
O=>XLXN_1(5));
BUF_1 : BUF
port map (I=>i_ee0x2410(13),
O=>XLXN_1(6));
BUF_2 : BUF
port map (I=>i_ee0x2410(14),
O=>XLXN_1(7));
BUF_3 : BUF
port map (I=>i_ee0x2410(15),
O=>XLXN_1(8));
ROM_ALPHAPTAT : RAMB16
-- synopsys translate_off
generic map( INIT_00 =>
x"411c0000411800004114000041100000410c0000410800004104000041000000",
INIT_01 =>
x"413c0000413800004134000041300000412c0000412800004124000041200000",
WRITE_WIDTH_B => 36,
WRITE_WIDTH_A => 36,
WRITE_MODE_B => "READ_FIRST",
WRITE_MODE_A => "READ_FIRST",
READ_WIDTH_B => 36,
READ_WIDTH_A => 36)
-- synopsys translate_on
port map (ADDRA(14 downto 0)=>XLXN_1(14 downto 0),
ADDRB(14 downto 0)=>ROM_ALPHAPTAT_ADDRB_openSignal(14 downto 0),
CASCADEINA=>ROM_ALPHAPTAT_CASCADEINA_openSignal,
CASCADEINB=>ROM_ALPHAPTAT_CASCADEINB_openSignal,
CLKA=>i_clock,
CLKB=>ROM_ALPHAPTAT_CLKB_openSignal,
DIA(31 downto 0)=>ROM_ALPHAPTAT_DIA_openSignal(31 downto 0),
DIB(31 downto 0)=>ROM_ALPHAPTAT_DIB_openSignal(31 downto 0),
DIPA(3 downto 0)=>ROM_ALPHAPTAT_DIPA_openSignal(3 downto 0),
DIPB(3 downto 0)=>ROM_ALPHAPTAT_DIPB_openSignal(3 downto 0),
ENA=>XLXN_10,
ENB=>ROM_ALPHAPTAT_ENB_openSignal,
REGCEA=>ROM_ALPHAPTAT_REGCEA_openSignal,
REGCEB=>ROM_ALPHAPTAT_REGCEB_openSignal,
SSRA=>i_reset,
SSRB=>ROM_ALPHAPTAT_SSRB_openSignal,
WEA(3 downto 0)=>ROM_ALPHAPTAT_WEA_openSignal(3 downto 0),
WEB(3 downto 0)=>ROM_ALPHAPTAT_WEB_openSignal(3 downto 0),
CASCADEOUTA=>open,
CASCADEOUTB=>open,
DOA(31 downto 0)=>o_alphaptat(31 downto 0),
DOB=>open,
DOPA=>open,
DOPB=>open);
XLXI_3_0 : GND
port map (G=>XLXN_1(0));
XLXI_3_1 : GND
port map (G=>XLXN_1(1));
XLXI_3_2 : GND
port map (G=>XLXN_1(2));
XLXI_3_3 : GND
port map (G=>XLXN_1(3));
XLXI_3_4 : GND
port map (G=>XLXN_1(4));
XLXI_4_0 : GND
port map (G=>XLXN_1(9));
XLXI_4_1 : GND
port map (G=>XLXN_1(10));
XLXI_4_2 : GND
port map (G=>XLXN_1(11));
XLXI_4_3 : GND
port map (G=>XLXN_1(12));
XLXI_4_4 : GND
port map (G=>XLXN_1(13));
XLXI_4_5 : GND
port map (G=>XLXN_1(14));
XLXI_5 : VCC
port map (P=>XLXN_10);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity ExtractKvPTATParameter_MUSER_CalculateTa is
port ( i_clock : in std_logic;
i_ee0x2432 : in std_logic_vector (15 downto 0);
i_reset : in std_logic;
o_kvptat : out std_logic_vector (31 downto 0));
end ExtractKvPTATParameter_MUSER_CalculateTa;
architecture BEHAVIORAL of ExtractKvPTATParameter_MUSER_CalculateTa is
attribute BOX_TYPE : string ;
attribute DOA_REG : string ;
attribute DOB_REG : string ;
attribute INIT_00 : string ;
attribute INIT_01 : string ;
attribute INIT_02 : string ;
attribute INIT_03 : string ;
attribute INIT_04 : string ;
attribute INIT_05 : string ;
attribute INIT_06 : string ;
attribute INIT_07 : string ;
attribute INIT_08 : string ;
attribute INIT_09 : string ;
attribute INIT_0A : string ;
attribute INIT_0B : string ;
attribute INIT_0C : string ;
attribute INIT_0D : string ;
attribute INIT_0E : string ;
attribute INIT_0F : string ;
attribute INIT_10 : string ;
attribute INIT_11 : string ;
attribute INIT_12 : string ;
attribute INIT_13 : string ;
attribute INIT_14 : string ;
attribute INIT_15 : string ;
attribute INIT_16 : string ;
attribute INIT_17 : string ;
attribute INIT_18 : string ;
attribute INIT_19 : string ;
attribute INIT_1A : string ;
attribute INIT_1B : string ;
attribute INIT_1C : string ;
attribute INIT_1D : string ;
attribute INIT_1E : string ;
attribute INIT_1F : string ;
attribute INIT_20 : string ;
attribute INIT_21 : string ;
attribute INIT_22 : string ;
attribute INIT_23 : string ;
attribute INIT_24 : string ;
attribute INIT_25 : string ;
attribute INIT_26 : string ;
attribute INIT_27 : string ;
attribute INIT_28 : string ;
attribute INIT_29 : string ;
attribute INIT_2A : string ;
attribute INIT_2B : string ;
attribute INIT_2C : string ;
attribute INIT_2D : string ;
attribute INIT_2E : string ;
attribute INIT_2F : string ;
attribute INIT_30 : string ;
attribute INIT_31 : string ;
attribute INIT_32 : string ;
attribute INIT_33 : string ;
attribute INIT_34 : string ;
attribute INIT_35 : string ;
attribute INIT_36 : string ;
attribute INIT_37 : string ;
attribute INIT_38 : string ;
attribute INIT_39 : string ;
attribute INIT_3A : string ;
attribute INIT_3B : string ;
attribute INIT_3C : string ;
attribute INIT_3D : string ;
attribute INIT_3E : string ;
attribute INIT_3F : string ;
attribute INIT_A : string ;
attribute INIT_B : string ;
attribute INITP_00 : string ;
attribute INITP_01 : string ;
attribute INITP_02 : string ;
attribute INITP_03 : string ;
attribute INITP_04 : string ;
attribute INITP_05 : string ;
attribute INITP_06 : string ;
attribute INITP_07 : string ;
attribute INIT_FILE : string ;
attribute INVERT_CLK_DOA_REG : string ;
attribute INVERT_CLK_DOB_REG : string ;
attribute RAM_EXTENSION_A : string ;
attribute RAM_EXTENSION_B : string ;
attribute READ_WIDTH_A : string ;
attribute READ_WIDTH_B : string ;
attribute SRVAL_A : string ;
attribute SRVAL_B : string ;
attribute WRITE_MODE_A : string ;
attribute WRITE_MODE_B : string ;
attribute WRITE_WIDTH_A : string ;
attribute WRITE_WIDTH_B : string ;
attribute SIM_COLLISION_CHECK : string ;
signal ADDRA : std_logic_vector (14 downto 0);
signal XLXN_11 : std_logic;
signal ROM_KVPTAT_ADDRB_openSignal : std_logic_vector (14 downto 0);
signal ROM_KVPTAT_CASCADEINA_openSignal : std_logic;
signal ROM_KVPTAT_CASCADEINB_openSignal : std_logic;
signal ROM_KVPTAT_CLKB_openSignal : std_logic;
signal ROM_KVPTAT_DIA_openSignal : std_logic_vector (31 downto 0);
signal ROM_KVPTAT_DIB_openSignal : std_logic_vector (31 downto 0);
signal ROM_KVPTAT_DIPA_openSignal : std_logic_vector (3 downto 0);
signal ROM_KVPTAT_DIPB_openSignal : std_logic_vector (3 downto 0);
signal ROM_KVPTAT_ENB_openSignal : std_logic;
signal ROM_KVPTAT_REGCEA_openSignal : std_logic;
signal ROM_KVPTAT_REGCEB_openSignal : std_logic;
signal ROM_KVPTAT_SSRB_openSignal : std_logic;
signal ROM_KVPTAT_WEA_openSignal : std_logic_vector (3 downto 0);
signal ROM_KVPTAT_WEB_openSignal : std_logic_vector (3 downto 0);
component BUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUF : component is "BLACK_BOX";
component RAMB16
-- synopsys translate_off
generic( DOA_REG : integer := 0;
DOB_REG : integer := 0;
INIT_00 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_10 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_11 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_12 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_13 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_14 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_15 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_16 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_17 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_18 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_19 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_1F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_20 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_21 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_22 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_23 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_24 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_25 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_26 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_27 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_28 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_29 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_2F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_30 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_31 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_32 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_33 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_34 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_35 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_36 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_37 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_38 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_39 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3A : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3B : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3C : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3D : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3E : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_3F : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_A : bit_vector := x"000000000";
INIT_B : bit_vector := x"000000000";
INITP_00 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_01 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_02 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_03 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_04 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_05 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_06 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INITP_07 : bit_vector :=
x"0000000000000000000000000000000000000000000000000000000000000000";
INIT_FILE : string := "NONE";
INVERT_CLK_DOA_REG : boolean := FALSE;
INVERT_CLK_DOB_REG : boolean := FALSE;
RAM_EXTENSION_A : string := "NONE";
RAM_EXTENSION_B : string := "NONE";
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SRVAL_A : bit_vector := x"000000000";
SRVAL_B : bit_vector := x"000000000";
WRITE_MODE_A : string := "WRITE_FIRST";
WRITE_MODE_B : string := "WRITE_FIRST";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL");
-- synopsys translate_on
port ( ADDRA : in std_logic_vector (14 downto 0);
ADDRB : in std_logic_vector (14 downto 0);
CASCADEINA : in std_logic;
CASCADEINB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_logic;
REGCEA : in std_logic;
REGCEB : in std_logic;
ENB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
WEA : in std_logic_vector (3 downto 0);
WEB : in std_logic_vector (3 downto 0);
CASCADEOUTA : out std_logic;
CASCADEOUTB : out std_logic;
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0));
end component;
attribute DOA_REG of RAMB16 : component is "0";
attribute DOB_REG of RAMB16 : component is "0";
attribute INIT_00 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_01 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_02 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_03 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_04 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_05 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_06 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_07 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_08 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_09 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_0F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_10 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_11 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_12 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_13 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_14 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_15 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_16 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_17 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_18 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_19 of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1A of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1B of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1C of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1D of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1E of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";
attribute INIT_1F of RAMB16 : component is
"0000000000000000000000000000000000000000000000000000000000000000";