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chleroyKernel Patches Daemon
chleroy
authored and
Kernel Patches Daemon
committed
powerpc/bpf/32: Fix failing test_bpf tests
Recent additions in BPF like cpu v4 instructions, test_bpf module exhibits the following failures: test_bpf: #82 ALU_MOVSX | BPF_B jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) test_bpf: #83 ALU_MOVSX | BPF_H jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) test_bpf: #84 ALU64_MOVSX | BPF_B jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) test_bpf: #85 ALU64_MOVSX | BPF_H jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) test_bpf: #86 ALU64_MOVSX | BPF_W jited:1 ret 2 != 1 (0x2 != 0x1)FAIL (1 times) test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times) test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times) test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times) test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times) test_bpf: #172 ALU64_SMOD_K: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times) test_bpf: #313 BSWAP 16: 0x0123456789abcdef -> 0xefcd eBPF filter opcode 00d7 (@2) unsupported jited:0 301 PASS test_bpf: #314 BSWAP 32: 0x0123456789abcdef -> 0xefcdab89 eBPF filter opcode 00d7 (@2) unsupported jited:0 555 PASS test_bpf: #315 BSWAP 64: 0x0123456789abcdef -> 0x67452301 eBPF filter opcode 00d7 (@2) unsupported jited:0 268 PASS test_bpf: #316 BSWAP 64: 0x0123456789abcdef >> 32 -> 0xefcdab89 eBPF filter opcode 00d7 (@2) unsupported jited:0 269 PASS test_bpf: #317 BSWAP 16: 0xfedcba9876543210 -> 0x1032 eBPF filter opcode 00d7 (@2) unsupported jited:0 460 PASS test_bpf: #318 BSWAP 32: 0xfedcba9876543210 -> 0x10325476 eBPF filter opcode 00d7 (@2) unsupported jited:0 320 PASS test_bpf: #319 BSWAP 64: 0xfedcba9876543210 -> 0x98badcfe eBPF filter opcode 00d7 (@2) unsupported jited:0 222 PASS test_bpf: #320 BSWAP 64: 0xfedcba9876543210 >> 32 -> 0x10325476 eBPF filter opcode 00d7 (@2) unsupported jited:0 273 PASS test_bpf: #344 BPF_LDX_MEMSX | BPF_B eBPF filter opcode 0091 (@5) unsupported jited:0 432 PASS test_bpf: #345 BPF_LDX_MEMSX | BPF_H eBPF filter opcode 0089 (@5) unsupported jited:0 381 PASS test_bpf: #346 BPF_LDX_MEMSX | BPF_W eBPF filter opcode 0081 (@5) unsupported jited:0 505 PASS test_bpf: #490 JMP32_JA: Unconditional jump: if (true) return 1 eBPF filter opcode 0006 (@1) unsupported jited:0 261 PASS test_bpf: Summary: 1040 PASSED, 10 FAILED, [924/1038 JIT'ed] Fix them by adding missing processing. Fixes: daabb2b ("bpf/tests: add tests for cpuv4 instructions") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
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2 files changed

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‎arch/powerpc/include/asm/ppc-opcode.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -510,6 +510,7 @@
510510
#define PPC_RAW_STB(r, base, i) (0x98000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
511511
#define PPC_RAW_LBZ(r, base, i) (0x88000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
512512
#define PPC_RAW_LDX(r, base, b) (0x7c00002a | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
513+
#define PPC_RAW_LHA(r, base, i) (0xa8000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
513514
#define PPC_RAW_LHZ(r, base, i) (0xa0000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
514515
#define PPC_RAW_LHBRX(r, base, b) (0x7c00062c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
515516
#define PPC_RAW_LWBRX(r, base, b) (0x7c00042c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
@@ -532,6 +533,7 @@
532533
#define PPC_RAW_MULW(d, a, b) (0x7c0001d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
533534
#define PPC_RAW_MULHWU(d, a, b) (0x7c000016 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
534535
#define PPC_RAW_MULI(d, a, i) (0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
536+
#define PPC_RAW_DIVW(d, a, b) (0x7c0003d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
535537
#define PPC_RAW_DIVWU(d, a, b) (0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
536538
#define PPC_RAW_DIVDU(d, a, b) (0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
537539
#define PPC_RAW_DIVDE(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
@@ -550,6 +552,8 @@
550552
#define PPC_RAW_XOR(d, a, b) (0x7c000278 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
551553
#define PPC_RAW_XORI(d, a, i) (0x68000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
552554
#define PPC_RAW_XORIS(d, a, i) (0x6c000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
555+
#define PPC_RAW_EXTSB(d, a) (0x7c000774 | ___PPC_RA(d) | ___PPC_RS(a))
556+
#define PPC_RAW_EXTSH(d, a) (0x7c000734 | ___PPC_RA(d) | ___PPC_RS(a))
553557
#define PPC_RAW_EXTSW(d, a) (0x7c0007b4 | ___PPC_RA(d) | ___PPC_RS(a))
554558
#define PPC_RAW_SLW(d, a, s) (0x7c000030 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
555559
#define PPC_RAW_SLD(d, a, s) (0x7c000036 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))

‎arch/powerpc/net/bpf_jit_comp32.c‎

Lines changed: 106 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -450,10 +450,16 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
450450
}
451451
break;
452452
case BPF_ALU | BPF_DIV | BPF_X: /* (u32) dst /= (u32) src */
453-
EMIT(PPC_RAW_DIVWU(dst_reg, src2_reg, src_reg));
453+
if (off)
454+
EMIT(PPC_RAW_DIVW(dst_reg, src2_reg, src_reg));
455+
else
456+
EMIT(PPC_RAW_DIVWU(dst_reg, src2_reg, src_reg));
454457
break;
455458
case BPF_ALU | BPF_MOD | BPF_X: /* (u32) dst %= (u32) src */
456-
EMIT(PPC_RAW_DIVWU(_R0, src2_reg, src_reg));
459+
if (off)
460+
EMIT(PPC_RAW_DIVW(_R0, src2_reg, src_reg));
461+
else
462+
EMIT(PPC_RAW_DIVWU(_R0, src2_reg, src_reg));
457463
EMIT(PPC_RAW_MULW(_R0, src_reg, _R0));
458464
EMIT(PPC_RAW_SUB(dst_reg, src2_reg, _R0));
459465
break;
@@ -467,10 +473,16 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
467473
if (imm == 1) {
468474
EMIT(PPC_RAW_MR(dst_reg, src2_reg));
469475
} else if (is_power_of_2((u32)imm)) {
470-
EMIT(PPC_RAW_SRWI(dst_reg, src2_reg, ilog2(imm)));
476+
if (off)
477+
EMIT(PPC_RAW_SRAWI(dst_reg, src2_reg, ilog2(imm)));
478+
else
479+
EMIT(PPC_RAW_SRWI(dst_reg, src2_reg, ilog2(imm)));
471480
} else {
472481
PPC_LI32(_R0, imm);
473-
EMIT(PPC_RAW_DIVWU(dst_reg, src2_reg, _R0));
482+
if (off)
483+
EMIT(PPC_RAW_DIVW(dst_reg, src2_reg, _R0));
484+
else
485+
EMIT(PPC_RAW_DIVWU(dst_reg, src2_reg, _R0));
474486
}
475487
break;
476488
case BPF_ALU | BPF_MOD | BPF_K: /* (u32) dst %= (u32) imm */
@@ -480,11 +492,19 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
480492
if (!is_power_of_2((u32)imm)) {
481493
bpf_set_seen_register(ctx, tmp_reg);
482494
PPC_LI32(tmp_reg, imm);
483-
EMIT(PPC_RAW_DIVWU(_R0, src2_reg, tmp_reg));
495+
if (off)
496+
EMIT(PPC_RAW_DIVW(_R0, src2_reg, tmp_reg));
497+
else
498+
EMIT(PPC_RAW_DIVWU(_R0, src2_reg, tmp_reg));
484499
EMIT(PPC_RAW_MULW(_R0, tmp_reg, _R0));
485500
EMIT(PPC_RAW_SUB(dst_reg, src2_reg, _R0));
486501
} else if (imm == 1) {
487502
EMIT(PPC_RAW_LI(dst_reg, 0));
503+
} else if (off) {
504+
EMIT(PPC_RAW_SRAWI(_R0, src2_reg, ilog2(imm)));
505+
EMIT(PPC_RAW_ADDZE(_R0, _R0));
506+
EMIT(PPC_RAW_SLWI(_R0, _R0, ilog2(imm)));
507+
EMIT(PPC_RAW_SUB(dst_reg, src2_reg, _R0));
488508
} else {
489509
imm = ilog2((u32)imm);
490510
EMIT(PPC_RAW_RLWINM(dst_reg, src2_reg, 0, 32 - imm, 31));
@@ -497,11 +517,21 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
497517
imm = -imm;
498518
if (!is_power_of_2(imm))
499519
return -EOPNOTSUPP;
500-
if (imm == 1)
520+
if (imm == 1) {
501521
EMIT(PPC_RAW_LI(dst_reg, 0));
502-
else
522+
EMIT(PPC_RAW_LI(dst_reg_h, 0));
523+
} else if (off) {
524+
EMIT(PPC_RAW_SRAWI(dst_reg_h, src2_reg_h, 31));
525+
EMIT(PPC_RAW_XOR(dst_reg, src2_reg, dst_reg_h));
526+
EMIT(PPC_RAW_SUBFC(dst_reg, dst_reg_h, dst_reg));
527+
EMIT(PPC_RAW_RLWINM(dst_reg, dst_reg, 0, 32 - ilog2(imm), 31));
528+
EMIT(PPC_RAW_XOR(dst_reg, dst_reg, dst_reg_h));
529+
EMIT(PPC_RAW_SUBFC(dst_reg, dst_reg_h, dst_reg));
530+
EMIT(PPC_RAW_SUBFE(dst_reg_h, dst_reg_h, dst_reg_h));
531+
} else {
503532
EMIT(PPC_RAW_RLWINM(dst_reg, src2_reg, 0, 32 - ilog2(imm), 31));
504-
EMIT(PPC_RAW_LI(dst_reg_h, 0));
533+
EMIT(PPC_RAW_LI(dst_reg_h, 0));
534+
}
505535
break;
506536
case BPF_ALU64 | BPF_DIV | BPF_K: /* dst /= imm */
507537
if (!imm)
@@ -727,15 +757,30 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
727757
* MOV
728758
*/
729759
case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */
730-
if (dst_reg == src_reg)
731-
break;
732-
EMIT(PPC_RAW_MR(dst_reg, src_reg));
733-
EMIT(PPC_RAW_MR(dst_reg_h, src_reg_h));
760+
if (off == 8) {
761+
EMIT(PPC_RAW_EXTSB(dst_reg, src_reg));
762+
EMIT(PPC_RAW_SRAWI(dst_reg_h, dst_reg, 31));
763+
} else if (off == 16) {
764+
EMIT(PPC_RAW_EXTSH(dst_reg, src_reg));
765+
EMIT(PPC_RAW_SRAWI(dst_reg_h, dst_reg, 31));
766+
} else if (off == 32 && dst_reg == src_reg) {
767+
EMIT(PPC_RAW_SRAWI(dst_reg_h, src_reg, 31));
768+
} else if (off == 32) {
769+
EMIT(PPC_RAW_MR(dst_reg, src_reg));
770+
EMIT(PPC_RAW_SRAWI(dst_reg_h, src_reg, 31));
771+
} else if (dst_reg != src_reg) {
772+
EMIT(PPC_RAW_MR(dst_reg, src_reg));
773+
EMIT(PPC_RAW_MR(dst_reg_h, src_reg_h));
774+
}
734775
break;
735776
case BPF_ALU | BPF_MOV | BPF_X: /* (u32) dst = src */
736777
/* special mov32 for zext */
737778
if (imm == 1)
738779
EMIT(PPC_RAW_LI(dst_reg_h, 0));
780+
else if (off == 8)
781+
EMIT(PPC_RAW_EXTSB(dst_reg, src_reg));
782+
else if (off == 16)
783+
EMIT(PPC_RAW_EXTSH(dst_reg, src_reg));
739784
else if (dst_reg != src_reg)
740785
EMIT(PPC_RAW_MR(dst_reg, src_reg));
741786
break;
@@ -751,6 +796,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
751796
* BPF_FROM_BE/LE
752797
*/
753798
case BPF_ALU | BPF_END | BPF_FROM_LE:
799+
case BPF_ALU64 | BPF_END | BPF_FROM_LE:
754800
switch (imm) {
755801
case 16:
756802
/* Copy 16 bits to upper part */
@@ -785,6 +831,8 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
785831
EMIT(PPC_RAW_MR(dst_reg_h, tmp_reg));
786832
break;
787833
}
834+
if (BPF_CLASS(code) == BPF_ALU64 && imm != 64)
835+
EMIT(PPC_RAW_LI(dst_reg_h, 0));
788836
break;
789837
case BPF_ALU | BPF_END | BPF_FROM_BE:
790838
switch (imm) {
@@ -918,11 +966,17 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
918966
* BPF_LDX
919967
*/
920968
case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */
969+
case BPF_LDX | BPF_MEMSX | BPF_B:
921970
case BPF_LDX | BPF_PROBE_MEM | BPF_B:
971+
case BPF_LDX | BPF_PROBE_MEMSX | BPF_B:
922972
case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */
973+
case BPF_LDX | BPF_MEMSX | BPF_H:
923974
case BPF_LDX | BPF_PROBE_MEM | BPF_H:
975+
case BPF_LDX | BPF_PROBE_MEMSX | BPF_H:
924976
case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */
977+
case BPF_LDX | BPF_MEMSX | BPF_W:
925978
case BPF_LDX | BPF_PROBE_MEM | BPF_W:
979+
case BPF_LDX | BPF_PROBE_MEMSX | BPF_W:
926980
case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */
927981
case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
928982
/*
@@ -931,7 +985,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
931985
* load only if addr is kernel address (see is_kernel_addr()), otherwise
932986
* set dst_reg=0 and move on.
933987
*/
934-
if (BPF_MODE(code) == BPF_PROBE_MEM) {
988+
if (BPF_MODE(code) == BPF_PROBE_MEM || BPF_MODE(code) == BPF_PROBE_MEMSX) {
935989
PPC_LI32(_R0, TASK_SIZE - off);
936990
EMIT(PPC_RAW_CMPLW(src_reg, _R0));
937991
PPC_BCC_SHORT(COND_GT, (ctx->idx + 4) * 4);
@@ -953,30 +1007,48 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
9531007
* as there are two load instructions for dst_reg_h & dst_reg
9541008
* respectively.
9551009
*/
956-
if (size == BPF_DW)
1010+
if (size == BPF_DW ||
1011+
(size == BPF_B && BPF_MODE(code) == BPF_PROBE_MEMSX))
9571012
PPC_JMP((ctx->idx + 3) * 4);
9581013
else
9591014
PPC_JMP((ctx->idx + 2) * 4);
9601015
}
9611016

962-
switch (size) {
963-
case BPF_B:
964-
EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off));
965-
break;
966-
case BPF_H:
967-
EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off));
968-
break;
969-
case BPF_W:
970-
EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off));
971-
break;
972-
case BPF_DW:
973-
EMIT(PPC_RAW_LWZ(dst_reg_h, src_reg, off));
974-
EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off + 4));
975-
break;
976-
}
1017+
if (BPF_MODE(code) == BPF_MEMSX || BPF_MODE(code) == BPF_PROBE_MEMSX) {
1018+
switch (size) {
1019+
case BPF_B:
1020+
EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off));
1021+
EMIT(PPC_RAW_EXTSB(dst_reg, dst_reg));
1022+
break;
1023+
case BPF_H:
1024+
EMIT(PPC_RAW_LHA(dst_reg, src_reg, off));
1025+
break;
1026+
case BPF_W:
1027+
EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off));
1028+
break;
1029+
}
1030+
if (!fp->aux->verifier_zext)
1031+
EMIT(PPC_RAW_SRAWI(dst_reg_h, dst_reg, 31));
9771032

978-
if (size != BPF_DW && !fp->aux->verifier_zext)
979-
EMIT(PPC_RAW_LI(dst_reg_h, 0));
1033+
} else {
1034+
switch (size) {
1035+
case BPF_B:
1036+
EMIT(PPC_RAW_LBZ(dst_reg, src_reg, off));
1037+
break;
1038+
case BPF_H:
1039+
EMIT(PPC_RAW_LHZ(dst_reg, src_reg, off));
1040+
break;
1041+
case BPF_W:
1042+
EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off));
1043+
break;
1044+
case BPF_DW:
1045+
EMIT(PPC_RAW_LWZ(dst_reg_h, src_reg, off));
1046+
EMIT(PPC_RAW_LWZ(dst_reg, src_reg, off + 4));
1047+
break;
1048+
}
1049+
if (size != BPF_DW && !fp->aux->verifier_zext)
1050+
EMIT(PPC_RAW_LI(dst_reg_h, 0));
1051+
}
9801052

9811053
if (BPF_MODE(code) == BPF_PROBE_MEM) {
9821054
int insn_idx = ctx->idx - 1;
@@ -1068,6 +1140,9 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, u32 *fimage, struct code
10681140
case BPF_JMP | BPF_JA:
10691141
PPC_JMP(addrs[i + 1 + off]);
10701142
break;
1143+
case BPF_JMP32 | BPF_JA:
1144+
PPC_JMP(addrs[i + 1 + imm]);
1145+
break;
10711146

10721147
case BPF_JMP | BPF_JGT | BPF_K:
10731148
case BPF_JMP | BPF_JGT | BPF_X:

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