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Lijo Lazaralexdeucher
Lijo Lazar
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alexdeucher
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drm/amdgpu: Add sysfs nodes to get xcp details
Add partition config nodes in sysfs to get resource instance details for a particular partition mode. A resource could be anything like an xcc, vcn decoder, system dma units etc. Details of various resource instances are available under /sys/bus/pci/devices/.../compute_partition_config/ Select a partition configuration: /sys/bus/pci/devices/.../compute_partition_config/xcp_config Number of instances of a resource: /sys/bus/pci/devices/.../compute_partition_config/<rsrc_name>/num_inst Total partitions sharing the resource: /sys/bus/pci/devices/.../compute_partition_config/<rsrc_name>/num_shared v2: Update node name as per spec Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4486,6 +4486,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
44864486

44874487
amdgpu_fru_sysfs_init(adev);
44884488
amdgpu_reg_state_sysfs_init(adev);
4489+
amdgpu_xcp_cfg_sysfs_init(adev);
44894490

44904491
if (IS_ENABLED(CONFIG_PERF_EVENTS))
44914492
r = amdgpu_pmu_init(adev);
@@ -4608,6 +4609,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
46084609
amdgpu_fru_sysfs_fini(adev);
46094610

46104611
amdgpu_reg_state_sysfs_fini(adev);
4612+
amdgpu_xcp_cfg_sysfs_fini(adev);
46114613

46124614
/* disable ras feature must before hw fini */
46134615
amdgpu_ras_pre_fini(adev);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c‎

Lines changed: 201 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -433,3 +433,204 @@ void amdgpu_xcp_release_sched(struct amdgpu_device *adev,
433433
}
434434
}
435435

436+
#define XCP_CFG_SYSFS_RES_ATTR_SHOW(_name) \
437+
static ssize_t amdgpu_xcp_res_sysfs_##_name##_show( \
438+
struct amdgpu_xcp_res_details *xcp_res, char *buf) \
439+
{ \
440+
return sysfs_emit(buf, "%d\n", xcp_res->_name); \
441+
}
442+
443+
struct amdgpu_xcp_res_sysfs_attribute {
444+
struct attribute attr;
445+
ssize_t (*show)(struct amdgpu_xcp_res_details *xcp_res, char *buf);
446+
};
447+
448+
#define XCP_CFG_SYSFS_RES_ATTR(_name) \
449+
struct amdgpu_xcp_res_sysfs_attribute xcp_res_sysfs_attr_##_name = { \
450+
.attr = { .name = __stringify(_name), .mode = 0400 }, \
451+
.show = amdgpu_xcp_res_sysfs_##_name##_show, \
452+
}
453+
454+
XCP_CFG_SYSFS_RES_ATTR_SHOW(num_inst)
455+
XCP_CFG_SYSFS_RES_ATTR(num_inst);
456+
XCP_CFG_SYSFS_RES_ATTR_SHOW(num_shared)
457+
XCP_CFG_SYSFS_RES_ATTR(num_shared);
458+
459+
#define XCP_CFG_SYSFS_RES_ATTR_PTR(_name) xcp_res_sysfs_attr_##_name.attr
460+
461+
static struct attribute *xcp_cfg_res_sysfs_attrs[] = {
462+
&XCP_CFG_SYSFS_RES_ATTR_PTR(num_inst),
463+
&XCP_CFG_SYSFS_RES_ATTR_PTR(num_shared), NULL
464+
};
465+
466+
ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs);
467+
468+
#define to_xcp_attr(x) \
469+
container_of(x, struct amdgpu_xcp_res_sysfs_attribute, attr)
470+
#define to_xcp_res(x) container_of(x, struct amdgpu_xcp_res_details, kobj)
471+
472+
static ssize_t xcp_cfg_res_sysfs_attr_show(struct kobject *kobj,
473+
struct attribute *attr, char *buf)
474+
{
475+
struct amdgpu_xcp_res_sysfs_attribute *attribute;
476+
struct amdgpu_xcp_res_details *xcp_res;
477+
478+
attribute = to_xcp_attr(attr);
479+
xcp_res = to_xcp_res(kobj);
480+
481+
if (!attribute->show)
482+
return -EIO;
483+
484+
return attribute->show(xcp_res, buf);
485+
}
486+
487+
static const struct sysfs_ops xcp_cfg_res_sysfs_ops = {
488+
.show = xcp_cfg_res_sysfs_attr_show,
489+
};
490+
491+
static const struct kobj_type xcp_cfg_res_sysfs_ktype = {
492+
.sysfs_ops = &xcp_cfg_res_sysfs_ops,
493+
.default_groups = xcp_cfg_res_sysfs_groups,
494+
};
495+
496+
const char *xcp_res_names[] = {
497+
[AMDGPU_XCP_RES_XCC] = "xcc",
498+
[AMDGPU_XCP_RES_DMA] = "dma",
499+
[AMDGPU_XCP_RES_DEC] = "dec",
500+
[AMDGPU_XCP_RES_JPEG] = "jpeg",
501+
};
502+
503+
static int amdgpu_xcp_get_res_info(struct amdgpu_xcp_mgr *xcp_mgr,
504+
int mode,
505+
struct amdgpu_xcp_cfg *xcp_cfg)
506+
{
507+
if (xcp_mgr->funcs && xcp_mgr->funcs->get_xcp_res_info)
508+
return xcp_mgr->funcs->get_xcp_res_info(xcp_mgr, mode, xcp_cfg);
509+
510+
return -EOPNOTSUPP;
511+
}
512+
513+
#define to_xcp_cfg(x) container_of(x, struct amdgpu_xcp_cfg, kobj)
514+
static ssize_t xcp_config_show(struct kobject *kobj,
515+
struct kobj_attribute *attr, char *buf)
516+
{
517+
struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj);
518+
519+
return sysfs_emit(buf, "%s\n",
520+
amdgpu_gfx_compute_mode_desc(xcp_cfg->mode));
521+
}
522+
523+
static ssize_t xcp_config_store(struct kobject *kobj,
524+
struct kobj_attribute *attr,
525+
const char *buf, size_t size)
526+
{
527+
struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj);
528+
int mode, r;
529+
530+
if (!strncasecmp("SPX", buf, strlen("SPX")))
531+
mode = AMDGPU_SPX_PARTITION_MODE;
532+
else if (!strncasecmp("DPX", buf, strlen("DPX")))
533+
mode = AMDGPU_DPX_PARTITION_MODE;
534+
else if (!strncasecmp("TPX", buf, strlen("TPX")))
535+
mode = AMDGPU_TPX_PARTITION_MODE;
536+
else if (!strncasecmp("QPX", buf, strlen("QPX")))
537+
mode = AMDGPU_QPX_PARTITION_MODE;
538+
else if (!strncasecmp("CPX", buf, strlen("CPX")))
539+
mode = AMDGPU_CPX_PARTITION_MODE;
540+
else
541+
return -EINVAL;
542+
543+
r = amdgpu_xcp_get_res_info(xcp_cfg->xcp_mgr, mode, xcp_cfg);
544+
545+
if (r)
546+
return r;
547+
548+
xcp_cfg->mode = mode;
549+
return size;
550+
}
551+
552+
static struct kobj_attribute xcp_cfg_sysfs_mode =
553+
__ATTR_RW_MODE(xcp_config, 0644);
554+
555+
static void xcp_cfg_sysfs_release(struct kobject *kobj)
556+
{
557+
struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj);
558+
559+
kfree(xcp_cfg);
560+
}
561+
562+
static const struct kobj_type xcp_cfg_sysfs_ktype = {
563+
.release = xcp_cfg_sysfs_release,
564+
.sysfs_ops = &kobj_sysfs_ops,
565+
};
566+
567+
void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev)
568+
{
569+
struct amdgpu_xcp_res_details *xcp_res;
570+
struct amdgpu_xcp_cfg *xcp_cfg;
571+
int i, r, j, rid;
572+
573+
if (!adev->xcp_mgr)
574+
return;
575+
576+
xcp_cfg = kzalloc(sizeof(*xcp_cfg), GFP_KERNEL);
577+
if (!xcp_cfg)
578+
return;
579+
xcp_cfg->xcp_mgr = adev->xcp_mgr;
580+
581+
r = kobject_init_and_add(&xcp_cfg->kobj, &xcp_cfg_sysfs_ktype,
582+
&adev->dev->kobj, "compute_partition_config");
583+
if (r)
584+
goto err1;
585+
586+
r = sysfs_create_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr);
587+
if (r)
588+
goto err1;
589+
590+
r = amdgpu_xcp_get_res_info(xcp_cfg->xcp_mgr, xcp_cfg->xcp_mgr->mode, xcp_cfg);
591+
if (r)
592+
goto err1;
593+
594+
xcp_cfg->mode = xcp_cfg->xcp_mgr->mode;
595+
for (i = 0; i < xcp_cfg->num_res; i++) {
596+
xcp_res = &xcp_cfg->xcp_res[i];
597+
rid = xcp_res->id;
598+
r = kobject_init_and_add(&xcp_res->kobj,
599+
&xcp_cfg_res_sysfs_ktype,
600+
&xcp_cfg->kobj, "%s",
601+
xcp_res_names[rid]);
602+
if (r)
603+
goto err;
604+
}
605+
606+
adev->xcp_mgr->xcp_cfg = xcp_cfg;
607+
return;
608+
err:
609+
for (j = 0; j < i; j++) {
610+
xcp_res = &xcp_cfg->xcp_res[i];
611+
kobject_put(&xcp_res->kobj);
612+
}
613+
614+
sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr);
615+
err1:
616+
kobject_put(&xcp_cfg->kobj);
617+
}
618+
619+
void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev)
620+
{
621+
struct amdgpu_xcp_res_details *xcp_res;
622+
struct amdgpu_xcp_cfg *xcp_cfg;
623+
int i;
624+
625+
if (!adev->xcp_mgr)
626+
return;
627+
628+
xcp_cfg = adev->xcp_mgr->xcp_cfg;
629+
for (i = 0; i < xcp_cfg->num_res; i++) {
630+
xcp_res = &xcp_cfg->xcp_res[i];
631+
kobject_put(&xcp_res->kobj);
632+
}
633+
634+
sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr);
635+
kobject_put(&xcp_cfg->kobj);
636+
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,13 +68,15 @@ struct amdgpu_xcp_res_details {
6868
enum amdgpu_xcp_res_id id;
6969
u8 num_inst;
7070
u8 num_shared;
71+
struct kobject kobj;
7172
};
7273

7374
struct amdgpu_xcp_cfg {
7475
u8 mode;
7576
struct amdgpu_xcp_res_details xcp_res[AMDGPU_XCP_RES_MAX];
7677
u8 num_res;
7778
struct amdgpu_xcp_mgr *xcp_mgr;
79+
struct kobject kobj;
7880
};
7981

8082
struct amdgpu_xcp_ip_funcs {
@@ -172,6 +174,9 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev,
172174
void amdgpu_xcp_release_sched(struct amdgpu_device *adev,
173175
struct amdgpu_ctx_entity *entity);
174176

177+
void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev);
178+
void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev);
179+
175180
#define amdgpu_xcp_select_scheds(adev, e, c, d, x, y) \
176181
((adev)->xcp_mgr && (adev)->xcp_mgr->funcs && \
177182
(adev)->xcp_mgr->funcs->select_scheds ? \

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