Help: Aisler Errors in Smart Testing

[kamronbatman]

Hey everyone,

I decided to venture into DIY hardware and this is my first project so I need some guidance.

I ordered boards based on the newest specs and it looks like they came back with errors during testing. Does this mean I should ask them to manufacture them again since they will be defective? Or is this ok?

Thanks!

[stapelberg]

I ordered boards based on the newest specs and it looks like they came back with errors during testing. Does this mean I should ask them to manufacture them again since they will be defective? Or is this ok?

The component in question is the solder jumper, so I’m leaning towards saying that this is okay and nothing to worry about.

I’m not entirely sure why you’re getting this error and not others (or maybe others are getting the error, too?). Maybe this changed with KiCad 6, or maybe we should be doing something differently in our design files… Maybe someone with more KiCad experience can weigh in.

[kamronbatman]

Here is the response from support:

[stapelberg]

I wonder if this issue was introduced with commit afac759 (cc @cincodenada)

If you want a known-working revision, v2021-04-25 is the latest revision that I have in my keyboards. Sorry for the trouble with this.

[kamronbatman]

Do you think I'm going to have to put another order in and throw those out?

For context I'm going to be using this with the kinesis advantage 2, with a teensy 4.1.

Instead of remanufacturing them, can I somehow cut/wire the shorted pathways especially since they are jumpers? I'm very new to this but willing to learn.

[stapelberg]

To be quite honest, even after re-reading the support reply, I’m not sure if there really is a problem with the boards.

In the reply, JP4, JP5 and JP6 are listed, and those are all the connected-by-default solder jumpers on the board. I’m still suspecting that either their tool gets tripped up by solder jumpers, or that we have somehow incorrectly designed/placed the solder jumpers.

A connection between J5/1 and U1/7 (the “fault” the e-tester found) is expected, so maybe no correction is necessary at all and the board just works.

But, yes, in case you do need to correct something, I think you could just cut traces close to the Teensy pins on the PCB. I would give it a try (no need to order a new revision just yet), but be sure you have more than one Teensy in case something goes wrong :)

[kamronbatman]

I ordered 3 of everything, but I am thinking about ordering removable pin headers for the teensy, so if I have to cut/desolder, it's only pin headers. 🤔

[aleb]

The boards are fine. I also noticed this error before. Aisler's software expects these "nets" to be disconnected. The idea is that if they are connected then they should be a single "net".

[cincodenada]

Oh sorry, I had drafted a reply but never finished it! The others are correct, yes, the boards should function just fine - the net-ties here are indeed intentional, the jumpers are intended to be connected these two nets in the normal case. If you were working with a Teensy 2.0 you would cut them to disconnect them, but since you're working with a Teensy 4, you don't need to cut any traces or change anything, you can just use the board as designed.

I'm not sure if there is a way to notate that in a way that Aisler will be happy with, I thought that the new version of KiCad had improved net-tie support, but I'm not familiar enough with the details of those exports to know - are you uploading the KiCad files directly to Aisler, or exported/generated gerbers, or something else?

[cincodenada]

If there's an easy way to notate this in a way that will make Aisler's checker happy, that would be optimal, otherwise we might want to add a note to the README about ignoring errors about shorts in JP4/5/6

[kamronbatman]

yeah, I am not sure how to either, but I can ask their support. I uploaded the kint.kicad_pcb file directly. Maybe I was supposed to send them other files too, but I didn't see a way to do that, so I am not sure.

[stapelberg]

Maybe I was supposed to send them other files too, but I didn't see a way to do that, so I am not sure.

No, the advantage of Aisler and other modern manufacturers is that you only need to upload one kicad file and they do the remaining processing.

[kamronbatman]

Thank you everyone for the support!

[stapelberg]

Let’s leave this issue open for easier discoverability. And, ideally someone could contribute a fix to make the design just work with Aisler’s checker :)

[impaktor]

(github allows pinning an issue. Not sure if it only works for open or also possible for closed issues).