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Preliminary tests complete
Z80all instruction exerciser
<adc,sbc> hl,<bc,de,hl,sp>.... OK
add hl,<bc,de,hl,sp>.......... OK
add ix,<bc,de,ix,sp>.......... OK
add iy,<bc,de,iy,sp>.......... OK
aluop a,nn.................... OK
aluop a,<b,c,d,e,h,l,(hl),a>.. OK
aluop a,<ixh,ixl,iyh,iyl>..... OK
aluop a,(<ix,iy>+1)........... OK
bit n,(<ix,iy>+1)............. OK
bit n,<b,c,d,e,h,l,(hl),a>.... OK
cpd<r>........................ OK
cpi<r>........................ OK
<daa,cpl,scf,ccf>............. OK
This raises some thoughts:
Our implementation of SCF and other instructions may be wrong.
ZEXALL is not ideal.
Marking this a bug to reflect the severity of the issue.
The text was updated successfully, but these errors were encountered:
In an attempt to make sure we do the right thing about the
WZ
register for the undocumentedBIT r, b, (i + d)
instructions (#21 and #22), I ran into the PORTAR MSX I/O MAPPING paper, http://datassette.nyc3.cdn.digitaloceanspaces.com/tech/portarmsxiomapping.pdf . It says:With our current implementation being changed to that, we still seem to pass
ZEXALL
:This raises some thoughts:
SCF
and other instructions may be wrong.ZEXALL
is not ideal.Marking this a bug to reflect the severity of the issue.
The text was updated successfully, but these errors were encountered: