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hwintrinsiccodegenarm64.cpp
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// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
#include "jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif
#ifdef FEATURE_HW_INTRINSICS
#include "codegen.h"
// HWIntrinsicImmOpHelper: constructs the helper class instance.
// This also determines what type of "switch" table is being used (if an immediate operand is not constant) and do
// some preparation work:
//
// a) If an immediate operand can be either 0 or 1, this creates <nonZeroLabel>.
//
// b) If an immediate operand can take any value in [0, upperBound), this extract a internal register from an
// intrinsic node. The register will be later used to store computed branch target address.
//
// Arguments:
// codeGen -- an instance of CodeGen class.
// immOp -- an immediate operand of the intrinsic.
// intrin -- a hardware intrinsic tree node.
//
// Note: This class is designed to be used in the following way
// HWIntrinsicImmOpHelper helper(this, immOp, intrin);
//
// for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
// {
// -- emit an instruction for a given value of helper.ImmValue()
// }
//
// This allows to combine logic for cases when immOp->isContainedIntOrIImmed() is either true or false in a form
// of a for-loop.
//
CodeGen::HWIntrinsicImmOpHelper::HWIntrinsicImmOpHelper(CodeGen* codeGen, GenTree* immOp, GenTreeHWIntrinsic* intrin)
: codeGen(codeGen)
, endLabel(nullptr)
, nonZeroLabel(nullptr)
, branchTargetReg(REG_NA)
{
assert(codeGen != nullptr);
assert(varTypeIsIntegral(immOp));
if (immOp->isContainedIntOrIImmed())
{
nonConstImmReg = REG_NA;
immValue = (int)immOp->AsIntCon()->IconValue();
immLowerBound = immValue;
immUpperBound = immValue;
}
else
{
const HWIntrinsicCategory category = HWIntrinsicInfo::lookupCategory(intrin->GetHWIntrinsicId());
if (category == HW_Category_SIMDByIndexedElement)
{
const HWIntrinsic intrinInfo(intrin);
var_types indexedElementOpType;
if (intrinInfo.numOperands == 3)
{
indexedElementOpType = intrinInfo.op2->TypeGet();
}
else
{
assert(intrinInfo.numOperands == 4);
indexedElementOpType = intrinInfo.op3->TypeGet();
}
assert(varTypeIsSIMD(indexedElementOpType));
const unsigned int indexedElementSimdSize = genTypeSize(indexedElementOpType);
HWIntrinsicInfo::lookupImmBounds(intrin->GetHWIntrinsicId(), indexedElementSimdSize,
intrin->GetSimdBaseType(), 1, &immLowerBound, &immUpperBound);
}
else
{
HWIntrinsicInfo::lookupImmBounds(intrin->GetHWIntrinsicId(), intrin->GetSimdSize(),
intrin->GetSimdBaseType(), 1, &immLowerBound, &immUpperBound);
}
nonConstImmReg = immOp->GetRegNum();
immValue = immLowerBound;
if (TestImmOpZeroOrOne())
{
nonZeroLabel = codeGen->genCreateTempLabel();
}
else
{
// At the moment, this helper supports only intrinsics that correspond to one machine instruction.
// If we ever encounter an intrinsic that is either lowered into multiple instructions or
// the number of instructions that correspond to each case is unknown apriori - we can extend support to
// these by
// using the same approach as in hwintrinsicxarch.cpp - adding an additional indirection level in form of a
// branch table.
branchTargetReg = codeGen->internalRegisters.GetSingle(intrin);
}
endLabel = codeGen->genCreateTempLabel();
}
}
// HWIntrinsicImmOpHelper: Variant constructor of the helper class instance.
// This is used when the immediate does not exist in a GenTree. For example, the immediate has been created
// during codegen from other immediate values.
//
// Arguments:
// codeGen -- an instance of CodeGen class.
// immReg -- the register containing the immediate.
// immLowerBound -- the lower bound of the register.
// immUpperBound -- the lower bound of the register.
// intrin -- a hardware intrinsic tree node.
//
// Note: This instance is designed to be used via the same for loop as the standard constructor.
//
CodeGen::HWIntrinsicImmOpHelper::HWIntrinsicImmOpHelper(
CodeGen* codeGen, regNumber immReg, int immLowerBound, int immUpperBound, GenTreeHWIntrinsic* intrin)
: codeGen(codeGen)
, endLabel(nullptr)
, nonZeroLabel(nullptr)
, immValue(immLowerBound)
, immLowerBound(immLowerBound)
, immUpperBound(immUpperBound)
, nonConstImmReg(immReg)
, branchTargetReg(REG_NA)
{
assert(codeGen != nullptr);
if (TestImmOpZeroOrOne())
{
nonZeroLabel = codeGen->genCreateTempLabel();
}
else
{
// At the moment, this helper supports only intrinsics that correspond to one machine instruction.
// If we ever encounter an intrinsic that is either lowered into multiple instructions or
// the number of instructions that correspond to each case is unknown apriori - we can extend support to
// these by
// using the same approach as in hwintrinsicxarch.cpp - adding an additional indirection level in form of a
// branch table.
branchTargetReg = codeGen->internalRegisters.GetSingle(intrin);
}
endLabel = codeGen->genCreateTempLabel();
}
//------------------------------------------------------------------------
// EmitBegin: emits the beginning of a "switch" table, no-op if an immediate operand is constant.
//
// Note: The function is called at the beginning of code generation and emits
// a) If an immediate operand can be either 0 or 1
//
// cbnz <nonZeroLabel>, nonConstImmReg
//
// b) If an immediate operand can take any value in [0, upperBound) range
//
// adr branchTargetReg, <beginLabel>
// add branchTargetReg, branchTargetReg, nonConstImmReg, lsl #3
// br branchTargetReg
//
// When an immediate operand is non constant this also defines <beginLabel> right after the emitted code.
//
void CodeGen::HWIntrinsicImmOpHelper::EmitBegin()
{
if (NonConstImmOp())
{
BasicBlock* beginLabel = codeGen->genCreateTempLabel();
if (TestImmOpZeroOrOne())
{
GetEmitter()->emitIns_J_R(INS_cbnz, EA_4BYTE, nonZeroLabel, nonConstImmReg);
}
else
{
// Here we assume that each case consists of one arm64 instruction followed by "b endLabel".
// Since an arm64 instruction is 4 bytes, we branch to AddressOf(beginLabel) + (nonConstImmReg << 3).
GetEmitter()->emitIns_R_L(INS_adr, EA_8BYTE, beginLabel, branchTargetReg);
GetEmitter()->emitIns_R_R_R_I(INS_add, EA_8BYTE, branchTargetReg, branchTargetReg, nonConstImmReg, 3,
INS_OPTS_LSL);
// If the lower bound is non zero we need to adjust the branch target value by subtracting
// (immLowerBound << 3).
if (immLowerBound != 0)
{
GetEmitter()->emitIns_R_R_I(INS_sub, EA_8BYTE, branchTargetReg, branchTargetReg,
((ssize_t)immLowerBound << 3));
}
GetEmitter()->emitIns_R(INS_br, EA_8BYTE, branchTargetReg);
}
codeGen->genDefineInlineTempLabel(beginLabel);
}
}
//------------------------------------------------------------------------
// EmitCaseEnd: emits the end of a "case", no-op if an immediate operand is constant.
//
// Note: The function is called at the end of each "case" (i.e. after an instruction has been emitted for a given
// immediate value ImmValue())
// and emits
//
// b <endLabel>
//
// After the last "case" this defines <endLabel>.
//
// If an immediate operand is either 0 or 1 it also defines <nonZeroLabel> after the first "case".
//
void CodeGen::HWIntrinsicImmOpHelper::EmitCaseEnd()
{
assert(!Done());
if (NonConstImmOp())
{
const bool isLastCase = (immValue == immUpperBound);
if (isLastCase)
{
codeGen->genDefineInlineTempLabel(endLabel);
}
else
{
GetEmitter()->emitIns_J(INS_b, endLabel);
if (TestImmOpZeroOrOne())
{
codeGen->genDefineInlineTempLabel(nonZeroLabel);
}
else
{
BasicBlock* tempLabel = codeGen->genCreateTempLabel();
codeGen->genDefineInlineTempLabel(tempLabel);
}
}
}
immValue++;
}
//------------------------------------------------------------------------
// genHWIntrinsic: Generates the code for a given hardware intrinsic node.
//
// Arguments:
// node - The hardware intrinsic node
//
void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
{
const HWIntrinsic intrin(node);
// We need to validate that other phases of the compiler haven't introduced unsupported intrinsics
assert(compiler->compIsaSupportedDebugOnly(HWIntrinsicInfo::lookupIsa(intrin.id)));
regNumber targetReg = node->GetRegNum();
regNumber op1Reg = REG_NA;
regNumber op2Reg = REG_NA;
regNumber op3Reg = REG_NA;
regNumber op4Reg = REG_NA;
switch (intrin.numOperands)
{
case 4:
assert(intrin.op4 != nullptr);
op4Reg = intrin.op4->GetRegNum();
FALLTHROUGH;
case 3:
assert(intrin.op3 != nullptr);
op3Reg = intrin.op3->GetRegNum();
FALLTHROUGH;
case 2:
assert(intrin.op2 != nullptr);
op2Reg = intrin.op2->GetRegNum();
FALLTHROUGH;
case 1:
assert(intrin.op1 != nullptr);
op1Reg = intrin.op1->GetRegNum();
break;
case 0:
break;
default:
unreached();
}
emitAttr emitSize;
insOpts opt;
if (HWIntrinsicInfo::SIMDScalar(intrin.id))
{
emitSize = emitTypeSize(intrin.baseType);
opt = INS_OPTS_NONE;
}
else if (intrin.category == HW_Category_Scalar)
{
emitSize = emitActualTypeSize(intrin.baseType);
opt = INS_OPTS_NONE;
}
else if (intrin.category == HW_Category_Special)
{
assert(intrin.id == NI_ArmBase_Yield);
emitSize = EA_UNKNOWN;
opt = INS_OPTS_NONE;
}
else if (HWIntrinsicInfo::IsScalable(intrin.id))
{
emitSize = EA_SCALABLE;
opt = emitter::optGetSveInsOpt(emitTypeSize(intrin.baseType));
}
else
{
emitSize = emitActualTypeSize(Compiler::getSIMDTypeForSize(node->GetSimdSize()));
opt = genGetSimdInsOpt(emitSize, intrin.baseType);
}
const bool isRMW = node->isRMWHWIntrinsic(compiler);
const bool hasImmediateOperand = HWIntrinsicInfo::HasImmediateOperand(intrin.id);
genConsumeMultiOpOperands(node);
if (intrin.codeGenIsTableDriven())
{
const instruction ins = HWIntrinsicInfo::lookupIns(intrin.id, intrin.baseType);
assert(ins != INS_invalid);
if (intrin.category == HW_Category_SIMDByIndexedElement)
{
if (hasImmediateOperand)
{
if (isRMW)
{
if (targetReg != op1Reg)
{
assert(targetReg != op2Reg);
assert(targetReg != op3Reg);
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
}
HWIntrinsicImmOpHelper helper(this, intrin.op4, node);
for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
{
const int elementIndex = helper.ImmValue();
GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op2Reg, op3Reg, elementIndex, opt);
}
}
else
{
HWIntrinsicImmOpHelper helper(this, intrin.op3, node);
for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
{
const int elementIndex = helper.ImmValue();
GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op1Reg, op2Reg, elementIndex, opt);
}
}
}
else
{
if (isRMW)
{
if (targetReg != op1Reg)
{
assert(targetReg != op2Reg);
assert(targetReg != op3Reg);
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
}
GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op2Reg, op3Reg, 0, opt);
}
else
{
GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op1Reg, op2Reg, 0, opt);
}
}
}
else if ((intrin.category == HW_Category_ShiftLeftByImmediate) ||
(intrin.category == HW_Category_ShiftRightByImmediate))
{
assert(hasImmediateOperand);
auto emitShift = [&](GenTree* op, regNumber reg) {
HWIntrinsicImmOpHelper helper(this, op, node);
for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
{
const int shiftAmount = helper.ImmValue();
if (shiftAmount == 0)
{
// TODO: Use emitIns_Mov instead.
// We do not use it currently because it will still elide the 'mov'
// even if 'canSkip' is false. We cannot elide the 'mov' here.
GetEmitter()->emitIns_R_R_R(INS_mov, emitTypeSize(node), targetReg, reg, reg);
}
else
{
GetEmitter()->emitIns_R_R_I(ins, emitSize, targetReg, reg, shiftAmount, opt);
}
}
};
if (isRMW)
{
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg, /* canSkip */ true);
emitShift(intrin.op3, op2Reg);
}
else
{
emitShift(intrin.op2, op1Reg);
}
}
else if (HWIntrinsicInfo::HasEnumOperand(intrin.id))
{
assert(hasImmediateOperand);
switch (intrin.numOperands)
{
case 1:
{
HWIntrinsicImmOpHelper helper(this, intrin.op1, node);
for (helper.EmitBegin(); !helper.Done(); helper.EmitCaseEnd())
{
const insSvePattern pattern = (insSvePattern)helper.ImmValue();
GetEmitter()->emitIns_R_PATTERN(ins, emitSize, targetReg, opt, pattern);
}
};
break;
default:
unreached();
}
}
else if (intrin.numOperands >= 2 && intrin.op2->IsEmbMaskOp())
{
// Handle case where op2 is operation that needs embedded mask
GenTree* op2 = intrin.op2;
assert(intrin.id == NI_Sve_ConditionalSelect);
assert(op2->OperIsHWIntrinsic());
assert(op2->isContained());
// Get the registers and intrinsics that needs embedded mask
const HWIntrinsic intrinEmbMask(op2->AsHWIntrinsic());
instruction insEmbMask = HWIntrinsicInfo::lookupIns(intrinEmbMask.id, intrinEmbMask.baseType);
const bool instrIsRMW = op2->isRMWHWIntrinsic(compiler);
regNumber maskReg = op1Reg;
regNumber embMaskOp1Reg = REG_NA;
regNumber embMaskOp2Reg = REG_NA;
regNumber embMaskOp3Reg = REG_NA;
regNumber falseReg = op3Reg;
switch (intrinEmbMask.numOperands)
{
case 3:
assert(intrinEmbMask.op3 != nullptr);
embMaskOp3Reg = intrinEmbMask.op3->GetRegNum();
FALLTHROUGH;
case 2:
assert(intrinEmbMask.op2 != nullptr);
embMaskOp2Reg = intrinEmbMask.op2->GetRegNum();
FALLTHROUGH;
case 1:
assert(intrinEmbMask.op1 != nullptr);
embMaskOp1Reg = intrinEmbMask.op1->GetRegNum();
break;
default:
unreached();
}
switch (intrinEmbMask.numOperands)
{
case 1:
{
assert(!instrIsRMW);
if (targetReg != falseReg)
{
// If targetReg is not the same as `falseReg` then need to move
// the `falseReg` to `targetReg`.
if (intrin.op3->isContained())
{
assert(intrin.op3->IsVectorZero());
if (intrin.op1->isContained() || intrin.op1->IsMaskAllBitsSet())
{
// We already skip importing ConditionalSelect if op1 == trueAll, however
// if we still see it here, it is because we wrapped the predicated instruction
// inside ConditionalSelect.
// As such, no need to move the `falseReg` to `targetReg`
// because the predicated instruction will eventually set it.
}
else
{
// If falseValue is zero, just zero out those lanes of targetReg using `movprfx`
// and /Z
GetEmitter()->emitIns_R_R_R(INS_sve_movprfx, emitSize, targetReg, maskReg, targetReg,
opt);
}
}
else if (emitter::isVectorRegister(embMaskOp1Reg) && (targetReg == embMaskOp1Reg))
{
// target != falseValue, but we do not want to overwrite target with `embMaskOp1Reg`.
// We will first do the predicate operation and then do conditionalSelect inactive
// elements from falseValue
// We cannot use use `movprfx` here to move falseReg to targetReg because that will
// overwrite the value of embMaskOp1Reg which is present in targetReg.
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg, opt);
GetEmitter()->emitIns_R_R_R_R(INS_sve_sel, emitSize, targetReg, maskReg, targetReg,
falseReg, opt, INS_SCALABLE_OPTS_UNPREDICATED);
break;
}
else
{
// At this point, target != embMaskOp1Reg != falseReg, so just go ahead
// and move the falseReg unpredicated into targetReg.
GetEmitter()->emitIns_R_R(INS_sve_movprfx, EA_SCALABLE, targetReg, falseReg);
}
}
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg, opt);
break;
}
case 2:
{
assert(instrIsRMW);
if (intrin.op3->IsVectorZero())
{
// If `falseReg` is zero, then move the first operand of `intrinEmbMask` in the
// destination using /Z.
assert(targetReg != embMaskOp2Reg);
GetEmitter()->emitIns_R_R_R(INS_sve_movprfx, emitSize, targetReg, maskReg, embMaskOp1Reg, opt);
// Finally, perform the actual "predicated" operation so that `targetReg` is the first operand
// and `embMaskOp2Reg` is the second operand.
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp2Reg, opt);
}
else if (targetReg != falseReg)
{
// If `targetReg` and `falseReg` are not same, then we need to move it to `targetReg` first
// so the `insEmbMask` operation can be merged on top of it.
if (falseReg != embMaskOp1Reg)
{
// At the point, targetReg != embMaskOp1Reg != falseReg
if (HWIntrinsicInfo::IsOptionalEmbeddedMaskedOperation(intrinEmbMask.id))
{
// If the embedded instruction supports optional mask operation, use the "unpredicated"
// version of the instruction, followed by "sel" to select the active lanes.
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, embMaskOp1Reg,
embMaskOp2Reg, opt, INS_SCALABLE_OPTS_UNPREDICATED);
}
else
{
// If the instruction just has "predicated" version, then move the "embMaskOp1Reg"
// into targetReg. Next, do the predicated operation on the targetReg and last,
// use "sel" to select the active lanes based on mask, and set inactive lanes
// to falseReg.
assert(targetReg != embMaskOp2Reg);
assert(HWIntrinsicInfo::IsEmbeddedMaskedOperation(intrinEmbMask.id));
GetEmitter()->emitIns_R_R(INS_sve_movprfx, EA_SCALABLE, targetReg, embMaskOp1Reg);
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp2Reg,
opt);
}
GetEmitter()->emitIns_R_R_R_R(INS_sve_sel, emitSize, targetReg, maskReg, targetReg,
falseReg, opt, INS_SCALABLE_OPTS_UNPREDICATED);
break;
}
else if (targetReg != embMaskOp1Reg)
{
// embMaskOp1Reg is same as `falseReg`, but not same as `targetReg`. Move the
// `embMaskOp1Reg` i.e. `falseReg` in `targetReg`, using "unpredicated movprfx", so the
// subsequent `insEmbMask` operation can be merged on top of it.
GetEmitter()->emitIns_R_R(INS_sve_movprfx, EA_SCALABLE, targetReg, falseReg);
}
// Finally, perform the actual "predicated" operation so that `targetReg` is the first operand
// and `embMaskOp2Reg` is the second operand.
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp2Reg, opt);
}
else
{
// Just perform the actual "predicated" operation so that `targetReg` is the first operand
// and `embMaskOp2Reg` is the second operand.
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp2Reg, opt);
}
break;
}
case 3:
{
assert(instrIsRMW);
assert(HWIntrinsicInfo::IsFmaIntrinsic(intrinEmbMask.id));
assert(falseReg != embMaskOp3Reg);
// For FMA, the operation we are trying to perform is:
// result = op1 + (op2 * op3)
//
// There are two instructions that can be used depending on which operand's register,
// optionally, will store the final result.
//
// 1. If the result is stored in the operand that was used as an "addend" in the operation,
// then we use `FMLA` format:
// reg1 = reg1 + (reg2 * reg3)
//
// 2. If the result is stored in the operand that was used as a "multiplicand" in the operation,
// then we use `FMAD` format:
// reg1 = (reg1 * reg2) + reg3
//
// Check if the result's register is same as that of one of the operand's register and accordingly
// pick the appropriate format. Suppose `targetReg` holds the result, then we have following cases:
//
// Case# 1: Result is stored in the operand that held the "addend"
// targetReg == reg1
//
// We generate the FMLA instruction format and no further changes are needed.
//
// Case# 2: Result is stored in the operand `op2` that held the "multiplicand"
// targetReg == reg2
//
// So we basically have an operation:
// reg2 = reg1 + (reg2 * reg3)
//
// Since, the result will be stored in the "multiplicand", we pick format `FMAD`.
// Then, we rearrange the operands to ensure that the operation is done correctly.
// reg2 = reg1 + (reg2 * reg3) // to start with
// reg2 = reg3 + (reg2 * reg1) // swap reg1 <--> reg3
// reg1 = reg3 + (reg1 * reg2) // swap reg1 <--> reg2
// reg1 = (reg1 * reg2) + reg3 // rearrange to get FMAD format
//
// Case# 3: Result is stored in the operand `op3` that held the "multiplier"
// targetReg == reg3
//
// So we basically have an operation:
// reg3 = reg1 + (reg2 * reg3)
// Since, the result will be stored in the "multiplier", we again pick format `FMAD`.
// Then, we rearrange the operands to ensure that the operation is done correctly.
// reg3 = reg1 + (reg2 * reg3) // to start with
// reg1 = reg3 + (reg2 * reg1) // swap reg1 <--> reg3
// reg1 = (reg1 * reg2) + reg3 // rearrange to get FMAD format
bool useAddend = true;
if (targetReg == embMaskOp2Reg)
{
// Case# 2
useAddend = false;
std::swap(embMaskOp1Reg, embMaskOp3Reg);
std::swap(embMaskOp1Reg, embMaskOp2Reg);
}
else if (targetReg == embMaskOp3Reg)
{
// Case# 3
useAddend = false;
std::swap(embMaskOp1Reg, embMaskOp3Reg);
}
else
{
// Case# 1
}
switch (intrinEmbMask.id)
{
case NI_Sve_FusedMultiplyAdd:
insEmbMask = useAddend ? INS_sve_fmla : INS_sve_fmad;
break;
case NI_Sve_FusedMultiplyAddNegated:
insEmbMask = useAddend ? INS_sve_fnmla : INS_sve_fnmad;
break;
case NI_Sve_FusedMultiplySubtract:
insEmbMask = useAddend ? INS_sve_fmls : INS_sve_fmsb;
break;
case NI_Sve_FusedMultiplySubtractNegated:
insEmbMask = useAddend ? INS_sve_fnmls : INS_sve_fnmsb;
break;
case NI_Sve_MultiplyAdd:
insEmbMask = useAddend ? INS_sve_mla : INS_sve_mad;
break;
case NI_Sve_MultiplySubtract:
insEmbMask = useAddend ? INS_sve_mls : INS_sve_msb;
break;
default:
unreached();
}
if (intrin.op3->IsVectorZero())
{
// If `falseReg` is zero, then move the first operand of `intrinEmbMask` in the
// destination using /Z.
assert(targetReg != embMaskOp2Reg);
assert(intrin.op3->isContained() || !intrin.op1->IsMaskAllBitsSet());
GetEmitter()->emitIns_R_R_R(INS_sve_movprfx, emitSize, targetReg, maskReg, embMaskOp1Reg, opt);
}
else
{
// Below are the considerations we need to handle:
//
// targetReg == falseReg && targetReg == embMaskOp1Reg
// fmla Zd, P/m, Zn, Zm
//
// targetReg == falseReg && targetReg != embMaskOp1Reg
// movprfx target, P/m, embMaskOp1Reg
// fmla target, P/m, embMaskOp2Reg, embMaskOp3Reg
//
// targetReg != falseReg && targetReg == embMaskOp1Reg
// sel target, P/m, embMaskOp1Reg, falseReg
// fmla target, P/m, embMaskOp2Reg, embMaskOp3Reg
//
// targetReg != falseReg && targetReg != embMaskOp1Reg
// sel target, P/m, embMaskOp1Reg, falseReg
// fmla target, P/m, embMaskOp2Reg, embMaskOp3Reg
//
// Note that, we just check if the targetReg/falseReg or targetReg/embMaskOp1Reg
// coincides or not.
if (targetReg != falseReg)
{
if (falseReg == embMaskOp1Reg)
{
// If falseReg value and embMaskOp1Reg value are same, then just mov the value
// to the target.
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, embMaskOp1Reg,
/* canSkip */ true);
}
else
{
// If falseReg value is not present in targetReg yet, move the inactive lanes
// into the targetReg using `sel`. Since this is RMW, the active lanes should
// have the value from embMaskOp1Reg
GetEmitter()->emitIns_R_R_R_R(INS_sve_sel, emitSize, targetReg, maskReg, embMaskOp1Reg,
falseReg, opt, INS_SCALABLE_OPTS_UNPREDICATED);
}
}
else if (targetReg != embMaskOp1Reg)
{
// If target already contains the values of `falseReg`, just merge the lanes from
// `embMaskOp1Reg`, again because this is RMW semantics.
GetEmitter()->emitIns_R_R_R(INS_sve_movprfx, emitSize, targetReg, maskReg, embMaskOp1Reg,
opt, INS_SCALABLE_OPTS_PREDICATE_MERGE);
}
}
// Finally, perform the desired operation.
GetEmitter()->emitIns_R_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp2Reg,
embMaskOp3Reg, opt);
break;
}
default:
unreached();
}
}
else
{
assert(!hasImmediateOperand);
switch (intrin.numOperands)
{
case 0:
GetEmitter()->emitIns_R(ins, emitSize, targetReg, opt);
break;
case 1:
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg, opt);
break;
case 2:
// This handles optimizations for instructions that have
// an implicit 'zero' vector of what would be the second operand.
if (HWIntrinsicInfo::SupportsContainment(intrin.id) && intrin.op2->isContained() &&
intrin.op2->IsVectorZero())
{
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg, opt);
}
else if (HWIntrinsicInfo::IsScalable(intrin.id))
{
assert(!node->IsEmbMaskOp());
if (HWIntrinsicInfo::IsExplicitMaskedOperation(intrin.id))
{
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
}
else
{
// This generates an unpredicated version
// Implicitly predicated should be taken care above `intrin.op2->IsEmbMaskOp()`
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt,
INS_SCALABLE_OPTS_UNPREDICATED);
}
}
else if (isRMW)
{
if (targetReg != op1Reg)
{
assert(targetReg != op2Reg);
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg,
/* canSkip */ true);
}
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op2Reg, opt);
}
else
{
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
}
break;
case 3:
if (isRMW)
{
if (targetReg != op1Reg)
{
assert(targetReg != op2Reg);
assert(targetReg != op3Reg);
GetEmitter()->emitIns_Mov(INS_mov, emitTypeSize(node), targetReg, op1Reg,
/* canSkip */ true);
}
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, opt);
}
else
{
GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, op3Reg, opt,
INS_SCALABLE_OPTS_UNPREDICATED);
}
break;
default:
unreached();
}
}
}
else
{
instruction ins = INS_invalid;
switch (intrin.id)
{
case NI_AdvSimd_AddWideningLower:
assert(varTypeIsIntegral(intrin.baseType));
if (intrin.op1->TypeGet() == TYP_SIMD8)
{
ins = varTypeIsUnsigned(intrin.baseType) ? INS_uaddl : INS_saddl;
}
else
{
assert(intrin.op1->TypeGet() == TYP_SIMD16);
ins = varTypeIsUnsigned(intrin.baseType) ? INS_uaddw : INS_saddw;
}
break;
case NI_AdvSimd_SubtractWideningLower:
assert(varTypeIsIntegral(intrin.baseType));
if (intrin.op1->TypeGet() == TYP_SIMD8)
{
ins = varTypeIsUnsigned(intrin.baseType) ? INS_usubl : INS_ssubl;
}
else
{
assert(intrin.op1->TypeGet() == TYP_SIMD16);
ins = varTypeIsUnsigned(intrin.baseType) ? INS_usubw : INS_ssubw;
}
break;
case NI_AdvSimd_AddWideningUpper:
assert(varTypeIsIntegral(intrin.baseType));
if (node->GetAuxiliaryType() == intrin.baseType)
{
ins = varTypeIsUnsigned(intrin.baseType) ? INS_uaddl2 : INS_saddl2;
}
else
{
ins = varTypeIsUnsigned(intrin.baseType) ? INS_uaddw2 : INS_saddw2;
}
break;
case NI_AdvSimd_SubtractWideningUpper:
assert(varTypeIsIntegral(intrin.baseType));
if (node->GetAuxiliaryType() == intrin.baseType)
{
ins = varTypeIsUnsigned(intrin.baseType) ? INS_usubl2 : INS_ssubl2;
}
else
{
ins = varTypeIsUnsigned(intrin.baseType) ? INS_usubw2 : INS_ssubw2;
}
break;
case NI_ArmBase_Yield:
{
ins = INS_yield;
break;
}
case NI_ArmBase_Arm64_MultiplyLongAdd:
ins = varTypeIsUnsigned(intrin.baseType) ? INS_umaddl : INS_smaddl;
break;
case NI_ArmBase_Arm64_MultiplyLongSub:
ins = varTypeIsUnsigned(intrin.baseType) ? INS_umsubl : INS_smsubl;
break;
case NI_Sve_StoreNarrowing:
ins = HWIntrinsicInfo::lookupIns(intrin.id, node->GetAuxiliaryType());
break;
default:
ins = HWIntrinsicInfo::lookupIns(intrin.id, intrin.baseType);
break;
}
assert(ins != INS_invalid);
switch (intrin.id)
{
case NI_AdvSimd_BitwiseSelect:
// Even though BitwiseSelect is an RMW intrinsic per se, we don't want to mark it as such
// since we can handle all possible allocation decisions for targetReg.
assert(!isRMW);
if (targetReg == op1Reg)
{
GetEmitter()->emitIns_R_R_R(INS_bsl, emitSize, targetReg, op2Reg, op3Reg, opt);
}
else if (targetReg == op2Reg)
{
GetEmitter()->emitIns_R_R_R(INS_bif, emitSize, targetReg, op3Reg, op1Reg, opt);
}
else if (targetReg == op3Reg)
{
GetEmitter()->emitIns_R_R_R(INS_bit, emitSize, targetReg, op2Reg, op1Reg, opt);
}
else
{
GetEmitter()->emitIns_Mov(INS_mov, emitSize, targetReg, op1Reg, /* canSkip */ false);
GetEmitter()->emitIns_R_R_R(INS_bsl, emitSize, targetReg, op2Reg, op3Reg, opt);
}
break;
case NI_Crc32_ComputeCrc32:
case NI_Crc32_ComputeCrc32C:
case NI_Crc32_Arm64_ComputeCrc32:
case NI_Crc32_Arm64_ComputeCrc32C:
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op1Reg, op2Reg, opt);
break;
case NI_AdvSimd_AbsoluteCompareLessThan:
case NI_AdvSimd_AbsoluteCompareLessThanOrEqual:
case NI_AdvSimd_CompareLessThan:
case NI_AdvSimd_CompareLessThanOrEqual:
case NI_AdvSimd_Arm64_AbsoluteCompareLessThan:
case NI_AdvSimd_Arm64_AbsoluteCompareLessThanScalar:
case NI_AdvSimd_Arm64_AbsoluteCompareLessThanOrEqual:
case NI_AdvSimd_Arm64_AbsoluteCompareLessThanOrEqualScalar:
case NI_AdvSimd_Arm64_CompareLessThan:
case NI_AdvSimd_Arm64_CompareLessThanScalar:
case NI_AdvSimd_Arm64_CompareLessThanOrEqual:
case NI_AdvSimd_Arm64_CompareLessThanOrEqualScalar:
GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op2Reg, op1Reg, opt);
break;
case NI_AdvSimd_FusedMultiplyAddScalar:
case NI_AdvSimd_FusedMultiplyAddNegatedScalar:
case NI_AdvSimd_FusedMultiplySubtractNegatedScalar:
case NI_AdvSimd_FusedMultiplySubtractScalar:
assert(opt == INS_OPTS_NONE);
GetEmitter()->emitIns_R_R_R_R(ins, emitSize, targetReg, op2Reg, op3Reg, op1Reg);
break;