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.gitmodules
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[submodule "submodules/verilog_sample_seldridge"]
path = submodules/verilog_sample_seldridge
url = https://github.com/seldridge/verilog
[submodule "submodules/verilog-ethernet"]
path = submodules/verilog-ethernet
url = https://github.com/alexforencich/verilog-ethernet
[submodule "submodules/parallella-oh"]
path = submodules/parallella-oh
url = https://github.com/parallella/oh
[submodule "submodules/FPGA-Bitcoin-Miner"]
path = submodules/FPGA-Bitcoin-Miner
url = https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner
[submodule "submodules/aws-fpga"]
path = submodules/aws-fpga
url = https://github.com/aws/aws-fpga
[submodule "submodules/xilinx-HLx_Examples"]
path = submodules/xilinx-HLx_Examples
url = https://github.com/Xilinx/HLx_Examples
[submodule "submodules/xilinx-ChaiDNN"]
path = submodules/xilinx-ChaiDNN
url = https://github.com/Xilinx/CHaiDNN
[submodule "submodules/arachne-pnr"]
path = submodules/arachne-pnr
url = https://github.com/YosysHQ/arachne-pnr
[submodule "submodules/yosys"]
path = submodules/yosys
url = https://github.com/YosysHQ/yosys
[submodule "submodules/icestorm"]
path = submodules/icestorm
url = https://github.com/cliffordwolf/icestorm
[submodule "submodules/netfpage"]
path = submodules/netfpage
url = https://github.com/NetFPGA/netfpga
[submodule "submodules/fpga-network-stack"]
path = submodules/fpga-network-stack
url = https://github.com/fpgasystems/fpga-network-stack
[submodule "submodules/timetoexplore"]
path = submodules/timetoexplore
url = https://github.com/WillGreen/timetoexplore
[submodule "submodules/irn-vivado-hls"]
path = submodules/irn-vivado-hls
url = https://github.com/NetSys/irn-vivado-hls
[submodule "submodules/P4HLS"]
path = submodules/P4HLS
url = https://github.com/engjefersonsantiago/P4HLS
[submodule "submodules/pciebench-netfpga"]
path = submodules/pciebench-netfpga
url = https://github.com/pcie-bench/pciebench-netfpga
[submodule "submodules/RFNoC-HLS-ATSC-RX"]
path = submodules/RFNoC-HLS-ATSC-RX
url = https://github.com/Xilinx/RFNoC-HLS-ATSC-RX
[submodule "submodules/Vivado_HLS"]
path = submodules/Vivado_HLS
url = https://github.com/engjefersonsantiago/Vivado_HLS
[submodule "xilinx_arty_a7/Arty"]
path = xilinx_arty_a7/Arty
url = https://github.com/Digilent/Arty
[submodule "submodules/verilog-axi"]
path = submodules/verilog-axi
url = https://github.com/alexforencich/verilog-axi
[submodule "submodules/ntl"]
path = submodules/ntl
url = https://github.com/acsl-technion/ntl