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[LoongArch] Implement COPY instruction between CFRs (llvm#69300)
With this patch, all CFRs can be used for register allocation.
1 parent ab301d8 commit 271087e

12 files changed

+227
-14
lines changed

‎llvm/lib/Target/LoongArch/LoongArch.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,9 +36,11 @@ bool lowerLoongArchMachineOperandToMCOperand(const MachineOperand &MO,
3636
FunctionPass *createLoongArchExpandAtomicPseudoPass();
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FunctionPass *createLoongArchISelDag(LoongArchTargetMachine &TM);
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FunctionPass *createLoongArchPreRAExpandPseudoPass();
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FunctionPass *createLoongArchExpandPseudoPass();
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void initializeLoongArchDAGToDAGISelPass(PassRegistry &);
4041
void initializeLoongArchExpandAtomicPseudoPass(PassRegistry &);
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void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &);
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void initializeLoongArchExpandPseudoPass(PassRegistry &);
4244
} // end namespace llvm
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#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCH_H

‎llvm/lib/Target/LoongArch/LoongArchExpandPseudoInsts.cpp‎

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@@ -29,6 +29,8 @@ using namespace llvm;
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#define LOONGARCH_PRERA_EXPAND_PSEUDO_NAME \
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"LoongArch Pre-RA pseudo instruction expansion pass"
32+
#define LOONGARCH_EXPAND_PSEUDO_NAME \
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"LoongArch pseudo instruction expansion pass"
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namespace {
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@@ -513,15 +515,134 @@ bool LoongArchPreRAExpandPseudo::expandFunctionCALL(
513515
return true;
514516
}
515517

518+
class LoongArchExpandPseudo : public MachineFunctionPass {
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public:
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const LoongArchInstrInfo *TII;
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static char ID;
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LoongArchExpandPseudo() : MachineFunctionPass(ID) {
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initializeLoongArchExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
530+
return LOONGARCH_EXPAND_PSEUDO_NAME;
531+
}
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private:
534+
bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
536+
MachineBasicBlock::iterator &NextMBBI);
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bool expandCopyCFR(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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};
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541+
char LoongArchExpandPseudo::ID = 0;
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bool LoongArchExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII =
545+
static_cast<const LoongArchInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool LoongArchExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
558+
while (MBBI != E) {
559+
MachineBasicBlock::iterator NMBBI = std::next(MBBI);
560+
Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
562+
}
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return Modified;
565+
}
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bool LoongArchExpandPseudo::expandMI(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
570+
switch (MBBI->getOpcode()) {
571+
case LoongArch::PseudoCopyCFR:
572+
return expandCopyCFR(MBB, MBBI, NextMBBI);
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}
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return false;
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}
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bool LoongArchExpandPseudo::expandCopyCFR(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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// Expand:
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// MBB:
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// fcmp.caf.s $dst, $fa0, $fa0 # set $dst 0(false)
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// bceqz $src, SinkBB
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// FalseBB:
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// fcmp.cueq.s $dst, $fa0, $fa0 # set $dst 1(true)
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// SinkBB:
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// fallthrough
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const BasicBlock *LLVM_BB = MBB.getBasicBlock();
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auto *FalseBB = MF->CreateMachineBasicBlock(LLVM_BB);
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auto *SinkBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MF->insert(++MBB.getIterator(), FalseBB);
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MF->insert(++FalseBB->getIterator(), SinkBB);
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Register DestReg = MI.getOperand(0).getReg();
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Register SrcReg = MI.getOperand(1).getReg();
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// DestReg = 0
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::SET_CFR_FALSE), DestReg);
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// Insert branch instruction.
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::BCEQZ))
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.addReg(SrcReg)
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.addMBB(SinkBB);
609+
// DestReg = 1
610+
BuildMI(FalseBB, DL, TII->get(LoongArch::SET_CFR_TRUE), DestReg);
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FalseBB->addSuccessor(SinkBB);
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SinkBB->splice(SinkBB->end(), &MBB, MI, MBB.end());
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SinkBB->transferSuccessors(&MBB);
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MBB.addSuccessor(FalseBB);
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MBB.addSuccessor(SinkBB);
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NextMBBI = MBB.end();
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MI.eraseFromParent();
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// Make sure live-ins are correctly attached to this new basic block.
624+
LivePhysRegs LiveRegs;
625+
computeAndAddLiveIns(LiveRegs, *FalseBB);
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computeAndAddLiveIns(LiveRegs, *SinkBB);
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return true;
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}
630+
516631
} // end namespace
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INITIALIZE_PASS(LoongArchPreRAExpandPseudo, "loongarch-prera-expand-pseudo",
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LOONGARCH_PRERA_EXPAND_PSEUDO_NAME, false, false)
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636+
INITIALIZE_PASS(LoongArchExpandPseudo, "loongarch-expand-pseudo",
637+
LOONGARCH_EXPAND_PSEUDO_NAME, false, false)
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521639
namespace llvm {
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523641
FunctionPass *createLoongArchPreRAExpandPseudoPass() {
524642
return new LoongArchPreRAExpandPseudo();
525643
}
644+
FunctionPass *createLoongArchExpandPseudoPass() {
645+
return new LoongArchExpandPseudo();
646+
}
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527648
} // end namespace llvm

‎llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -126,6 +126,23 @@ def PseudoST_CFR : Pseudo<(outs),
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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def PseudoLD_CFR : Pseudo<(outs CFR:$ccd),
128128
(ins GPR:$rj, grlenimm:$imm)>;
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// SET_CFR_{FALSE,TRUE}
131+
// These instructions are defined in order to avoid expensive check error if
132+
// regular instruction patterns are used.
133+
// fcmp.caf.s $dst, $fa0, $fa0
134+
def SET_CFR_FALSE : SET_CFR<0x0c100000, "fcmp.caf.s">;
135+
// fcmp.cueq.s $dst, $fa0, $fa0
136+
def SET_CFR_TRUE : SET_CFR<0x0c160000, "fcmp.cueq.s">;
137+
138+
// Pseudo instruction for copying CFRs.
139+
def PseudoCopyCFR : Pseudo<(outs CFR:$dst), (ins CFR:$src)> {
140+
let mayLoad = 0;
141+
let mayStore = 0;
142+
let hasSideEffects = 0;
143+
let Size = 12;
144+
}
145+
129146
} // Predicates = [HasBasicF]
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131148
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td‎

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@@ -218,3 +218,15 @@ class FP_STORE_2RI12<bits<32> op, RegisterClass rc = FPR32>
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: FPFmt2RI12<op, (outs), (ins rc:$fd, GPR:$rj, simm12:$imm12),
219219
"$fd, $rj, $imm12">;
220220
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
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222+
// This class is used to define `SET_CFR_{FALSE,TRUE}` instructions which are
223+
// used to expand `PseudoCopyCFR`.
224+
class SET_CFR<bits<32> op, string opcstr>
225+
: FP_CMP<op> {
226+
let isCodeGenOnly = 1;
227+
let fj = 0; // fa0
228+
let fk = 0; // fa0
229+
let AsmString = opcstr # "\t$cd, $$fa0, $$fa0";
230+
let OutOperandList = (outs CFR:$cd);
231+
let InOperandList = (ins);
232+
}

‎llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -77,6 +77,12 @@ void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
7777
.addReg(SrcReg, getKillRegState(KillSrc));
7878
return;
7979
}
80+
// CFR->CFR copy.
81+
if (LoongArch::CFRRegClass.contains(DstReg, SrcReg)) {
82+
BuildMI(MBB, MBBI, DL, get(LoongArch::PseudoCopyCFR), DstReg)
83+
.addReg(SrcReg, getKillRegState(KillSrc));
84+
return;
85+
}
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8187
// FPR->FPR copies.
8288
unsigned Opc;

‎llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -98,13 +98,6 @@ LoongArchRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
9898
if (TFI->hasBP(MF))
9999
markSuperRegs(Reserved, LoongArchABI::getBPReg()); // bp
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// FIXME: To avoid generating COPY instructions between CFRs, only use $fcc0.
102-
// This is required to work around the fact that COPY instruction between CFRs
103-
// is not provided in LoongArch.
104-
if (MF.getSubtarget<LoongArchSubtarget>().hasBasicF())
105-
for (size_t Reg = LoongArch::FCC1; Reg <= LoongArch::FCC7; ++Reg)
106-
markSuperRegs(Reserved, Reg);
107-
108101
assert(checkAllSuperRegsMarked(Reserved));
109102
return Reserved;
110103
}

‎llvm/lib/Target/LoongArch/LoongArchTargetMachine.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -180,6 +180,7 @@ LoongArchTargetMachine::getTargetTransformInfo(const Function &F) const {
180180
void LoongArchPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
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182182
void LoongArchPassConfig::addPreEmitPass2() {
183+
addPass(createLoongArchExpandPseudoPass());
183184
// Schedule the expansion of AtomicPseudos at the last possible moment,
184185
// avoiding the possibility for other passes to break the requirements for
185186
// forward progress in the LL/SC block.

‎llvm/test/CodeGen/LoongArch/O0-pipeline.ll‎

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@@ -69,6 +69,7 @@
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
7171
; CHECK-NEXT: Stack Frame Layout Analysis
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; CHECK-NEXT: LoongArch pseudo instruction expansion pass
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; CHECK-NEXT: LoongArch atomic pseudo instruction expansion pass
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter

‎llvm/test/CodeGen/LoongArch/cfr-copy.mir‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
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# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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# RUN: llc --mtriple=loongarch64 --mattr=+d %s -o - | FileCheck %s
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## Check the PseudoCopyCFR instruction expand.
5+
6+
--- |
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
8+
target triple = "loongarch64"
9+
10+
define void @test() {
11+
; CHECK-LABEL: test:
12+
; CHECK: # %bb.0:
13+
; CHECK-NEXT: fcmp.caf.s $fcc1, $fa0, $fa0
14+
; CHECK-NEXT: bceqz $fcc0, .LBB0_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fcmp.cueq.s $fcc1, $fa0, $fa0
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: movcf2gr $a0, $fcc1
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; CHECK-NEXT: ret
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ret void
21+
}
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...
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---
24+
name: test
25+
tracksRegLiveness: true
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body: |
27+
bb.0:
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liveins: $fcc0
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$fcc1 = COPY $fcc0
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$r4 = COPY $fcc1
32+
PseudoRET implicit killed $r4
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34+
...

‎llvm/test/CodeGen/LoongArch/cfr-pseudo-copy.mir‎

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@@ -0,0 +1,26 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc --mtriple=loongarch64 --mattr=+d --stop-after=postrapseudos %s \
3+
# RUN: -o - | FileCheck %s
4+
5+
## Check the COPY instruction between CFRs.
6+
## A pseudo (PseudoCopyCFR) is generated after postrapseudos pass.
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8+
...
9+
---
10+
name: test
11+
tracksRegLiveness: true
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body: |
13+
bb.0.entry:
14+
liveins: $fcc0
15+
16+
; CHECK-LABEL: name: test
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; CHECK: liveins: $fcc0
18+
; CHECK-NEXT: {{ $}}
19+
; CHECK-NEXT: $fcc1 = PseudoCopyCFR $fcc0
20+
; CHECK-NEXT: $r4 = MOVCF2GR killed $fcc1
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; CHECK-NEXT: PseudoRET implicit killed $r4
22+
$fcc1 = COPY $fcc0
23+
$r4 = COPY $fcc1
24+
PseudoRET implicit killed $r4
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26+
...

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