PCIe/NVME may not be described correctly

[qzed]

While the PCIe NVME drive seems to work well, it may not be described correctly. According to spec, it uses four PCIe lanes, stemming from controllers 1 and 2, each providing two lanes. This bonding together of controllers/lanes doesn't seem to be described properly in the DT yet. It apparently also requires some more driver work to do so.

At the moment, we may rely on UEFI configuring everything for us. This could lead to problems when suspending, where that config may be lost.

[qzed]

Quoting @andersson form aarch64-laptops IRC:

there's a register which defines if the phys work separately or in tandem...in tandem the initialization sequence needs to initialize both phys, in a slightly different way from when they are separate

I've decided to set num-lanes = <2> for now, which hopefully lets us avoid the second (unconfigured) phy. That way we can hopefully get a stable configuration for experimenting with suspend.