Changin the working frequency of the pynq-z2 board

[Clay-Cui]

Hi, I'm currently working with vexriscv on the tul pynq-z2 board. Unlike other people, I need to turn down the clock frequency of the core to make side-channel power measurements more feasible. The standard clock frequency is the clock provided by the Ethernet port, which is 125Mhz, is there a way to turn it down to like, 25Mhz?
`class BaseSoC(SoCCore):
def init(self, platform):
sys_clk_freq = int(125e6)

    # SoC with CPU
    SoCCore.__init__(self, platform,
        cpu_type                 = "vexriscv",
        cpu_variant              = "gfmulex_vector", 
        # cpu_cfu                  = "",         
        clk_freq                 = 125e6,
        ident                    = "LiteX VexRiscV Test SoC", ident_version=True,
        integrated_rom_size      = 0x8000,
        integrated_sram_size     = 0x4000,
        integrated_main_ram_size = 0x8000,
        uart_baudrate            = 19200)`

I tried to change the parameter sys_clk_freq and clk_freq in this python class, but it seems that I can't get correct behavior from the uart. Is it correct to change the uart baudrate here? Or I need to configure other things?
Thank you in advance!

[enjoy-digital]

Hi @Clay-Cui,

If you target file has a CRG similar to this: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/digilent_pynq_z1.py#L24-L55, reducing the sys_clk_freq to 25MHz should only be a matter of passing --sys-clk-freq=25e6 to your build command.

Changing only clk_freq parameter of SoCCore will not work since this is only an indication for SoCCore, the frequency change has to be done on the CRG.

If this is not working, please share some code to ease support.