Bump pythondata_cpu_minerva/sources subtree to d393a7b

Updated using 0.0.post155 from https://github.com/litex-hub/litex-data-auto

Author: cr1901

pythondata_cpu_minerva/__init__.py

@@ -24,7 +24,7 @@
 data_git_describe = "v0.0-139-gd393a7b"
 data_git_msg = """\
 commit d393a7b4367d2d2c1c5d26be03039cdee45010c0
-Author: Jean-François Nguyen <jf@jfng.fr>
+Author: Jean-François Nguyen <jf@jfng.fr>
 Date:   Wed Feb 19 19:28:12 2025 +0100
 
     gpr: remove unused d_{rp1,rp2}_en ports.

pythondata_cpu_minerva/sources/.env.toolchain

@@ -0,0 +1,2 @@
+AMARANTH_USE_YOSYS=builtin
+YOSYS=yowasp-yosys

pythondata_cpu_minerva/sources/.gitignore

@@ -1,10 +1,18 @@
 # Python
 __pycache__/
+__pypackages__/
+dist/
 /*.egg-info
 /.eggs
 
+# pdm
+/.pdm-plugins
+/.pdm-python
+/.venv
+/pdm.lock
+
 # tests
-**/test/spec_*/
+tests/spec_*/
 *.vcd
 *.gtkw
 

pythondata_cpu_minerva/sources/README.md

@@ -2,24 +2,15 @@
 
 ## A 32-bit RISC-V soft processor
 
-Minerva is a CPU core that currently implements the [RISC-V][1] RV32IM instruction set. Its microarchitecture is described in plain Python code using the [Amaranth][2] toolbox.
+Minerva is a CPU core that implements the [RISC-V][1] `RV32IMZicsr` instruction set. Its microarchitecture is described in plain Python code using [Amaranth HDL][2].
 
 ### Quick start
 
-Minerva requires Python 3.7+ and [Amaranth][2]. Installation instructions for Amaranth can be found [here](https://amaranth-lang.org/docs/amaranth/latest/install.html).
+    pipx install pdm
+    pdm install
+    pdm run python cli.py generate minerva.v
 
-    python setup.py install
-    python cli.py generate > minerva.v
-
-To use Minerva in its minimal configuration, you need to wire the following ports to `minerva_cpu`:
-
-* `clk`
-* `rst`
-* `ibus__*`
-* `dbus__*`
-* `external_interrupt`
-* `timer_interrupt`
-* `software_interrupt`
+See `pdm run python cli.py -h` for more options.
 
 ### Features
 
@@ -53,43 +44,27 @@ The following parameters can be used to configure the Minerva core.
 | `reset_address`   | `0x00000000`   | Reset vector address                               |
 | `with_icache`     | `False`        | Enable the instruction cache                       |
 | `icache_nways`    | `1`            | Number of ways in the instruction cache            |
-| `icache_nlines`   | `128`          | Number of lines in the instruction cache           |
+| `icache_nlines`   | `32`           | Number of lines in the instruction cache           |
 | `icache_nwords`   | `4`            | Number of words in a line of the instruction cache |
 | `icache_base`     | `0x00000000`   | Base of the instruction cache address space        |
 | `icache_limit`    | `0x80000000`   | Limit of the instruction cache address space       |
 | `with_dcache`     | `False`        | Enable the data cache                              |
 | `dcache_nways`    | `1`            | Number of ways in the data cache                   |
-| `dcache_nlines`   | `128`          | Number of lines in the data cache                  |
+| `dcache_nlines`   | `32`           | Number of lines in the data cache                  |
 | `dcache_nwords`   | `4`            | Number of words in a line of the data cache        |
 | `dcache_base`     | `0x00000000`   | Base of the data cache address space               |
 | `dcache_limit`    | `0x80000000`   | Limit of the data cache address space              |
+| `wrbuf_depth`     | `8`            | Depth of the write buffer FIFO                     |
 | `with_muldiv`     | `False`        | Enable RV32M support                               |
-| `with_debug`      | `False`        | Enable the Debug Module                            |
-| `with_trigger`    | `False`        | Enable the Trigger Module                          |
-| `nb_triggers`     | `8`            | Number of triggers                                 |
 | `with_rvfi`       | `False`        | Enable the riscv-formal interface                  |
 
-### Testing
-
-A riscv-formal testbench for Minerva is available [here](https://github.com/jfng/riscv-formal/tree/minerva/cores/minerva).
-
-### Possible improvements
-
-In no particular order:
-
-* RV64I
-* Floating Point Unit
-* Stateful branch prediction
-* MMU
-* ...
-
-If you are interested in sponsoring new features or improvements, get in touch at contact [at] lambdaconcept.com .
+A riscv-formal testbench for Minerva is available [here](https://github.com/minerva-cpu/riscv-formal/tree/minerva/cores/minerva).
 
 ### License
 
 Minerva is released under the permissive two-clause BSD license.
 See LICENSE file for full copyright and license information.
 
 [1]: https://riscv.org/specifications/
-[2]: https://github.com/amaranth-lang/amaranth/
+[2]: https://amaranth-lang.org/
 [3]: https://github.com/m-labs/lm32/

pythondata_cpu_minerva/sources/cli.py

@@ -1,10 +1,58 @@
 import argparse
-import warnings
 from amaranth import cli
+from amaranth.back import rtlil, cxxrtl, verilog
 
 from minerva.core import Minerva
 
 
+__all__ = ["main"]
+
+
+def main_parser(parser=None):
+    if parser is None:
+        parser = argparse.ArgumentParser()
+
+    p_action = parser.add_subparsers(dest="action")
+
+    p_generate = p_action.add_parser("generate",
+            help="generate RTLIL, Verilog or CXXRTL from the design")
+    p_generate.add_argument("-t", "--type",
+            dest="generate_type", metavar="LANGUAGE", choices=["il", "cc", "v"],
+            help="generate LANGUAGE (il for RTLIL, v for Verilog, cc for CXXRTL; "
+                 "default: file extension of FILE, if given)")
+    p_generate.add_argument("--no-src",
+            dest="emit_src", default=True, action="store_false",
+            help="suppress generation of source location attributes")
+    p_generate.add_argument("generate_file",
+            metavar="FILE", type=argparse.FileType("w"), nargs="?",
+            help="write generated code to FILE")
+
+    return parser
+
+
+def main_runner(parser, args, design, name="top"):
+    if args.action == "generate":
+        generate_type = args.generate_type
+        if generate_type is None and args.generate_file:
+            if args.generate_file.name.endswith(".il"):
+                generate_type = "il"
+            if args.generate_file.name.endswith(".cc"):
+                generate_type = "cc"
+            if args.generate_file.name.endswith(".v"):
+                generate_type = "v"
+        if generate_type is None:
+            parser.error("Unable to auto-detect language, specify explicitly with -t/--type")
+        if generate_type == "il":
+            output = rtlil.convert(design, name=name, emit_src=args.emit_src)
+        if generate_type == "cc":
+            output = cxxrtl.convert(design, name=name, emit_src=args.emit_src)
+        if generate_type == "v":
+            output = verilog.convert(design, name=name, emit_src=args.emit_src)
+        if args.generate_file:
+            args.generate_file.write(output)
+        else:
+            print(output)
+
 def main():
     parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
 
@@ -21,12 +69,6 @@ def main():
     parser.add_argument("--with-muldiv",
             default=False, action="store_true",
             help="enable RV32M support")
-    parser.add_argument("--with-debug",
-            default=False, action="store_true",
-            help="enable the Debug Module")
-    parser.add_argument("--with-trigger",
-            default=False, action="store_true",
-            help="enable the Trigger Module")
     parser.add_argument("--with-rvfi",
             default=False, action="store_true",
             help="enable the riscv-formal interface")
@@ -68,50 +110,20 @@ def main():
             type=int, default=8,
             help="write buffer depth")
 
-    trigger_group = parser.add_argument_group("trigger options")
-    trigger_group.add_argument("--nb-triggers",
-            type=int, default=8,
-            help="number of triggers")
-
-    cli.main_parser(parser)
+    main_parser(parser)
 
     args = parser.parse_args()
 
-    if args.with_debug and not args.with_trigger:
-        warnings.warn("Support for hardware breakpoints requires --with-trigger")
-
     cpu = Minerva(args.reset_addr,
             args.with_icache, args.icache_nways, args.icache_nlines, args.icache_nwords,
             args.icache_base, args.icache_limit,
             args.with_dcache, args.dcache_nways, args.dcache_nlines, args.dcache_nwords,
             args.dcache_base, args.dcache_limit,
             args.wrbuf_depth,
             args.with_muldiv,
-            args.with_debug,
-            args.with_trigger, args.nb_triggers,
             args.with_rvfi)
 
-    ports = [
-        cpu.external_interrupt, cpu.timer_interrupt, cpu.software_interrupt,
-        cpu.ibus.ack, cpu.ibus.adr, cpu.ibus.bte, cpu.ibus.cti, cpu.ibus.cyc, cpu.ibus.dat_r,
-        cpu.ibus.dat_w, cpu.ibus.sel, cpu.ibus.stb, cpu.ibus.we, cpu.ibus.err,
-        cpu.dbus.ack, cpu.dbus.adr, cpu.dbus.bte, cpu.dbus.cti, cpu.dbus.cyc, cpu.dbus.dat_r,
-        cpu.dbus.dat_w, cpu.dbus.sel, cpu.dbus.stb, cpu.dbus.we, cpu.dbus.err
-    ]
-
-    if args.with_debug:
-        ports += [cpu.jtag.tck, cpu.jtag.tdi, cpu.jtag.tdo, cpu.jtag.tms]
-
-    if args.with_rvfi:
-        ports += [
-            cpu.rvfi.valid, cpu.rvfi.order, cpu.rvfi.insn, cpu.rvfi.trap, cpu.rvfi.halt,
-            cpu.rvfi.intr, cpu.rvfi.mode, cpu.rvfi.ixl, cpu.rvfi.rs1_addr, cpu.rvfi.rs2_addr,
-            cpu.rvfi.rs1_rdata, cpu.rvfi.rs2_rdata, cpu.rvfi.rd_addr, cpu.rvfi.rd_wdata,
-            cpu.rvfi.pc_rdata, cpu.rvfi.pc_wdata, cpu.rvfi.mem_addr, cpu.rvfi.mem_rmask,
-            cpu.rvfi.mem_wmask, cpu.rvfi.mem_rdata, cpu.rvfi.mem_wdata
-        ]
-
-    cli.main_runner(parser, args, cpu, name="minerva_cpu", ports=ports)
+    main_runner(parser, args, cpu, name="minerva_cpu")
 
 
 if __name__ == "__main__":

pythondata_cpu_minerva/sources/minerva/arbiter.py

@@ -0,0 +1,80 @@
+from amaranth import *
+from amaranth.lib import wiring
+from amaranth.lib.wiring import In, Out
+
+from amaranth_soc import wishbone
+
+
+__all__ = ["WishboneArbiter"]
+
+
+class WishboneArbiter(wiring.Component):
+    bus: Out(wishbone.Signature(addr_width=30, data_width=32, granularity=8,
+                                features=("err", "cti", "bte")))
+
+    def __init__(self):
+        self._port_map = dict()
+        super().__init__()
+
+    def port(self, priority):
+        if not isinstance(priority, int) or priority < 0:
+            raise TypeError("Priority must be a non-negative integer, not '{!r}'"
+                            .format(priority))
+        if priority in self._port_map:
+            raise ValueError("Conflicting priority: '{!r}'".format(priority))
+        port = wishbone.Interface(addr_width=30, data_width=32, granularity=8,
+                                  features=("err", "cti", "bte"))
+        self._port_map[priority] = port
+        return port
+
+    def elaborate(self, platform):
+        m = Module()
+
+        ports = [port for priority, port in sorted(self._port_map.items())]
+
+        req = Signal(len(ports))
+        gnt = Signal.like(req)
+
+        with m.If(~self.bus.cyc):
+            for i, port in enumerate(ports):
+                m.d.sync += req[i].eq(port.cyc)
+
+        m.d.comb += gnt.eq(req & (-req)) # isolate rightmost 1-bit
+
+        bus_adr_mux   = 0
+        bus_dat_w_mux = 0
+        bus_sel_mux   = 0
+        bus_cyc_mux   = 0
+        bus_stb_mux   = 0
+        bus_we_mux    = 0
+        bus_cti_mux   = 0
+        bus_bte_mux   = 0
+
+        for i, port in enumerate(ports):
+            bus_adr_mux   |= Mux(gnt[i], port.adr,   0)
+            bus_dat_w_mux |= Mux(gnt[i], port.dat_w, 0)
+            bus_sel_mux   |= Mux(gnt[i], port.sel,   0)
+            bus_cyc_mux   |= Mux(gnt[i], port.cyc,   0)
+            bus_stb_mux   |= Mux(gnt[i], port.stb,   0)
+            bus_we_mux    |= Mux(gnt[i], port.we,    0)
+            bus_cti_mux   |= Mux(gnt[i], port.cti,   0)
+            bus_bte_mux   |= Mux(gnt[i], port.bte,   0)
+
+            m.d.comb += [
+                port.dat_r.eq(self.bus.dat_r),
+                port.ack  .eq(self.bus.ack & gnt[i]),
+                port.err  .eq(self.bus.err & gnt[i]),
+            ]
+
+        m.d.comb += [
+            self.bus.adr  .eq(bus_adr_mux),
+            self.bus.dat_w.eq(bus_dat_w_mux),
+            self.bus.sel  .eq(bus_sel_mux),
+            self.bus.cyc  .eq(bus_cyc_mux),
+            self.bus.stb  .eq(bus_stb_mux),
+            self.bus.we   .eq(bus_we_mux),
+            self.bus.cti  .eq(bus_cti_mux),
+            self.bus.bte  .eq(bus_bte_mux),
+        ]
+
+        return m