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This patch teaches x86 fast-isel to generate the native div/idiv instructions
for the sdiv/srem/udiv/urem bitcode instructions. This is done for the i8, i16, and i32 types, as well as i64 for the x86_64 target. Patch by Jim Stichnoth git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179715 91177308-0d34-0410-b5e6-96231b3b80d8
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‎lib/Target/X86/X86FastISel.cpp

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Original file line numberDiff line numberDiff line change
@@ -107,6 +107,8 @@ class X86FastISel : public FastISel {
107107

108108
bool X86SelectShift(const Instruction *I);
109109

110+
bool X86SelectDivRem(const Instruction *I);
111+
110112
bool X86SelectSelect(const Instruction *I);
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112114
bool X86SelectTrunc(const Instruction *I);
@@ -1235,6 +1237,124 @@ bool X86FastISel::X86SelectShift(const Instruction *I) {
12351237
return true;
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}
12371239

1240+
bool X86FastISel::X86SelectDivRem(const Instruction *I) {
1241+
const static unsigned NumTypes = 4; // i8, i16, i32, i64
1242+
const static unsigned NumOps = 4; // SDiv, SRem, UDiv, URem
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const static bool S = true; // IsSigned
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const static bool U = false; // !IsSigned
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const static unsigned Copy = TargetOpcode::COPY;
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// For the X86 DIV/IDIV instruction, in most cases the dividend
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// (numerator) must be in a specific register pair highreg:lowreg,
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// producing the quotient in lowreg and the remainder in highreg.
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// For most data types, to set up the instruction, the dividend is
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// copied into lowreg, and lowreg is sign-extended or zero-extended
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// into highreg. The exception is i8, where the dividend is defined
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// as a single register rather than a register pair, and we
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// therefore directly sign-extend or zero-extend the dividend into
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// lowreg, instead of copying, and ignore the highreg.
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const static struct DivRemEntry {
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// The following portion depends only on the data type.
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const TargetRegisterClass *RC;
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unsigned LowInReg; // low part of the register pair
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unsigned HighInReg; // high part of the register pair
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// The following portion depends on both the data type and the operation.
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struct DivRemResult {
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unsigned OpDivRem; // The specific DIV/IDIV opcode to use.
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unsigned OpSignExtend; // Opcode for sign-extending lowreg into
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// highreg, or copying a zero into highreg.
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unsigned OpCopy; // Opcode for copying dividend into lowreg, or
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// zero/sign-extending into lowreg for i8.
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unsigned DivRemResultReg; // Register containing the desired result.
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bool IsOpSigned; // Whether to use signed or unsigned form.
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} ResultTable[NumOps];
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} OpTable[NumTypes] = {
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{ &X86::GR8RegClass, X86::AX, 0, {
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{ X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S }, // SDiv
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{ X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem
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{ X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U }, // UDiv
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{ X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem
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}
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}, // i8
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{ &X86::GR16RegClass, X86::AX, X86::DX, {
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{ X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv
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{ X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem
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{ X86::DIV16r, X86::MOV16r0, Copy, X86::AX, U }, // UDiv
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{ X86::DIV16r, X86::MOV16r0, Copy, X86::DX, U }, // URem
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}
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}, // i16
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{ &X86::GR32RegClass, X86::EAX, X86::EDX, {
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{ X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv
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{ X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S }, // SRem
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{ X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv
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{ X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem
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}
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}, // i32
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{ &X86::GR64RegClass, X86::RAX, X86::RDX, {
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{ X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv
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{ X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem
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{ X86::DIV64r, X86::MOV64r0, Copy, X86::RAX, U }, // UDiv
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{ X86::DIV64r, X86::MOV64r0, Copy, X86::RDX, U }, // URem
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}
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}, // i64
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};
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MVT VT;
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if (!isTypeLegal(I->getType(), VT))
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return false;
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unsigned TypeIndex, OpIndex;
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switch (VT.SimpleTy) {
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default: return false;
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case MVT::i8: TypeIndex = 0; break;
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case MVT::i16: TypeIndex = 1; break;
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case MVT::i32: TypeIndex = 2; break;
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case MVT::i64: TypeIndex = 3;
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if (!Subtarget->is64Bit())
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return false;
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break;
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}
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switch (I->getOpcode()) {
1318+
default: llvm_unreachable("Unexpected div/rem opcode");
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case Instruction::SDiv: OpIndex = 0; break;
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case Instruction::SRem: OpIndex = 1; break;
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case Instruction::UDiv: OpIndex = 2; break;
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case Instruction::URem: OpIndex = 3; break;
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}
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1325+
const DivRemEntry &TypeEntry = OpTable[TypeIndex];
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const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
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unsigned Op0Reg = getRegForValue(I->getOperand(0));
1328+
if (Op0Reg == 0)
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return false;
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unsigned Op1Reg = getRegForValue(I->getOperand(1));
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if (Op1Reg == 0)
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return false;
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// Move op0 into low-order input register.
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg);
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// Zero-extend or sign-extend into high-order input register.
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if (OpEntry.OpSignExtend) {
1339+
if (OpEntry.IsOpSigned)
1340+
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1341+
TII.get(OpEntry.OpSignExtend));
1342+
else
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(OpEntry.OpSignExtend), TypeEntry.HighInReg);
1345+
}
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// Generate the DIV/IDIV instruction.
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
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// Copy output register into result register.
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unsigned ResultReg = createResultReg(TypeEntry.RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Copy), ResultReg).addReg(OpEntry.DivRemResultReg);
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UpdateValueMap(I, ResultReg);
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1355+
return true;
1356+
}
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bool X86FastISel::X86SelectSelect(const Instruction *I) {
12391359
MVT VT;
12401360
if (!isTypeLegal(I->getType(), VT))
@@ -2084,6 +2204,11 @@ X86FastISel::TargetSelectInstruction(const Instruction *I) {
20842204
case Instruction::AShr:
20852205
case Instruction::Shl:
20862206
return X86SelectShift(I);
2207+
case Instruction::SDiv:
2208+
case Instruction::UDiv:
2209+
case Instruction::SRem:
2210+
case Instruction::URem:
2211+
return X86SelectDivRem(I);
20872212
case Instruction::Select:
20882213
return X86SelectSelect(I);
20892214
case Instruction::Trunc:

‎test/CodeGen/X86/fast-isel-divrem-x86-64.ll

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
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; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
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3+
define i64 @test_sdiv64(i64 %dividend, i64 %divisor) nounwind {
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entry:
5+
%result = sdiv i64 %dividend, %divisor
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ret i64 %result
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}
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; CHECK: test_sdiv64:
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; CHECK: cqto
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; CHECK: idivq
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define i64 @test_srem64(i64 %dividend, i64 %divisor) nounwind {
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entry:
15+
%result = srem i64 %dividend, %divisor
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ret i64 %result
17+
}
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; CHECK: test_srem64:
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; CHECK: cqto
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; CHECK: idivq
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define i64 @test_udiv64(i64 %dividend, i64 %divisor) nounwind {
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entry:
25+
%result = udiv i64 %dividend, %divisor
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ret i64 %result
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}
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; CHECK: test_udiv64:
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; CHECK: xorl
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; CHECK: divq
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define i64 @test_urem64(i64 %dividend, i64 %divisor) nounwind {
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entry:
35+
%result = urem i64 %dividend, %divisor
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ret i64 %result
37+
}
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; CHECK: test_urem64:
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; CHECK: xorl
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; CHECK: divq

‎test/CodeGen/X86/fast-isel-divrem.ll

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
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; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
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; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
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define i8 @test_sdiv8(i8 %dividend, i8 %divisor) nounwind {
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entry:
6+
%result = sdiv i8 %dividend, %divisor
7+
ret i8 %result
8+
}
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10+
; CHECK: test_sdiv8:
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; CHECK: movsbw
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; CHECK: idivb
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define i8 @test_srem8(i8 %dividend, i8 %divisor) nounwind {
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entry:
16+
%result = srem i8 %dividend, %divisor
17+
ret i8 %result
18+
}
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; CHECK: test_srem8:
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; CHECK: movsbw
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; CHECK: idivb
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24+
define i8 @test_udiv8(i8 %dividend, i8 %divisor) nounwind {
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entry:
26+
%result = udiv i8 %dividend, %divisor
27+
ret i8 %result
28+
}
29+
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; CHECK: test_udiv8:
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; CHECK: movzbw
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; CHECK: divb
33+
34+
define i8 @test_urem8(i8 %dividend, i8 %divisor) nounwind {
35+
entry:
36+
%result = urem i8 %dividend, %divisor
37+
ret i8 %result
38+
}
39+
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; CHECK: test_urem8:
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; CHECK: movzbw
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; CHECK: divb
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define i16 @test_sdiv16(i16 %dividend, i16 %divisor) nounwind {
45+
entry:
46+
%result = sdiv i16 %dividend, %divisor
47+
ret i16 %result
48+
}
49+
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; CHECK: test_sdiv16:
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; CHECK: cwtd
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; CHECK: idivw
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define i16 @test_srem16(i16 %dividend, i16 %divisor) nounwind {
55+
entry:
56+
%result = srem i16 %dividend, %divisor
57+
ret i16 %result
58+
}
59+
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; CHECK: test_srem16:
61+
; CHECK: cwtd
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; CHECK: idivw
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64+
define i16 @test_udiv16(i16 %dividend, i16 %divisor) nounwind {
65+
entry:
66+
%result = udiv i16 %dividend, %divisor
67+
ret i16 %result
68+
}
69+
70+
; CHECK: test_udiv16:
71+
; CHECK: xorl
72+
; CHECK: divw
73+
74+
define i16 @test_urem16(i16 %dividend, i16 %divisor) nounwind {
75+
entry:
76+
%result = urem i16 %dividend, %divisor
77+
ret i16 %result
78+
}
79+
80+
; CHECK: test_urem16:
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; CHECK: xorl
82+
; CHECK: divw
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84+
define i32 @test_sdiv32(i32 %dividend, i32 %divisor) nounwind {
85+
entry:
86+
%result = sdiv i32 %dividend, %divisor
87+
ret i32 %result
88+
}
89+
90+
; CHECK: test_sdiv32:
91+
; CHECK: cltd
92+
; CHECK: idivl
93+
94+
define i32 @test_srem32(i32 %dividend, i32 %divisor) nounwind {
95+
entry:
96+
%result = srem i32 %dividend, %divisor
97+
ret i32 %result
98+
}
99+
100+
; CHECK: test_srem32:
101+
; CHECK: cltd
102+
; CHECK: idivl
103+
104+
define i32 @test_udiv32(i32 %dividend, i32 %divisor) nounwind {
105+
entry:
106+
%result = udiv i32 %dividend, %divisor
107+
ret i32 %result
108+
}
109+
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; CHECK: test_udiv32:
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; CHECK: xorl
112+
; CHECK: divl
113+
114+
define i32 @test_urem32(i32 %dividend, i32 %divisor) nounwind {
115+
entry:
116+
%result = urem i32 %dividend, %divisor
117+
ret i32 %result
118+
}
119+
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; CHECK: test_urem32:
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; CHECK: xorl
122+
; CHECK: divl

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