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Commit 6bb00df

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Jim Grosbach
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X86: Remove TargetMachine CPU auto-detection.
This logic is properly in the realm of whatever is creating the TargetMachine. This makes plain 'llc foo.ll' consistent across heterogenous machines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206094 91177308-0d34-0410-b5e6-96231b3b80d8
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-285
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2 files changed

+15
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‎lib/Target/X86/X86Subtarget.cpp

+15-281
Original file line numberDiff line numberDiff line change
@@ -173,241 +173,6 @@ bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
173173
return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
174174
}
175175

176-
static bool OSHasAVXSupport() {
177-
#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
178-
|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
179-
#if defined(__GNUC__)
180-
// Check xgetbv; this uses a .byte sequence instead of the instruction
181-
// directly because older assemblers do not include support for xgetbv and
182-
// there is no easy way to conditionally compile based on the assembler used.
183-
int rEAX, rEDX;
184-
__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
185-
#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
186-
unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
187-
#else
188-
int rEAX = 0; // Ensures we return false
189-
#endif
190-
return (rEAX & 6) == 6;
191-
#else
192-
return false;
193-
#endif
194-
}
195-
196-
void X86Subtarget::AutoDetectSubtargetFeatures() {
197-
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
198-
unsigned MaxLevel;
199-
union {
200-
unsigned u[3];
201-
char c[12];
202-
} text;
203-
204-
if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
205-
MaxLevel < 1)
206-
return;
207-
208-
X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
209-
210-
if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
211-
if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); }
212-
if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); }
213-
if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); }
214-
if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); }
215-
if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
216-
if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
217-
if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
218-
if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
219-
X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX);
220-
}
221-
222-
bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
223-
bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
224-
225-
if ((ECX >> 1) & 0x1) {
226-
HasPCLMUL = true;
227-
ToggleFeature(X86::FeaturePCLMUL);
228-
}
229-
if ((ECX >> 12) & 0x1) {
230-
HasFMA = true;
231-
ToggleFeature(X86::FeatureFMA);
232-
}
233-
if (IsIntel && ((ECX >> 22) & 0x1)) {
234-
HasMOVBE = true;
235-
ToggleFeature(X86::FeatureMOVBE);
236-
}
237-
if ((ECX >> 23) & 0x1) {
238-
HasPOPCNT = true;
239-
ToggleFeature(X86::FeaturePOPCNT);
240-
}
241-
if ((ECX >> 25) & 0x1) {
242-
HasAES = true;
243-
ToggleFeature(X86::FeatureAES);
244-
}
245-
if ((ECX >> 29) & 0x1) {
246-
HasF16C = true;
247-
ToggleFeature(X86::FeatureF16C);
248-
}
249-
if (IsIntel && ((ECX >> 30) & 0x1)) {
250-
HasRDRAND = true;
251-
ToggleFeature(X86::FeatureRDRAND);
252-
}
253-
254-
if ((ECX >> 13) & 0x1) {
255-
HasCmpxchg16b = true;
256-
ToggleFeature(X86::FeatureCMPXCHG16B);
257-
}
258-
259-
if (IsIntel || IsAMD) {
260-
// Determine if bit test memory instructions are slow.
261-
unsigned Family = 0;
262-
unsigned Model = 0;
263-
X86_MC::DetectFamilyModel(EAX, Family, Model);
264-
if (IsAMD || (Family == 6 && Model >= 13)) {
265-
IsBTMemSlow = true;
266-
ToggleFeature(X86::FeatureSlowBTMem);
267-
}
268-
269-
// Determine if SHLD/SHRD instructions have higher latency then the
270-
// equivalent series of shifts/or instructions.
271-
// FIXME: Add Intel's processors that have SHLD instructions with very
272-
// poor latency.
273-
if (IsAMD) {
274-
IsSHLDSlow = true;
275-
ToggleFeature(X86::FeatureSlowSHLD);
276-
}
277-
278-
// If it's an Intel chip since Nehalem and not an Atom chip, unaligned
279-
// memory access is fast. We hard code model numbers here because they
280-
// aren't strictly increasing for Intel chips it seems.
281-
if (IsIntel &&
282-
((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
283-
// Jasper Froest
284-
(Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
285-
(Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
286-
(Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
287-
(Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
288-
(Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
289-
(Family == 6 && Model == 0x2A) || // SandyBridge
290-
(Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
291-
(Family == 6 && Model == 0x3A) || // IvyBridge
292-
(Family == 6 && Model == 0x3E) || // IvyBridge EP
293-
(Family == 6 && Model == 0x3C) || // Haswell
294-
(Family == 6 && Model == 0x3F) || // ...
295-
(Family == 6 && Model == 0x45) || // ...
296-
(Family == 6 && Model == 0x46))) { // ...
297-
IsUAMemFast = true;
298-
ToggleFeature(X86::FeatureFastUAMem);
299-
}
300-
301-
// Set processor type. Currently only Atom or Silvermont (SLM) is detected.
302-
if (Family == 6 &&
303-
(Model == 28 || Model == 38 || Model == 39 ||
304-
Model == 53 || Model == 54)) {
305-
X86ProcFamily = IntelAtom;
306-
307-
UseLeaForSP = true;
308-
ToggleFeature(X86::FeatureLeaForSP);
309-
}
310-
else if (Family == 6 &&
311-
(Model == 55 || Model == 74 || Model == 77)) {
312-
X86ProcFamily = IntelSLM;
313-
}
314-
315-
unsigned MaxExtLevel;
316-
X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
317-
318-
if (MaxExtLevel >= 0x80000001) {
319-
X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
320-
if ((EDX >> 29) & 0x1) {
321-
HasX86_64 = true;
322-
ToggleFeature(X86::Feature64Bit);
323-
}
324-
if ((ECX >> 5) & 0x1) {
325-
HasLZCNT = true;
326-
ToggleFeature(X86::FeatureLZCNT);
327-
}
328-
if (IsIntel && ((ECX >> 8) & 0x1)) {
329-
HasPRFCHW = true;
330-
ToggleFeature(X86::FeaturePRFCHW);
331-
}
332-
if (IsAMD) {
333-
if ((ECX >> 6) & 0x1) {
334-
HasSSE4A = true;
335-
ToggleFeature(X86::FeatureSSE4A);
336-
}
337-
if ((ECX >> 11) & 0x1) {
338-
HasXOP = true;
339-
ToggleFeature(X86::FeatureXOP);
340-
}
341-
if ((ECX >> 16) & 0x1) {
342-
HasFMA4 = true;
343-
ToggleFeature(X86::FeatureFMA4);
344-
}
345-
}
346-
}
347-
}
348-
349-
if (MaxLevel >= 7) {
350-
if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
351-
if (IsIntel && (EBX & 0x1)) {
352-
HasFSGSBase = true;
353-
ToggleFeature(X86::FeatureFSGSBase);
354-
}
355-
if ((EBX >> 3) & 0x1) {
356-
HasBMI = true;
357-
ToggleFeature(X86::FeatureBMI);
358-
}
359-
if ((EBX >> 4) & 0x1) {
360-
HasHLE = true;
361-
ToggleFeature(X86::FeatureHLE);
362-
}
363-
if (IsIntel && ((EBX >> 5) & 0x1)) {
364-
X86SSELevel = AVX2;
365-
ToggleFeature(X86::FeatureAVX2);
366-
}
367-
if (IsIntel && ((EBX >> 8) & 0x1)) {
368-
HasBMI2 = true;
369-
ToggleFeature(X86::FeatureBMI2);
370-
}
371-
if (IsIntel && ((EBX >> 11) & 0x1)) {
372-
HasRTM = true;
373-
ToggleFeature(X86::FeatureRTM);
374-
}
375-
if (IsIntel && ((EBX >> 16) & 0x1)) {
376-
X86SSELevel = AVX512F;
377-
ToggleFeature(X86::FeatureAVX512);
378-
}
379-
if (IsIntel && ((EBX >> 18) & 0x1)) {
380-
HasRDSEED = true;
381-
ToggleFeature(X86::FeatureRDSEED);
382-
}
383-
if (IsIntel && ((EBX >> 19) & 0x1)) {
384-
HasADX = true;
385-
ToggleFeature(X86::FeatureADX);
386-
}
387-
if (IsIntel && ((EBX >> 26) & 0x1)) {
388-
HasPFI = true;
389-
ToggleFeature(X86::FeaturePFI);
390-
}
391-
if (IsIntel && ((EBX >> 27) & 0x1)) {
392-
HasERI = true;
393-
ToggleFeature(X86::FeatureERI);
394-
}
395-
if (IsIntel && ((EBX >> 28) & 0x1)) {
396-
HasCDI = true;
397-
ToggleFeature(X86::FeatureCDI);
398-
}
399-
if (IsIntel && ((EBX >> 29) & 0x1)) {
400-
HasSHA = true;
401-
ToggleFeature(X86::FeatureSHA);
402-
}
403-
}
404-
if (IsAMD && ((ECX >> 21) & 0x1)) {
405-
HasTBM = true;
406-
ToggleFeature(X86::FeatureTBM);
407-
}
408-
}
409-
}
410-
411176
void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
412177
AttributeSet FnAttrs = MF->getFunction()->getAttributes();
413178
Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
@@ -426,54 +191,23 @@ void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
426191

427192
void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
428193
std::string CPUName = CPU;
429-
if (!FS.empty() || !CPU.empty()) {
430-
if (CPUName.empty()) {
431-
#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
432-
|| defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
433-
CPUName = sys::getHostCPUName();
434-
#else
435-
CPUName = "generic";
436-
#endif
437-
}
438-
439-
// Make sure 64-bit features are available in 64-bit mode. (But make sure
440-
// SSE2 can be turned off explicitly.)
441-
std::string FullFS = FS;
442-
if (In64BitMode) {
443-
if (!FullFS.empty())
444-
FullFS = "+64bit,+sse2," + FullFS;
445-
else
446-
FullFS = "+64bit,+sse2";
447-
}
448-
449-
// If feature string is not empty, parse features string.
450-
ParseSubtargetFeatures(CPUName, FullFS);
451-
} else {
452-
if (CPUName.empty()) {
453-
#if defined (__x86_64__) || defined(__i386__)
454-
CPUName = sys::getHostCPUName();
455-
#else
456-
CPUName = "generic";
457-
#endif
458-
}
459-
// Otherwise, use CPUID to auto-detect feature set.
460-
AutoDetectSubtargetFeatures();
461-
462-
// Make sure 64-bit features are available in 64-bit mode.
463-
if (In64BitMode) {
464-
if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); }
465-
if (!HasCMov) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); }
466-
467-
if (X86SSELevel < SSE2) {
468-
X86SSELevel = SSE2;
469-
ToggleFeature(X86::FeatureSSE1);
470-
ToggleFeature(X86::FeatureSSE2);
471-
}
472-
}
194+
if (CPUName.empty())
195+
CPUName = "generic";
196+
197+
// Make sure 64-bit features are available in 64-bit mode. (But make sure
198+
// SSE2 can be turned off explicitly.)
199+
std::string FullFS = FS;
200+
if (In64BitMode) {
201+
if (!FullFS.empty())
202+
FullFS = "+64bit,+sse2," + FullFS;
203+
else
204+
FullFS = "+64bit,+sse2";
473205
}
474206

475-
// CPUName may have been set by the CPU detection code. Make sure the
476-
// new MCSchedModel is used.
207+
// If feature string is not empty, parse features string.
208+
ParseSubtargetFeatures(CPUName, FullFS);
209+
210+
// Make sure the right MCSchedModel is used.
477211
InitCPUSchedModel(CPUName);
478212

479213
if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM)

‎lib/Target/X86/X86Subtarget.h

-4
Original file line numberDiff line numberDiff line change
@@ -235,10 +235,6 @@ class X86Subtarget final : public X86GenSubtargetInfo {
235235
/// subtarget options. Definition of function is auto generated by tblgen.
236236
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
237237

238-
/// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
239-
/// instruction.
240-
void AutoDetectSubtargetFeatures();
241-
242238
/// \brief Reset the features for the X86 target.
243239
void resetSubtargetFeatures(const MachineFunction *MF) override;
244240
private:

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